JPH0242693B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed control device for setting, storing, and canceling a speed of a constant speed traveling device for a vehicle that causes the vehicle to travel at a desired target set speed.

Typically, this type of device detects the current vehicle speed as a number of pulses and obtains an analog voltage proportional to the number of pulses as a vehicle speed signal. When the driver reaches a desired vehicle speed, he operates the constant speed travel set switch to set (store) the vehicle speed signal at that time in the memory circuit. The speed control device uses the set vehicle speed signal as a reference voltage for one of the comparison circuits, and adjusts the opening degree of the throttle valve in a direction such that the difference becomes zero based on the difference between this signal and the current vehicle speed.

In this type of device, when the driver continues to press the constant speed set switch while the vehicle is running at a constant speed and keeps the set switch closed, the vehicle speed gradually decreases and the vehicle speed at the moment when the set switch is opened is reset. It has a so-called deceleration set function that memorizes and shifts to constant speed driving. Furthermore, some vehicles have a so-called tap-up function in which the speed of the vehicle increases slightly when the driver momentarily activates the set switch while driving at a constant speed. In this way, it is possible to decelerate by holding down the set switch, and to increase speed by momentarily operating it.

However, with this tap-up function, the amount of increase in vehicle speed at one time is small at 1 to 5 km/h, so
In order to significantly increase the vehicle speed, the set switch must be operated repeatedly, making the operation complicated and also having the disadvantage that it takes a long time to reach the desired vehicle speed.

By the way, in general, constant speed running devices for vehicles are designed to automatically cancel constant speed running when the brake is operated, even if constant speed running is set, in order to prevent danger or the like. Therefore, some vehicles are equipped with a resume switch in order to subsequently return the vehicle speed to the memorized target vehicle speed.

An object of the present invention is to simplify the speed increasing operation by providing the above-mentioned resume switch with a speed increasing function during constant speed running.

In order to achieve the above object, a timer circuit that operates for a predetermined period of time in response to the operation of a resume switch, and an acceleration signal generation circuit that generates an acceleration signal when the operation of the resume switch exceeds the predetermined period of time are provided. The main point of the structure is to prepare for the disaster.

With the above configuration, when the driver wants to increase the speed while driving at a constant speed, the driver operates the resume switch, and when this operation time exceeds a predetermined time, the driver starts accelerating and operates the resume switch. If the vehicle speed continues to increase while the vehicle is in the vehicle, and when the desired vehicle speed is reached, the resume switch is turned off, the vehicle can resume constant speed driving at the current vehicle speed, achieving the initial objective. In addition, the present invention can be implemented with only a few additional components added to conventional equipment;
It has excellent practical effects.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. The frequency of the vehicle speed signal obtained from the reed switch 10, which is opened and closed by a permanent magnet (not shown) rotating at the same speed as the wheel speedometer cable, is determined by the FV conversion circuit (frequency-voltage conversion circuit) 2.
0, it is converted into a voltage corresponding to the frequency.

30 stores the voltage corresponding to the vehicle speed voltage signal (actual vehicle speed signal) Vv from the FV conversion circuit 20 by operating the set switch SW ₁ , and converts the voltage along with the vehicle speed voltage signal Vv around the voltage at the time when the storage was performed. This is a storage circuit (target vehicle speed storage means) 30 that outputs a changing storage voltage signal _VM . This memory circuit 30 includes an input resistor R ₅ , a memory capacitor C ₁ ,
The gate of FET F ₂ for impedance conversion is connected in series, and the drain of FETF ₂ is connected to constant voltage Vcc.
The source is grounded via resistor _R6 . _F1
is a FET for analog switch, the drain is connected to the gate of FET _F2 for impedance conversion,
A voltage obtained by dividing the constant voltage Vcc by resistors R ₃ and R ₄ is applied to the source. The gate of FET F ₁ is a resistor
Connected via R ₂ to the constant voltage Vcc and the collector of the transistor T ₁ . The base of this transistor _T1 is connected to a constant voltage Vcc via a resistor _R1 , and a diode _D1 is connected to a set switch _SW1 .
connected via.

Reference numeral 40 denotes a comparator circuit, in which the memory voltage signal V _M is applied to the inverting input terminal (-) of the comparator CM, and the CM
A constant voltage Vcc is connected to the non-inverting input terminal (+) of the resistor.
A comparison voltage Vx divided by R ₇ and R ₈ is applied. The output end of the CM is connected to a power amplifier 60 that drives a control solenoid SL ₁ of the vacuum actuator 50 . In addition, CM
The output terminal of is connected to constant voltage Vcc through resistor _R9 , and also connected to the integrating capacitor through resistor _R10 .
Connected to _C2 . The connection point between the integrating capacitor C ₂ and the resistor R ₁₀ is connected to the memory circuit 3 via the resistor R ₁₁ .
0 memory capacitor _C1 is connected to the input side of the memory capacitor C1.

Reference numeral 70 denotes a flip-flop circuit that maintains the setting/cancellation state of constant speed running, the input end of which is connected to the set switch SW ₁ , the resume switch SW ₂ , and the cancel switch SW ₃ , and the output end of the NAND gate 71 is connected to the non-input terminal of the comparator CM. A diode _D5 is connected to the inverting input terminal and the integrating capacitor _C2 , respectively.
_D6 , and the output end of another NAND gate 72 is connected to the release solenoid of the vacuum actuator 50 via the power amplifier 80.
Connected to SL ₂ .

90 is an acceleration signal generating circuit equipped with a timer circuit, and the timer operation is started by closing the resume switch _SW2 . When the closing time of the resume switch SW ₂ exceeds the set time of the timer circuit 90, the acceleration signal generating circuit 90 generates an "L" level signal which is an acceleration signal. This signal is passed through the transistor _T1 through the diodes _D2 and _D3 .
and the integrating capacitor _C2 .

100 is the OR gate for the safety circuit, and the input terminal is the resume switch SW ₂ and the cancel switch.
Each is connected to SW ₃ , and the output terminal is fed back to one input terminal.

In the above configuration, the operation will be explained next.

The number of times the reed switch 10 is opened and closed, that is, the frequency of the vehicle speed signal, is converted into a voltage corresponding to the frequency by the FV conversion circuit 20 and output as a vehicle speed voltage signal Vv.

Now, when memorizing the vehicle speed, the set switch
When SW ₁ is closed and a storage instruction signal is applied, transistor T ₁ is turned off, the gate potential of FET F ₁ rises, and conduction occurs between the drain and source of FET F ₁ . As a result, a source voltage obtained by dividing the constant voltage Vcc by the resistors R ₃ and R ₄ is applied to the capacitor C ₁ and the gate of the FET F ₂ . If this source voltage is the reference voltage Vr, the vehicle speed voltage Vv is applied to the other end of the capacitor _C1 , so the capacitor _C1
A charge corresponding to the potential difference |Vv−Vr| between the terminals is accumulated in . When the memory instruction signal is removed,
Since FET F ₁ is turned off again and the input impedance of FET F ₂ is high, one end of capacitor C ₁ connected to its gate becomes in a floating state.
The charge of capacitor _C1 is held at the charge immediately before the storage instruction signal is removed, and the vehicle speed voltage at this time Vv=
If Vv ₀ , the potential difference V of the capacitor C ₁ is held at the current value |Vv ₀ −Vr|. Therefore, FET
At the gate of F ₂ , Vv + V (Vv + | Vv ₀ − V |)
voltage is applied, and the corresponding voltage is applied to the FET
It is output as the memory voltage V _M from the source end of F ₂ .
If the storage voltage immediately after storage is V _M0 , the storage voltage is
V _M becomes higher as the vehicle speed increases and decreases as the vehicle speed decreases, with the voltage V _M0 as the center.

In the comparator circuit 40, a predetermined voltage Vx obtained by dividing a constant voltage Vcc by resistors R ₇ and R ₈ is applied to the non-inverting input terminal (+) of the comparator CM. Also,
The memory voltage V _M is applied to the inverting input terminal (-). Therefore, the output of the comparator CM becomes "H" level when V _M <Vx, and becomes "L" level when V _M >Vx. In response to this output, the power amplifier 60 is turned on when the output is at the "H" level and turned off when the output is at the "L" level.

Here, the divided voltage Vx by the resistors R ₇ and R ₈ is set a little higher than the reference voltage Vr by the resistors R ₃ and R ₄ mentioned above, and the divided voltage _V
Make Vx a little higher, and power amplifier 6
Immediately after 0 is stored, it is biased so that it becomes "on".

Therefore, the power amplifier 60 is turned on, energizing the control solenoid _SL1 of the vacuum actuator 50, and operating the throttle valve (not shown) in the opening direction. Incidentally, the vacuum actuator 50 is configured such that the opening degree of the throttle valve is determined by the energization time to the control solenoid _SL1 .

Next, the output of the comparator CM is integrated by the resistor R ₁₀ and the capacitor C ₂ , and the output is passed through the resistor R ₁₁ to the memory capacitor C ₁ of the memory circuit.
Feedback is provided to Due to this feedback, for example, when the vehicle speed decreases and the control solenoid SL ₁ is energized, the voltage of the integrating capacitor C ₂ gradually increases, and this voltage is added to the vehicle speed voltage Vv, which is the actual vehicle speed, via the resistor R ₁₁ . Since the voltage is applied to the memory capacitor _C1 , a signal indicating that the vehicle speed has increased is issued before the vehicle speed voltage Vv reaches the memory voltage V _M , which is the target speed, and the acceleration is suppressed, so the vehicle accelerates beyond the target speed. There is no such thing as too much. Conversely, if the vehicle speed increases too much, the output of comparator CM becomes L, so control solenoid SL ₁ is de-energized and the throttle valve operates in the closing direction, but the integrated voltage of capacitor C ₂ is also reduced. , before the vehicle speed decreases to the target speed, a signal indicating that the vehicle speed has decreased to the target speed is generated to prevent excessive deceleration. Note that the charge on this integrating capacitor _C2 is
When SW ₁ is closed, it is discharged through diode D ₇ .

Furthermore, since ripples are added to the vehicle speed voltage signal Vv, which is the output of the FV conversion circuit 20, and ripples due to the on/off signals of the comparator CM are also added to the feedback signal, the comparator
The output of the CM is controlled to quickly repeat "H" and "L", that is, duty-controlled.

In the flip-flop circuit 70, normally, the output terminal of the NAND gate 71 is held at the "H" level, and the output terminal of the NAND gate 72 is held at the "L" level. At this time, when the cancel switch SW ₃ is closed, the state is reversed, the output terminal of the NAND gate 71 becomes "L" level, the output terminal of the NAND gate 72 becomes "H" level, and the non-inverting input terminal of the comparator CM becomes "L" level. ” level, and discharges the charge in the integrating capacitor _C2 . Furthermore, power amplifier 80 is turned on and release solenoid SL ₂ is turned on.
energize and release the throttle valve. As a result, constant speed running is canceled. after that,
If you want to drive at a constant speed again at the speed before the release, close the resume switch SW ₂ and the NAND gate 71
The output of the NAND gate 72 is “H” and the output of the NAND gate 72 is “L”.
As a result, the release solenoid SL ₂ is de-energized and the reference voltage Vv is applied to the comparator CM to maintain the vehicle speed at the speed before release. Furthermore, if you want to drive at a constant speed at a new set vehicle speed, you can close the set switch _SW1 again and change the memorized voltage _VM .

Next, when the resume switch SW ₂ is closed, the acceleration signal generation circuit 9 including the timer circuit 90
The timer of the timer circuit 90 of 0 operates. If the closing time of the resume switch SW ₂ is shorter than the set time of the timer circuit 90, the above-mentioned vehicle speed is returned to the speed before the release. Further, when the closing time exceeds the set time, the acceleration signal generating circuit 90 generates an acceleration signal. This acceleration signal is an "L" level signal, and this signal is connected to the base of the transistor _T1 and the capacitor _C2 via diodes _D2 and _D3 . Therefore, the transistor _T1 is turned off, the FET _F1 is turned on, and the reference voltage Vr is applied to the base of the FET _F2 . That is, the source voltage V _M of FET F ₂ is V _M =
Therefore, the comparator CM compares the reference voltage Vr and the divided voltage Vx. At this time, as mentioned above, since Vx>Vr is set, the comparator
The output of the CM becomes "H" level, the control solenoid SL ₁ of the actuator 50 is turned on, the throttle opening becomes large, and the engine accelerates. This acceleration continues as long as the resume switch SW ₂ is closed, and when the desired speed is reached, the resume switch SW 2 is closed.
When SW ₂ is opened, a set signal is obtained by turning the transistor T ₁ from OFF to ON, and the vehicle speed is memorized again and the vehicle shifts to constant speed driving. At this time, the capacitor
_C2 is discharged via diode _D3 to prevent excessive feedback from being applied during the storage.

When the cancel switch SW ₃ is closed during the above-mentioned speed increase operation, the flip-flop circuit 70 is activated and the constant speed running is canceled, and the output of the safety circuit OR gate 100 is set to "L". and hold this. For this reason, the cancel switch
Even if SW ₃ is open, the flip-flop circuit 70
maintains the constant speed running state. This state is
This continues until the resume switch SW ₂ is once opened. Therefore, even if the stop switch SW ₂ remains closed during constant speed driving and does not return, constant speed driving can be canceled by closing the cancel switch SW ₃ , thereby preventing the danger of the vehicle not accelerating.

[Brief explanation of the drawing]

The drawing is a circuit diagram showing an embodiment of a vehicle speed control device according to the present invention. 20...FV conversion circuit, 30...memory circuit, 4
0...Comparison circuit, 50...Vacuum actuator, 90...Acceleration signal generation circuit with timer circuit, 100...Safety circuit, SW ₁ ...Set switch, SW ₂ ...Resume switch, SW ₃ ...Cancel switch.

Claims (1)

[Claims] 1. A comparison circuit that generates a speed difference signal when a speed difference occurs between a vehicle speed signal corresponding to the vehicle speed and a set vehicle speed signal corresponding to the desired set speed, and a comparison circuit that generates a speed difference signal upon receiving the speed difference signal. In a vehicle speed control device comprising an actuator that adjusts the opening degree of a throttle valve to increase or decrease the vehicle speed in the direction of eliminating a signal, and a resume switch that restores constant speed running once released, A vehicle speed control device comprising: a timer circuit that operates for a predetermined period of time in response to an operation; and an acceleration signal generation circuit that generates an acceleration signal when the resume switch is operated for a predetermined period of time or more.