JPH0241948B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing device that processes original images.

For example, a recording apparatus may record only a certain area of a document, or may record certain areas of each of two pages of a document on one page of recording paper. Conventionally, such trimming or overlaying has been performed by first outputting and displaying the entire scanned image of the document on a CRT, then specifying the area with a cursor, light pen, etc., and then performing image processing. However, this method has the disadvantage that real-time processing is difficult, a high-resolution CRT is required, and the component equipment is expensive.
Also, draw blind spots in a loop shape,
There is now a method for two-dimensionally detecting edges in a designated loop-shaped area based on the locus. However, this method also has the disadvantage that real-time processing is difficult, a page memory is required, and the device configuration is complicated and expensive.

In some copying apparatuses, a cursor lever is placed on a document table as an area specifying means for processing a specified image. However, since the cursor lever has a limited shape, there is a limit to the shape of the region designation, and there are drawbacks such as poor operability.

Further, even when it is desired to reproduce all images in a desired area of a document containing images of multiple colors in the desired color, the above-mentioned complicated area designation mechanism and troublesome operations are required.

The present invention has been made in view of the above points, and it is possible to print all images in a desired area of a document containing images in multiple colors in a desired color without requiring a complicated area specifying mechanism or troublesome operations. The purpose is to make it reproducible, and in detail, it includes a reading means that outputs a plurality of color signals by color-separating and reading the original image, and a reading means that outputs a plurality of color signals by color-separating and reading the original image, and a a discriminating means for discriminating an image area defined by a specific color; and processing for converting all the plurality of color signals in the image area into desired color signals according to the area discrimination by the discriminating means and outputting the desired color signals. The present invention provides an image processing apparatus having means.

Hereinafter, the present invention will be explained in detail based on the drawings.

FIG. 1 shows a color recording apparatus to which the present invention is applied. Here, let the manuscript MAT be A4 version, for example,
The original is printed in two colors: red and black. Manuscript MAT
The area specified above is specified using a loop of constant thickness. Such a document MAT is irradiated with light by a light source SOL, and the reflected light LM is reflected by a first reflecting mirror RM1 and a second reflecting mirror RM2, and then is irradiated onto a beam splitter BS by an imaging lens LNS. . In this beam splitter BS, short-wavelength blue light is transmitted, and long-wavelength red light is reflected.
to each of them. Therefore, the brightness of the blue light image is detected by the photoelectric converter PHB, and the brightness and darkness of the red light image is detected by the photoelectric converter PHR and converted into electrical signals. Each image information detected by both photoelectric converters PHB and PHR is clock pulse
The signals are sequentially outputted in time series according to CP1 and supplied to amplifiers APB and APR as a blue signal SAB and a red signal SAR, respectively. The amplified blue signal SB is converted into a digital binary blue signal BSB by a binarizer CDB and is supplied to a color discriminator DMC. Similarly, the amplified red signal SR is converted into a digital binary red signal BSR by another binarizer CDR and supplied to the color discriminator DMC. color discriminator
DMC is a binary blue signal BSB and a binary red signal
Color discrimination is performed based on BSR, blue data DBU,
Three color data of red data DRE and black data DBK are generated respectively.

The designated area is determined based on the blue data DBU obtained in this way. Furthermore, this blue data
Noise reduction is performed to enable area discrimination even if there is noise in the DBU. In other words, the blue data DBU is first compressed by the main scanning compressor CDM, and the compressed data DCM is further compressed by the sub-scanning compressor CDS to create the compressed data.
Get DCS. This compressed data DCS is sequentially stored in the first line memory ML1 in accordance with the clock pulse CP2. Further, the data stored in this line memory ML1 is read out in response to the clock pulse CP2, and the read data DM1 (3 bits) is supplied to the edge detector EDE, and 1 bit of it is sent to the second line memory ML2. supply This second line memory ML2 also receives data DM1 in response to the clock pulse CP2.
are stored sequentially, and the stored data are read out sequentially. The read data DM2 (3 bits) is supplied to the edge detector EDE, and 1 bit of the data is supplied to the third line memory ML3. According to the clock pulse CP2, data DM2 is stored in the third line memory ML3, and the read data DM3 (3 bits) is supplied to the edge detector EDE.

Three readout data DM with temporally shifted limits of the area specified by the blue loop on the manuscript MAT, that is, edge information.
1. Edge detector based on DM2 and DM3
Detected by EDE. Detected edge information
DE is supplied to the region detector DEA, and region data DM, which is the output data thereof, is supplied to the loop discriminator DCL and the fourth line memory ML4. This fourth line memory ML4 sequentially stores area data DM,
Further, the data stored there is read out and supplied to the data selector SDT as read data DM4. Now, the data selection control signal DCR, which is the output signal of the loop discriminator DCL, is sent to the data selector.
Supply to SDT. As a result, either the read data DM4 of the fourth line memory or the read data DM5 of the fifth line memory ML5 is selected as the output signal DOUT. This output signal
In order to use DOUT as information for determining the designated area, it is supplied to the data switch DSW and used as a data switch control signal. At the same time, it is supplied to the fifth line memory ML5 and stored during the reading period of the next one line.

Black data DBK obtained from the color discriminator DMC is stored in line memory MBK, and red data DRE is stored in another line memory MRE. Two sets of data groups consisting of pairs of read data DMB and DMR of both line memories MBK and MRE are supplied to the data switch DSW. This data switch DSW uses the output signal from the data selector SDT.
For example, black head
Black data DHB to HEB, and red head HER
The red data DHR is supplied to each. head
Let HEB be the inkjet head for black ink,
Also, let the head HER be an inkjet head for red ink. Both heads HEB and HER
can project ink based on the black data DHB and the red data DHR, and form a black and red color recorded image on recording paper (not shown) over the area specified in blue on the document MAT.

In addition, both line memories MBK and MRE are
This is provided to match the time relationship with data processing for obtaining the data switching control signal DOUT by data compression and edge detection for each line.

FIGS. 2A to 2E schematically show data at each stage of data processing in FIG. 1. As shown in FIG. 2A, on the manuscript MAT (A4 size), for example, draw a loop LP in blue to surround the area AER to be read. In addition, MER is the manuscript
The right end of MAT, OP1, is the missing part of the loop LP.
The document MAT with the specified area is looped in the main scanning direction m and in the sub-scanning direction s for each line.
Read the LP optically. Compressed data DCS obtained by subjecting the blue data DBU obtained by such reading to main scanning compression and sub-scanning compression is shown in FIG. 2B. Here, the missing part OP1 of the loop LP
Corresponding to this, a missing portion OP2 of one line is generated.
Edge detector based on compressed data DCS
The edge information DE detected by EDE is shown in FIG. 2C. In addition, here, the missing part OP3 is the missing part OP3.
This is the deletion and error of edge information DE of the leading edge due to No. 2.

The area detector DEA consists of one D-type flip-flop (hereinafter referred to as FF), and it detects edge information of the leading edge (left side of loop LP) in one line.
After setting with DE, trailing edge (right side of loop LP)
Reset with the edge information DE. in this way,
While T _ZK is in the set state of FF, which is set and reset by a pair of edge information from the leading edge and trailing edge, the specified area AER in that line
Indicates that it is within. In addition, in one line,
Multiple pairs of edge information DE may occur. Area data DM obtained by such an area detector DEA is shown in FIG. 2D. Here, the diagonal line is the area detector
Indicates T _ZK while the FF of DEA is in the set state. Therefore, depending on the missing part OP3 where there is no edge information DE of the leading edge, the area detector is installed on the left side of the original loop.
The FF of DEA is not set, but rather is set by the trailing edge information DE from the right side of the loop. The incorrectly set state of FF is the end of document reading corresponding to the right MER of the document MAT.
Continues until MER1. In addition, in Figure 2A, the extremely narrow part of the designated area AER by loop LP
There is NA. The detected edge information DE corresponding to this partial NA is the leading edge information NA as shown in FIG. 2C.
1, and there is no detection of trailing edge information. Therefore, with this leading edge information NA1, the FF of the area detector DEA is
is set, and the end of document reading is MER1.
The set state continues until In this way, the area detector DEA may output area data DM that is incorrectly indicating that a portion outside the specified area AER is actually within the specified area AER.

Therefore, in order to overcome such a malfunction, in the present invention, when the reading end end MER1 is detected while the area detector DEA is outputting a signal indicating that it is "within the specified area", 1. The edge information DE detected in the previous line is used as is. For example, the missing part OP3 in Figure 2C
For the 4th line in , the leading edge information of the previous line is
LBF is used as leading edge information. Therefore, the edge information DE for the line currently being read is temporarily stored in the fourth line memory ML4, and the detected edge information DE for the line one line before it is temporarily stored in the fifth line memory ML5.
When MER1 is detected "within the specified area", the edge information DE of one line before, which was stored in the memory ML5, is selected and outputted by the data selector SDT. The control output signal DOUT obtained through such processing and the area specified thereby are shown in diagonal lines in FIG. 2E. As is clear from this, designated area information indicating a shape similar to the designated area AER surrounded by the loop LP shown in FIG. 2A is obtained.

In addition, draw the loop LP directly on the manuscript MAT to create an area.
You may specify AER, but this is inconvenient if you do not want to contaminate the manuscript MAT. In such a case, you can place a transparent film plate on the original MAT and draw a loop LP on it using a dry ink marker or the like. It does not stain the manuscript MAT, and
This is convenient because the ink loop LP can be easily erased once recording is completed.

FIG. 3 specifically shows the circuit from both amplifiers APB and APR to the color discriminator DMC in FIG. 1. FIGS. 4A to 4K show signal waveforms at each part in FIG. 3. In both figures, the amplified blue signal SB is connected to the respective inverting input terminals of both comparators CB1 and CB2, and the amplified red signal SR is connected to both comparators CR1.
and the respective inverting input terminals of CR2. The threshold voltage VB1 of the first slice level, which is close to the dark level of the blue signal level, is connected to the non-inverting input terminal of the comparator CB1, and the threshold voltage VB2 of the second slice level, which is close to the bright level, is connected to the non-inverting input terminal of the comparator CB2. supply Similarly, the threshold voltage VR1 of the first slice level, which is close to the dark level of the red signal level, is applied to the non-inverting input terminal of the comparator CR1.
Further, a threshold voltage VR2 at a second slice level close to the bright level is supplied to the non-inverting input terminal of the comparator CR2. Both signals SB and SR are binarized by having the output of the comparator go high when it goes below these threshold voltages, and go low when it goes above the threshold voltage.

Now, assume that the original has the pattern shown in FIG. 4A.
Since the slice level is different for each color signal, the pulse width corresponding to the image of the original is sliced at the first slice level.
Narrower than those sliced at the second slice level. That is, the output signal BB1 of the comparator CB1 is higher than the output signal BB2 of the comparator CB2.
Output signal BR1 of CR1 is output signal of comparator CR2
Each pulse width is narrower than that of BR2.

The signals digitized in this way BB1, BB
2. Correspond to BR1 and BR2 respectively.
D of each of FF31, 33, 35 and 37
Supplied to the input terminal. A clock pulse CP is applied to each clock terminal CK of these FF31 to FF37.
3 are commonly supplied. Therefore, the output signal of the comparator
BB1, BB2, BR1 and BR2 are latched by FF31 to 37 corresponding to each signal depending on the appearance of clock pulse CP3, and these
Signals FB1, FB2, FR1, and FR2 are output from the respective Q output terminals of FFs 31 to 37. Signals FB2 and FR2 are supplied to AND gate AD1, and a blackout signal SBN is obtained by logical operation.
This signal SBN is at a high logic level only in the black pattern of the document. While supplying the black signal SBN to one input terminal of the AND gate AD2,
After being inverted by inverter IV, it is supplied to one input terminal of each of AND gates AD3 and AD4.
Furthermore, signal FB1 is connected to both AND gates AD2 and
The signal FR1 is supplied to the other input terminal of AD4, and the signal FR1 is supplied to the other input terminal of AND gate AD3. Then, the signal SBK from AND gate AD2 becomes a high logic level only in black patterns on the document, the signal SRE becomes a high logic level only in red patterns from AND gate AD3, and the signal SRE becomes a high logic level only in blue patterns from AND gate AD4. Signals SBU are obtained and supplied to the D input terminals of FFs 41, 43 and 45, respectively. A common clock pulse CP3 is supplied to the clock terminal CK of each of these FFs 41 to 45, and the appearance of this clock pulse CP3 causes the signals SBK, SRE and
The SBU is latched to FFs 41-45 and obtained as black data DBK, red data DRE and blue data DBU, respectively.

FIG. 5 shows a specific example of the main scanning compressor CDM in FIG. 1. Here, four FF51-54
are connected in cascade, and the Q output signals Q1, Q2, and Q3 of FFs 51, 52, and 53 are connected to an AND gate 55.
supply to. Also, Q output signals Q1, Q2 and Q4 of FFs 51, 52 and 54 are sent to an AND gate 56, and Q output signals Q1, Q3 and Q4 of FFs 51, 53 and 54 are sent to an AND gate 57.
Q output signals Q2, Q of FF52, 53 and 54
3 and Q4 are supplied to AND gate 58, respectively. A logic signal DMR1 obtained by a logical operation of an OR gate 59 based on the output signals of these AND gates 55 to 58 is supplied to one input terminal of both AND gates 60 and 61.

When synchronization signal SYNC1 is supplied to the clear terminal CLR of hexadecimal counter CT1, this counter CT1
The count data of becomes 0, and this counter CT1 counts the clock pulses CP3 introduced into its clock terminal CK. The 1/2 frequency divided signal 61 output from the output terminal Q _A of the counter CT1 and the 1/4 frequency divided signal 62 output from the output terminal Q _B are supplied to the AND gate 63, and the output signal T1 is applied to the AND gate 63. 64 to one input terminal, and
Signal 1 inverted by inverter 65 is supplied to the other input terminal of AND gate 60 . The logical sum signal 67 obtained by the OR gate 66 based on the output signals of the AND gates 60 and 64 is
68 D input terminal. A logic signal DMR2 obtained from the Q output terminal of the FF 68 is supplied to the other input terminal of both AND gates 61 and 64, respectively. The operation of obtaining main compressed data DCM from blue data DBU in this main scanning compressor CDM is as follows:
In the above configuration, this is done by commonly supplying the clock pulse CP3 to the FFs 51-54, 68 and the counter CT1.

FIGS. 6A to 6G show signal waveforms at various parts in FIG. 5. Now, assuming that the blue data DBU acquired from the original MAT is a signal as shown in FIG. 6D, the signals T1, DMR1, DMR shown in FIG. 5 are generated in response to the clock pulse CP3 shown in FIG.
2 and DCM become the signals shown in FIGS. 6C to 6G, respectively. Here, the four AND gates 55~
58 and the OR gate 59 form a 3/4 majority logic circuit, and if the number of data that takes a high logic level is large (3 or more out of 4), the group of compared data will have a high logic level as a whole. It is viewed as one large piece of data with logical levels. In this way, the present main scanning compressor CDM compresses data from, for example, 1728 bits per line to 1/8, or 216 bits, and obtains compressed data DCM using 6/8 majority logic.

FIG. 7 shows a specific example of the sub-scanning compressor CDS in FIG. 1. Here, the main compressed data DCM is
The output signal 71 is supplied to the 215-bit shift register SR1, and the output signal 71 is sent to the 216-bit shift register SR2.
The output signal 72 is supplied to a 216-bit shift register SR3, and these three cascaded shift registers SR1, SR2 and
A sequential output signal 73 is obtained by SR3. Main compressed data DCM and gates 74, 75 and 76
, output signal 71 of shift register SR1 is applied to AND gates 74, 75 and 77, and output signal 72 of shift register SR2 is applied to AND gates 74, 77.
6 and 77, output signal 73 of shift register SR3 is supplied to AND gates 75, 76 and 77, respectively. These four AND gates 74
Based on the output signals of ~77, an OR gate 78 performs a logical sum operation, and the output logic signal is
Supply DSR1 to AND gate 79 and 216
The output signal 80 is supplied to the bit shift register SR4 and the output signal 80 is supplied to the AND gate 79.
The signal is supplied to a 216-bit shift register SR5, and its output signal 81 is supplied to an AND gate 79. Output logic signal of AND gate 79
DSR2 (corresponding to compressed data DCS in Figure 1)
The data is supplied to a 216-bit shift register SR6 (part of the first line memory ML1), and sampled sub-compressed data DCS is obtained as its output.

A clock pulse that controls the operation of the main sub-scanning compressor CDS is sent to the clock terminal CK of the hexadecimal counter CT2.
Supply CP3. The counter CT2 counts the clock pulse CP3 and outputs the 1/2 frequency divided signal Q _A , 1/4 frequency divided signal Q _B and 1/8 frequency divided signal Q _C to the AND gate 82 .
to obtain the time signal TS1 of the AND output. Further, a synchronizing signal SYNC2 is supplied to the clear terminal CLR of the counter CT2 and the clock terminal CK of a separate hexadecimal counter CT3. Counter CT3 counts the synchronizing signal SYNC2, and divides the frequency by 1/2, Q _A and 1/4
Divided signal Q _B , 1/8 divided signal Q _C and 1/16 divided signal
Q _D is supplied to a decoder DEC to obtain a second time signal TS2 as its decoded output. Furthermore, the carry output signal of the hexadecimal counter CT3 is transferred to the inverter 83.
is supplied to the clear terminal CLR via the time signal TS3, and this signal is obtained as the third time signal TS3.

The first time signal TS1 is transferred to shift register SR1,
Commonly supplied to clock terminal CK of SR2 and SR3. Further, the first time signal TS1 and the second time signal TS2 are supplied to the AND gate 84, and the output signal LGS1 is sent to both shift registers SR4 and SR.
5 clock terminals in common. Further, the first time signal TS1 and the third time signal TS3 are supplied to an AND gate 85, and its output signal LGS2 is supplied to the clock terminal CK of the shift register SR6.

Here, the clock pulse CP3 is a signal for main scanning m, and is a pulse signal generated for each bit. Further, the synchronizing signal SYNC2 is a signal for sub-scanning s, and is a signal that causes the counter CT3 to count up every line. In response to the clock pulse CP3 and synchronization signal SYNC2 that control the main scanning and sub-scanning,
The CDS compresses the main compressed data DCM into data DCS with 1/12 the number of bits. The logic circuit LOG composed of four AND gates 74 to 77 and an OR gate 78 is compressed to 1/4 and is a 3/4 majority logic circuit. That is, the main compressed data DCM,
If any three of the four data output signals 71, 72 and 73 of the three shift registers SR1, SR2 and SR3 are at a high logic level, the output logic signal DSR1 is at a high logic level. Further, the AND gate 79 is a logic circuit that compresses data by 1/3. Therefore, logic circuit
The LOG and AND gate 79 perform a 9/12 majority logic operation.

In this way, by the sub-scanning compressor CDS,
Sub-compressed data by bulk processing every 12 lines
Get DCS.

FIG. 8 shows signal waveforms at various parts in FIG. 7. Here, if the period of the clock pulse CP is _TCP , the period _TSY1 of the synchronizing signal SYNC1 is _1728TCP . Further, if the period of the synchronization signal SYNC2 is T _SY2 , the period T _TS1 of the first time signal TS1 is 8T _CP , the period T TS2 of the second time signal _TS2 is 4T _SY2 , and the period T TS3 of the third time signal _TS3 is 12T It becomes _SY2 .

FIG. 9 shows details of the edge detection section in FIG. 1. Here, the output signal Q90 of the first line memory ML1 to which the sub-compressed data DSR2 is supplied is
The Q output signal Q91 is supplied to the D input terminal of FF91, and the Q output signal Q91 is supplied to the D input terminal of FF92 in the next stage.
Its Q output signal Q92 is obtained. The output signal Q of the second line memory ML2 to which this signal Q92 is supplied
93 is supplied to the D input terminal of FF94, and its Q output signal Q94 is supplied to the D input terminal of FF95 at the next stage to obtain its Q output signal Q95. Similarly, the third line memory is supplied with signal Q95.
The output signal Q96 of ML3 is supplied to the D input terminal of FF97, and the Q output signal Q97 is supplied to the next stage FF9.
8, and its Q output signal Q9
Get 8. In this configuration, reading data,
Read and latch operations are controlled by the sub-scan compressor.
Timing signal obtained by CDS (see Figure 7)
LGS2 and these line memories ML1 and ML2
and ML3 and FF91,92,94,95,9
This is done by commonly supplying the clock terminals CK of clocks 7 and 98.

Read data DM1 consisting of three signals Q90, Q91 and Q92, read data DM2 consisting of signals Q93, Q94 and Q95, signal Q96,
Read data DM3 consisting of Q97 and Q98 is supplied to edge detector EDE. Note that the logic circuit constituting this edge detector EDE is configured such that the parameters of read data DM1 are a, b, c, the parameters of read data DM2 are d, e, f, and the parameters of read data DM3 are g, h, i. Shown as a logical formula.

The logic output signal LGO1 of the logic circuit LGC1 is LGO1=e・g...(a+b+c)
(1) is given as. Further, the logic output LGO2 of the logic circuit LGC2 is expressed as LGO2=(d..).(a+b).(g+h).(.) (2). Furthermore, the logic output LGO3 of the logic circuit LGC3 is LGO3=a・e...(g+h+i)
(3) is given as.

These logic outputs LGO1, LGO2 and LGO
3, an OR gate 99 performs a logical sum operation to obtain edge detection information DE.

The pattern detected by the logic circuit LGC2 is shown in FIG. 10A, the pattern detected by the logic circuit LGC3 is shown in FIG. 10B, and the pattern detected by the logic circuit LGC2 is shown in FIG.
The patterns detected by 1 are shown in FIG. 10C, respectively.

Incidentally, the correspondence relationship between these parameters a to i and each element of a 3.times.3 matrix forming one pixel is shown in FIG. 10D. Edge information DE is obtained by such logical judgment of matrix formation.

Figure 11 shows edge detection information DE in Figure 1.
Specifically shows the circuit that obtains the output signal DOUT from
Figure 12A shows the signal waveform to explain its operation.
- Shown in D. Here, the edge information DE from the edge detector EDE and the third time signal TS3 obtained by the sub-scanning compressor CDS (see FIG. 7) are supplied to the AND gate 111 of the area detector DEA. The output signal 112 is supplied to the clock terminal CK of the FF 113. The output signal of FF113 is supplied to its D input terminal, and the region data DM, which is its Q output signal, is supplied to FF1 configuring the loop discriminator DCL.
14 D input terminal. Third time signal TS
is inverted by an inverter 115, and then supplied to the clock terminal CK of the FF 114 and the AND gate 116 of the data selector SDT. Third time signal TS3
and area data DM are supplied to the AND gate 117, and an OR gate 118 performs a logical OR operation based on both the output signals of the AND gates 116 and 117, and then outputs the output signal 119 to the fourth line memory ML.
Supply to 4. Data is read in response to the clock pulse CP3 supplied to the clock terminal CK of the line memory ML4, and the data DM4 read out at the same time is sent to the AND gates 116 and 121.
supply to. Also, FF1 in the loop discriminator DCL
The data selection control signal is the Q output signal of 14.
The DCR is supplied to another AND gate 122, and after being inverted by an inverter 123, it is supplied to an AND gate 121. After the OR gate 124 performs a logical OR operation based on both the output signals of the AND gates 121 and 122, the output signal DOUT
is supplied to the fifth line memory ML5. Data reading in this line memory ML5 is performed in accordance with a clock pulse CP3 supplied to its clock terminal CK, and the data DM5 read in response to the clock pulse CP3 is read out by an AND gate 1.
22.

In addition, in the period T _SN of the third time signal TS3,
11 lines, 1 line is processed in period T _SP , that is, 12 lines are processed during one period.

FIG. 13 shows a flowchart for explaining the operation of FIG. 11. Hereinafter, the explanation will be made according to FIG. 13 with reference to FIGS. 11 and 12.

First, it is determined whether or not the line currently being main scanned has reached the line end, that is, the end of reading MER1 (step 131). If the determination is negative, it is determined whether the line being read is the 12th line (step 133). If the determination is positive, determine whether edge detection has been performed (step
135). If the determination is affirmative, it is determined whether the FFA (referring to the Q output logic state of the FF 113 included in the area detector DEA, the same applies hereinafter) is at the low logic level "0" (step 137). If affirmative judgment, that is, FFA=0
The FF 113 is set (step 139), and if the determination is negative, that is, FFA=1, the FF 113 is reset (step 141), and the process proceeds to step 143 as in the case of the negative determination in step 135. In step 143, after storing the FFA in the fourth line memory ML4, as in the case of a negative judgment in step 133,
It is determined whether the output logic state (representing the output logic state, and so on) is a low logic level "0" (step 145). If the judgment is affirmative, the read data DM4 from the fourth line memory ML4 is set as the output signal DOUT (step
147) and store this data DM4 in the fifth line memory ML5 (step 149).
A data selector SDT is controlled. If the determination is negative in step 145, the read data DM5 from the fifth line memory ML5 is output as the output signal.
The data selector SDT is controlled to set the data as DOUT (step 151) and store the data DM5 in the fifth line memory ML5 again (step 153). After such data selection, the process returns to step 131.

If the determination in step 131 is affirmative, it means that the reading end end MER1 of the reading line has been detected, and it is then determined whether the reading end line is the 12th line (step 161). If the determination is positive, determine whether FFA is “0” (step 163);
If FFA=0 (affirmative), reset the FF 114 forming the loop discriminator DCL (step 165),
If FFA=1 (: negative), FF114 is set (step 167), and then, at the same time as the negative judgment is made in step 161, the process moves to step 167,
Reset FF113. Then, in step 169, wait until the read is no longer at the end of the line,
After that, step to the next line.
Move to 133.

Based on the data switching control signal DOUT obtained by such edge detection processing, red recording or black recording can be performed in the specified area AER for each line according to the timing. Or specified area
Processing that does not record the AER at all is also possible, such as trimming or overlaying the original.
This can be easily done by simply drawing a blue loop LP on the MAT. Furthermore, even if a portion of the loop is missing or there is a reading error, it is possible to specify an area using a loop having an approximate shape.

Note that, as described above, the designated area is determined by the loop LP based on the compressed data DCS, but the area may be determined using the blue data DBU itself without data compression. That is, edge detection is performed by directly introducing the blue data DBU into the first line memory ML1.

Figure 14 shows the data switch DSW in Figure 1.
A specific example is shown below. Here, data switch DSW
A data switching control signal DOUT is introduced into the control circuit CL constituting the control circuit CL along with an energizing signal EN based on a command from a console panel (not shown), and the first data selection signal SD1, the second data selection signal SD2 and the selected data are first and second controlling passage;
generates logic signals SDL1 and SDL2. In addition, the black read data DMB, the red read data DMR, the output OR signal DBR of the OR gate 141 based on these data DMB and DMR, and the zero data GND equal to the ground potential are
They are introduced into contacts s, t, u, and v of changeover switches 151 and 153 included in data selection circuit DSC1 and second data selection circuit DSC2, respectively. The data DSL1 and DSL2 selected by both the changeover switches 151 and 153 are supplied to AND gates 161 and 163, respectively, and are passed through only when the logic signal SDL1 or SDL2 is at a high logic level, and the data are respectively converted to black data.
DHB or red data DHR.

Now, the designated area AER surrounded by the blue loop LP
Consider the case where only the image is recorded in normal color. The changeover switch 151 is set to contact s by the energizing signal EN.
Then, both data selection signals SD1 and SD2 are generated to respectively connect the switch 153 to the contact point t. Furthermore, by the data switching control signal DOUT, both logic signals _SDL1 and
Generate SDL2. Therefore, the edge detection information DE
Accordingly, the original image within the designated area AER is recorded line by line, and no recording is performed outside the designated area AER even if color data DMB and DMR are present.

Next, consider the case where red is also reproduced as black, regardless of whether it is inside or outside the designated area AER. First, switch 1
51 is connected to contact u, and switch 153 is connected to contact v. In other words, the black head HEB is determined by the logical sum signal DBR of both black and red data.
Perform black ink protrusion in . On the other hand, Red Head
Since zero data GND is supplied to HER, red ink is not ejected. In this state, the logical signal
By controlling the control circuit CL so that SDL1 is constantly at a high logic level, the entire document MAT is recorded in black inside and outside the specified area AER.

Further, if the logic signal SDL1 is set to a high logic level only during the detection period _TZK of both edge information DE, red and black are recorded only in the designated area AER.

By the way, such color conversion is also possible when black is recorded in red. That is,
The changeover switch 151 is connected to the contact point v to prohibit black ink from protruding from the black head HEB. Along with that,
By connecting the switch 153 to contact u, it is possible to record data in red including black data.

Furthermore, it is also possible to convert black to red and red to black in the original MAT and record them. In this case, the changeover switch 151 is set to contact t,
Switches 153 are connected to contacts s, respectively. Therefore, based on the red data DMR, the black head
HEB black ink protrusion is performed, and black data
Red ink is ejected from the red head HER based on the DMB, and recording is performed with color conversion between black and red. In addition, in this case as well, both logic signals
Depending on the logic level states of SDL1 and SDL2, control can be performed to perform color conversion recording inside and outside the specified area AER.

Furthermore, the above-mentioned color conversion can be made different inside and outside the blue loop LP. For example, the detection period T _ZK of both edges is determined by the control circuit CL.
The first logic signal SDL1 is set to a high logic level,
The second logic signal SDL2 is controlled to be at a low logic level. In addition, the changeover switch 151 is connected to contact t.
Then, each switch 153 is connected to the contact point s. Then, red data will be displayed within the specified area AER.
Black ink is ejected by the black head HEB based on the DMR, and black data is displayed outside the designated area AER.
Red ink is projected by red head HER based on DMB. Therefore, black to red conversion can be performed outside the area AER, and red to black conversion can be performed within the area AER.

Further, it is also possible to make it impossible to reproduce a certain color. For example, if the changeover switch 151 is set to contact s,
Switches 153 are connected to contacts v, respectively. Then, black recording is performed based only on the black data DMB of the read data, and the red data DMR is suddenly cut off. Note that when erasing such red color only for areas outside the designated area AER, the logic signal SDL2 is set to a high logic level only during the edge detection period T _ZK . in this case,
The switch 151 is connected to the contact s, and the switch 153 is connected to the contact t. Within the area AER,
The black data DMB causes ink to protrude from the black head HEB, and the red data DMR causes the red head to protrude.
Ink ejection of HER is performed respectively. However, since the red data DHR is prohibited outside the area AER, only the black ink protrusion of the black head HEB is performed by the black data DMB. Therefore, it is possible to perform recording with the red color erased only outside the area AER.

In addition, in the above-mentioned embodiment, the manuscript MAT
Although the printing colors are set as red and black, if the original is printed in three or more colors including other colors, all the colors are determined to be red, black, and blue in terms of hue. Therefore, if the area specified loop LP is colored blue, the original
MAT must not be a manuscript that contains a printing color that is considered blue.

Further, although edge detection is performed based on the blue data DBU, edge detection may be performed based on data of other colors to designate a region. Furthermore, the data compression and edge detection unit is not limited to just one color of blue, but can also be provided for other color data (for example, red data DRE) to perform recording processing based on multiple color data. You can also do this. For example, it is convenient for organization if the area surrounded by a blue loop is recorded in black and the area surrounded by a red loop is recorded in red. It is also possible to print the area surrounded by the red loop without printing at all, and convert the area surrounded by the red loop (for example, converting a black and white document to red) using the data switch DSW in accordance with the data switching control signal DOUT. This can also be done by controlling the However, when specifying areas in blue and red as shown above, the original
The printing color of MAT must be other than blue or red.

Furthermore, although the application example described above is an inkjet recording apparatus, the present invention is not limited to this, and the present invention can be applied to other types of recording apparatuses by replacing the inkjet heads HEB and HER with other recording elements.

As described in detail above, according to the present invention, it is possible to realize an image processing device that eliminates the conventional drawbacks.

As described above, according to the present invention, an image area defined by a specific color on a document is determined based on a specific color signal output by color-separating and reading the document image, According to this area discrimination, all the multiple color signals in the image area are converted into the desired color signals and output, so you can easily create multiple color images without the need for a complicated area specification mechanism or troublesome operations. It is possible to reproduce all images in a desired area of an arbitrary shape of a document having a color tinge in a desired color.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a recording device to which an embodiment of the image processing device according to the present invention is applied, and FIG. 2A
~E are diagrams for explaining the operation of each stage of data processing in Figure 1, Figure 3 is a block diagram specifically showing the circuit configuration in the color discrimination section, and Figures 4A~
K is a waveform diagram for explaining the operation of Fig. 3, and Fig. 5
The figure is a block diagram showing a specific example of a main scanning compressor.
6A to 6G are signal waveform diagrams of each part in FIG. 5, FIG. 7 is a block diagram showing a specific example of a sub-scanning compressor, and FIGS. 8A to 8H are signal waveform diagrams of each part in FIG. 7. , FIG. 9 is a detailed block diagram of the edge detection section, FIGS. 10A to D are explanatory diagrams of detection patterns in the edge detection section, FIG. 11 is a block diagram of the circuit section that processes the edge detection signal, and FIG. 12A -D are signal waveform diagrams for explaining the operation of FIG. 11, FIG. 13 is a flowchart for explaining the operation of FIG. 11, and FIG. 14 is a block diagram showing a specific example of the data switcher. . MAT...manuscript, SOL...light source, BS...beam splitter, PHB, PHR...photoelectric converter,
DMC...color discriminator, CDM...main scan compressor,
CDS...sub-scanning compressor, EDE...edge detector,
DEA...Area detector, DCL...Loop discriminator,
SDT...Data selector, CT1, CT2, CT3...
...Counter, SR1 to SR6...Shift register,
CL...control circuit, DSC1, DSC2...data selection circuit.

Claims (1)

[Scope of Claims] 1. A reading means for outputting a plurality of color signals by color-separating and reading a document image; and a reading means for outputting a plurality of color signals by separating and reading a document image; and a processing means for converting all the plurality of color signals in the image area into desired color signals and outputting the desired color signals according to the area discrimination by the discrimination means. An image processing device characterized by: