JPH024173B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a digital compression circuit that converts a linear code into a μ-law code or an A-law code, a constant is added to the linear code to generate an output, and this constant can be switched. The system detects the position where "1" first appears in the output and can switch the range in which this detection is performed, counts the number of bits from the upper bit to the detected position of "1" in the addition output, and calculates this value. Obtain the segment value of the μ code or A-law code by outputting the numerical value as is or inverted, and extract the signal of a predetermined number of bits following the detection position of "1" and output it inverted or as is. The step value of μ-law or A-law is obtained by

[Industrial application field]

The present invention relates to a digital compression circuit for compressing digital audio signals, and in particular to a digital compression circuit that can perform processing in a common circuit when converting a signal consisting of a linear code into a μ-law code and an A-law code. This relates to compression circuits.

In a PCM communication encoder, an audio signal consisting of a linear code is non-linearly encoded into a μ-law code or an A-law code, depending on the communication method, and the encoder encodes the audio signal consisting of a linear code into a μ-law code or an A-law code. It is necessary to create a PCM code consisting of one upper code bit, a three-bit segment value indicating the next size, and a four-bit step value indicating the lowest size. The present invention is applied to the purpose of code conversion in such cases.

[Conventional technology]

In PCM communication, in order to improve the transmission efficiency when transmitting digitized audio signals, a method of compressing the code length by performing non-linear quantization is widely used. The μ law and the A law are generally used as nonlinear encoding rules in this case.

When performing such non-linear encoding, it is necessary to perform compression conversion from a linear code to a μ-law or A-law code, or from a μ-law or A-law code to a linear code, at the transmitting and receiving ends. However, as a conversion method in this case, conventionally the most commonly used method is to use a readout memory (ROM) that stores the correspondence between the linear code and the μ-law or A-law code, and perform the conversion using a table lookup method. ing.

However, although the code conversion method using ROM has a high processing speed, there is a problem in that the ROM itself increases the circuit size. Summer.

Conventionally, digital compression circuits that convert linear codes to μ-law codes or A-law codes through logical operation processing have been used to convert linear codes to μ-law codes, linear codes to A-law codes, etc.
Methods that each perform a single conversion process are already known.

[Problem that the invention seeks to solve]

However, no digital compression circuit has been known that can commonly process the conversion from linear code to μ-law code and A-law code.

The present invention aims to solve the problems of the prior art, and by providing three types of switching circuits, the conversion from linear code to μ-law code and A-law code can be performed in a common circuit. It is an object of the present invention to provide a digital compression circuit that can be processed as described above.

[Means for solving problems]

FIG. 4 illustrates an algorithm for compressing a linear code into a μ-law code, and FIG. 5 illustrates an algorithm for compressing a linear code into an A-law code. In Figures 4 and 5, the case where the step value is 0 is taken as a linear segment boundary value,
It is displayed in binary. Also, in Fig. 4, A is a segment value, B is a linear segment boundary value,
C is a constant for the segment boundary value & H21 (displayed in hexadecimal)
In FIG. 5, A is a segment value and B is a linear segment boundary value. However, the boundary value + &H21 value in Figure 4C and the linear segment boundary value in Figure 5B are all set to the constant value "1 1111 0000 0000" if "1" is set at the 14th bit or higher. Therefore, in each figure, the 14th bit and above are all displayed as "0".

As is clear from these two figures, in the case of μ law, S at the value of boundary value + & H21 (Figure 4 C)
As shown in Figure 4, the segment value (Fig. 4A) can be uniquely determined depending on which bit from the MSB is set to "1", and in this case the step value is determined by that "1". It is sufficient to invert the value of the lower bit.

In addition, in the case of the A-law, in the boundary value displayed without adding a constant (Figure 5B), the unique The segment value (FIG. 5A) can be determined, and the step value can take the value of the 4 bits lower than "1". However, the only exception is when the segment value is "000", and the step value is obtained from the position shown in FIG. 5B.

FIG. 1 shows the basic configuration of the present invention.

Reference numeral 101 denotes an adding means which adds a constant to an input signal consisting of a linear code to generate an output.

102 is a first switching means that switches the constant value to be added to the linear code according to the μ law or the A law.

Reference numeral 103 is a position detection means, and addition means 10
The position where "1" first appears in the output of "1" is detected.

Reference numeral 104 is a second switching means that switches the range in which "1" should be detected.

105 is a counting means that counts the number of bits in the output of the adding means 101 from the upper bit to the first "1" detection position.

Reference numeral 106 denotes a predetermined bit extracting means, which extracts a signal of a predetermined number of bits following the detection position of "1" in the output of the adding means 101.

107 is the third switching means, and the counting means 1
05 is output as is or inverted.

108 is a fourth switching means, which inverts or outputs the extracted signal of the predetermined bit extracting means 106 as is.

[Effect]

As shown in Figures 4 and 5, the number of bits from the upper bit to the first appearance of "1" in the result of adding a constant (&H21 in the case of μ law, 0 in the case of A law) to the linear code. Since corresponds to the segment value, this number of bits is counted. Also, since the signal of a predetermined number of bits following this "1" detection position corresponds to the step value, this is extracted. Then, by outputting the counted value as it is as a segment value and inverting the extracted value and outputting it as a step value, a μ-law coded output can be obtained. Further, by inverting the count value and outputting it as a segment value, and outputting the extracted value as it is as a step value, an output coded in A-law can be obtained.

〔Example〕

FIG. 2 shows an embodiment of the present invention. In the same figure, 11 is a latch circuit (LT), 12
is a two's complement circuit (COM), 13 is an adder (ADD), 14 is a selector (SEL), 15 is a limit circuit (LIM), 16 is a shift register (P/S),
17 is a selector (SEL), 18 and 19 are OR circuits,
20 is a counter, 21 and 22 are inversion circuits, 23 is a selector (SEL), and 24 is an inversion circuit.

In FIG. 2, selector 14, selector 1
7. The selector 23 is switched to side (1) when converting to μ-law code, and to side (2) when converting to A-law code.

The input signal SL, which is a 16-bit linear code expressed in two's complement, is temporarily stored in the latch circuit 11, and added to the two's complement circuit 12 to obtain 15
Produces an absolute value signal consisting of bits. Adder 1
3 adds a constant value &H21 (in hexadecimal notation) to this absolute value signal in the case of the μ law, and adds 0 in the case of the A law to produce a 16-bit output. The control circuit 15 outputs the 13-bit signal as is when the 14th bit or higher is not set to "1", and if the 14th bit or higher is set to "1", it outputs a constant value &
Limits to H1F00 (hexadecimal representation) to produce 13-bit output. The output of the control circuit 15 is the shift register 1
6 is loaded.

The shift register 16 is supplied with clock CK1 in the case of μ law, and clock CK2 in the case of A law.
is supplied. Clock CK1 has been eight clocks since the signal was loaded into shift register 16, and clock CK2 has also been seven clocks.
The counter 20 is reset at the same time as the signal is input to the shift register 16, and is supplied with the clock CK1. shift register 1
6 outputs the signal from the MSB first, and when "1" is output, the clock supply to the shift register 16 and counter 20 is stopped, and the current state is held.

In this state, when the μ law is applied, the 3-bit output of the counter 20 is used as the segment value, the inverted signal of the parallel 4-bit output of the shift register 16 is used as the step value, and the sign bit of the linear code SL in the latch circuit 11 is added to it. By adding the inverted signal as a sign bit, an 8-bit output signal SP converted to a μ-law code is obtained.

In addition, when using Law A, the 3-bit output of the counter 20 is inverted and used as a segment value, the parallel 4-bit output of the shift register 16 is used as a step value, and the inverted signal of the sign bit of the linear code is added as a sign bit. As a result, an 8-bit output signal SP converted to an A-law code is obtained.

〔Effect of the invention〕

As explained above, according to the digital compression circuit of the present invention, when compressing a linear code into a μ-law code or an A-law code through logical operation processing, processing can be performed using a common circuit. This simplifies the circuit configuration.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing the configuration of an embodiment of the present invention, and Fig. 3 is a diagram showing the configuration of an embodiment of the present invention.
FIG. 4 is a diagram illustrating the configuration of a PCM code, FIG. 4 is a diagram illustrating a conversion algorithm from a linear code to a μ-law code, and FIG. 5 is a diagram illustrating a conversion algorithm from a linear code to an A-law code. 11... Latch circuit (LT), 12... Two's complement circuit (COM), 13... Adder (ADD), 14...
...Selector (SEL), 15...Limiting circuit (LIM),
16...Shift register (P/S), 17...Selector (SEL), 18, 19...OR circuit, 20
...Counter, 21, 22...Inversion circuit, 23...
...Selector (SEL), 24...Inversion circuit.

Claims (1)

[Claims] 1. Adding means 101 that adds a constant to a linear code to generate an output, and first switching means 102 that switches the constant value.
, a position detecting means 103 for detecting the position where "1" first appears in the addition output; a second switching means 104 for switching the range in which the detection should be performed; Counting means 105 for counting the number of bits of
a predetermined bit extracting means 106 for extracting a predetermined number of bits of a signal following the detection position; a third switching means 107 for outputting the counted value as is or inverted; and a third switching means 107 for inverting or outputting the extracted signal as is. and a fourth switching means 108 for switching the respective switching means, the output of the third switching means is provided with a μ-law code or an A
obtain the segment value of the law code, and input the μ law code or A to the output of the fourth switching means.
A digital compression circuit characterized by obtaining a step value of a regular code.