JPH0241674Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a circuit for mixing an RGB input signal and an RGB sign signal in a color television having an RGB input terminal.

(Prior technology) Modern color televisions are connected directly to external devices such as personal computers, and in order to display high-density characters and graphics, RGB signals (red, green, and blue synchronization signals) are input from the outside. Input the primary color signal (not including the primary color signal)
Some have RGB input terminals.

Each RGB data signal input from the RGB input terminal is processed by a signal processing circuit.
Mixed with the sine signal.

FIG. 4 shows an example of this type of signal processing circuit 30, and FIG. 5 shows a timing chart of the signal processing circuit 30. Note that FIG. 4 illustrates only the circuit configuration for mixing the R data signal and the R sine signal.

The signal processing circuit 30 receives an R data signal S10 from a terminal 31 and an R sign signal S11 from a terminal 32.
is a circuit in which the RGB sign blanking signal S12 is inputted from the terminal 33, and the mixed signal S13 is outputted from the terminal 34.

The R data signal S10 [FIG. 5C] is connected to the resistor R1.
3, through a differentiating circuit 35 consisting of C13, a resistor R
14, and a first bias value (V ₁ ) determined by R15. On the other hand, RGB
When the sign blanking signal S12 (FIG. 5B) is input to the terminal 33 and the transistor _Q13 becomes conductive, the R data signal S10 is transferred to the transistor _Q14.
is biased by a second bias value (V ₂ ) determined by resistors R14, R15, and R16 and is input to the base side of the transistor _Q14 (see FIG. 5D).

On the other hand, the R sign signal S11 (FIG. 5A) is input to the base side of the transistor _Q15 , which shares the collector and emitter terminals of the transistor _Q14 . In addition, a resistor R17 is connected to the common emitter terminal of these transistors Q ₁₄ and Q ₁₅ .
The mixed signal S13 (FIG. 5E) is outputted via the resistor R17.

(Problems to be Solved by the Invention) In the conventional processing circuit, the data signal is simply biased at the first bias value (V ₁ ). The sine level (V ₃ ) indicates the difference level between the highest level value in the signal S13 after mixing and the lowest level value of the R data signal. Therefore, in conventional circuits, when the amplitude level of the data signal changes, the sine level (V 3 ) V ₃ ) will fluctuate.

Furthermore, since the collector potential of the transistor _Q13 is affected by the charging and discharging of the capacitor C13 in the differentiating circuit 35, the first bias value ( _V1 ) and the second bias value ( V ₂ ) will fluctuate, and as a result, the sine level (V ₃ ) after mixing will also fluctuate.

(Means for solving the problem) The RGB input terminal is connected to the drain side of the N-channel FET via a capacitor, and the
The FET is activated by the first voltage applied to the gate.
The present invention relates to an RGB signal processing circuit in which an RGB input signal is clamped to a predetermined voltage and output to the source side, and is cut off by a second voltage applied to the gate by an RGB sign blanking signal.

(Function) When the RGB sign blanking signal is at the "L" level, each RGB data signal is clamped to a predetermined voltage by the first voltage applied to the gate of the N-channel FET via the capacitor, and the mixing circuit This becomes the output. On the other hand, when the RGB sign blanking signal goes to the "H" level, the voltage applied to the gate is lowered to the second voltage, and the discharge of the capacitor reverse biases the gate and source, cutting off the drain and source. The data signal is blanked only during the input period of the sign blanking signal.

(Example) Hereinafter, the configuration of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit configuration of an R data signal processing section 1 in an RGB signal processing circuit according to the present invention, and FIG. 2 shows a timing chart of the processing section 1.

The terminal 2 constitutes one of the RGB input terminals (not shown), and is a terminal to which the R data signal S1 is input.

The R data signal S1 input to the terminal 2 is input to the drain (D) side of the N-channel FETQ ₁ via a differentiating circuit 3 consisting of a resistor R1 and a capacitor C1. As this N-channel FETQ ₁ , for example, a depletion type J-FET is used.

A clamping means 4 is connected to the gate (G) side of the N-channel FETQ ₁ for clamping the R data signal S1 and outputting it to the source (S) side.

The clamping means 4 consists of an NPN transistor _Q2 , a diode D1, and resistors _R2 and R3, and the collector side of the NPN transistor _Q2 and the cathode side of the diode D1 are connected to the gate (G) side of the N-channel FETQ1. , a voltage _V5 obtained by dividing the power supply voltage (Vcc) by resistors R2 and R3 is applied to the anode side of the diode D1.

The NPN transistor _Q2 is controlled to open and close by the RGB sign blanking signal S2 input from the terminal 5, and when the signal S2 is at the "H" level, the gate of the N-channel FET _Q1 is lowered to the ground potential.

A mixing circuit 6 is connected to the source (S) side of the N-channel FETQ ₁ .

The mixing circuit 6 has mutual emitter terminals,
A pair of NPNs whose collector terminals are commonly connected
It is composed of transistors Q ₃ and Q ₄ and a resistor R4, and the R data signal S1 outputted via the clamping means 4 is input to the base side of one NPN transistor Q ₃ , and the other NPN transistor Q ₄
An R-sine signal S3 is input from the terminal 7 to the base side of the circuit. And those signals S1 and S3
is the mixing signal S from resistor R4 after mixing.
4 is output to terminal 8.

Processing unit 1 for R data signal S1 having the above configuration
, when the RGB sign blanking signal S2 is at "L" level, the R data signal S1
is the diode D1 and the N-channel to the voltage _V5 .
Forward voltage between gate and source of FETQ ₁ (V _F )
It is clamped at a constant voltage value V ₄ (see FIG. 2D) and applied to the NPN transistor Q ₃ .
At this time, the capacitor C1 is charged with the polarity shown in the figure.

On the other hand, when the RGB sign blanking signal S2 is at the "H" level, the NPN transistor _Q2 becomes conductive, and the gate potential of the N-channel _FETQ1 becomes the ground potential. Channel FETQ ₁ is blocked.
When the N-channel FETQ ₁ is cut off, the R data signal S1 is blanked during the cut-off period, that is, the period during which the RGB sign blanking signal S3 is inputted [FIG. 2D]. As a result, the mixing signal S4 output from the resistor R4
becomes a mixing waveform having a constant amplitude obtained by adding the amplitude of the R sine input signal S2 [sine level V ₆ ] to the lowest level of the R data signal S1 after mixing (FIG. 2E).

In addition, in the above circuit configuration, if the blanking period is long, the charge of capacitor C1 becomes
FETQ ₁ ~ NPN transistor Q ₃ ~ Resistor R4 ~ The reverse voltage between N-channel FETQ ₁ - gate (G) and source (S) decreases as it is discharged through the discharge path from resistor _R4 to ground. conducts, so
The time constant of the discharge path is set to be sufficiently larger than the "H" level period of the RGB sign blanking signal S2.

FIG. 3 shows a specific circuit configuration of the RGB signal processing circuit 9, which includes processing sections for G data signals and B data signals in addition to the processing section 1 for the R data signal S1 shown in FIG.

In this figure, circuit elements having the same functions as those in FIG.
indicates the terminals of the IC, terminal 23 is the input terminal for the G data signal, and terminal 24 is the input terminal for the B data signal.

Terminals 10, 11, and 12 are terminals to which the R data signal, G data signal, and B data signal after passing through the differentiating circuit 3 are input.

Terminal 13 is a terminal for power supply voltage (Vcc), terminal 21
is the ground terminal.

Terminals 14, 17, and 19 are terminals to which an R sine signal, a G sine signal, and a B sine signal are respectively input.

Terminals 15, 18, 20 are R mixing signals, G
These are output terminals for each of the mixing signal and the B mixing signal.

Terminal 16 receives R sign signal, G sign signal, B
Reference voltage setting terminal for limiting the amplitude of the sine signal,
The terminal 22 is an output terminal for an RGB sign blanking signal.

The RGB signal processing circuit 9 includes the above-mentioned R data signal, G data signal, and B data signal processing units, as well as
It includes an RGB sign blanking signal generation circuit 25, an amplitude limiting circuit 26 for each sign signal level, and a speed up circuit 27.

The RGB sign blanking signal generation circuit 25 includes four NPN transistors _Q5 to _Q8 , base current limiting resistors R7 and R8 of the transistors, and RGB
Consisting of a blanking signal output resistor R9, each of the sign signal lines 28 to 30 corresponds to the blanking signal output resistor R9.
Connected to the base side of NPN transistors _Q5 to _Q7 . Then, when each sign signal becomes "H" level, the corresponding NPN transistor becomes conductive.
The RGB blanking signal S2 is outputted via the output resistor R9. Also, when the RGB blanking signal S2 is output from the resistor R9,
The NPN transistor _Q8 also outputs an "H" level signal to the conductive terminal 22 at the same time.

The amplitude limiting circuit 26 includes a PNP transistor Q ₉ ,
Three diodes D2-D4 and resistors R10, R
11, connected from each sign signal line 28 to 30 to the emitter side of the PNP transistor Q9 via the corresponding diode D2 to D4, and connected to the emitter side of the PNP transistor _Q9 .
0, voltage value divided by R11 and terminal 1
Reference voltage (V ₇ ) determined by the voltage value input to 6
The amplitude of each sine signal exceeding .

The speed up circuit 27 consists of a resistor R12, a capacitor C2, and a diode D5.
The rise and fall times of the RGB sign blanking signal S2 to the NPN transistor _Q2 are accelerated.
The values of resistor R12, capacitor C2, and diode D5 are set to values compatible with NPN transistor _Q3 .

In addition, the resistor R13 in the figure is an N-channel FETQ ₁
The resistors R14 and R15, which adjust the gate potential at the time of cut-off, are current-limiting resistors, respectively.

(Effects of the invention) As described above, the invention clamps the RGB input signal to a constant level when the RGB sign blanking signal is at the "L" level, so the influence of the data signal level and the frequency of the sign blanking signal The sign level after mixing does not change due to

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the configuration of the R data signal processing section in the RGB signal processing circuit of the present invention, Fig. 2 is a timing chart showing the operation of the processing section, and Fig. 3 is a specific example of the RGB signal processing circuit. FIG. 4 is a circuit diagram showing the configuration of a conventional R data signal processing section, and FIG. 5 is a timing chart showing the operation of the processing section. Q ₁ ...N channel FET, C1...Capacitor,
4... Clamp means, 6... Mixing circuit.

Claims (1)

[Scope of utility model registration request] The RGB input signal input from the RGB input terminal
The RGB signal processing circuit is equipped with a circuit for mixing RGB sign signals, and the RGB input terminal is connected to the drain side of an N-channel FET via a capacitor. An RGB signal processing circuit characterized in that an RGB input signal is clamped to a predetermined voltage by a voltage and outputted to the source side, and is cut off by a second voltage applied to the gate by an RGB sign blanking signal. .