JPH0241525A - Address allocation processing system in translation processor - Google Patents

Abstract

PURPOSE:To constitute the title system so that a constant value of an address at the time of using an array is contained appropriately in a range of a displacement fixing part by generating a hardware instruction by allocating an intermediate code of a fixed value derived by a displacement updating means to the displacement fixing part and allocating an intermediate code of a variable value to a displacement variable part. CONSTITUTION:A base address allocating means 23 executes a determination so that a value of a displacement 'D0' extending from a base address to a head element satisfies a prescribed inequality, and a displacement updating means 24 processes an intermediate code of a constant value which has been generated by a displacement generating means 21, so as to shift it by a value portion of this 'D0'. By this processing, a constant value of each array goes into a range which a displacement fixing part has. On the other hand, when the value of 'D0' does not satisfy this inequality, the displacement updating means 24 generates an intermediate code in a form for absorbing the intermediate code of the constant value which does not go into the range which the displacement fixing part has, into a displacement variable part. In such a way, the constant value of the array comes to be contained appropriately and automatically in the range of the displacement fixing part.

Description

[Detailed Description of the Invention] [Summary] For array elements in a source program written according to variable values and constant values, an array element on the main memory represented by a base address, a variable displacement part, and a fixed displacement part is Regarding the address allocation processing method in the translation processing device for allocating addresses, the purpose is to ensure that the constant value of the address when using an array is appropriately included in the value range of the displacement fixed part, and the base address of the array is As assigned to the first element, there is a displacement generation means that generates intermediate codes of variable values and constant values, and according to the generation results of this displacement generation means, the maximum and minimum values of the intermediate codes of constant values are generated for each array. Maximum/minimum detection means for detecting values; base address allocation means for allocating a displacement relationship between the base address and the first element of the array according to the detection results of the maximum/minimum detection means; , displacement updating means for updating the intermediate code of the variable value and constant value generated by the displacement generating means so that the intermediate code of the constant value of each array falls within the value range of the displacement fixing section; The intermediate code of the determined constant value is assigned to the fixed displacement section, and the intermediate code of the variable value is assigned to the variable displacement section, thereby generating a hardware instruction.

[Industrial application field]

The present invention relates to an address allocation processing method in a translation processing device for allocating addresses in main memory to array elements described in a source program.

The translation processing device that executes the compilation process performs a process of allocating addresses in main memory to array elements described in the source program. This allocation process needs to be configured in a manner that improves program execution performance while taking into account the limitations imposed by the structure of the instruction format.

[Conventional technology]

In commonly used general-purpose computers, addresses in main memory are expressed in the format (base address + variable displacement part, fixed displacement part). FIG. 11 shows an example of an instruction format for a general-purpose computer.

As shown in ``Main memory operand'' in this figure, the base address in main memory and the variable displacement part are represented by the contents of the register specified as the register operand in the hardware instruction, and the fixed displacement part is , the value will be embedded directly into the instruction.

Generally, when accessing array elements that appear in a source program, an address unique to each array is used as the base address, and array subscripts are expressed using a variable displacement part and a fixed displacement part. become. The array index expression in the source program is expressed in the format (variable value + constant value), so in order to reduce the number of addition instructions by one and speed up address calculation, the variable value is specified by the register of the variable displacement part. A configuration is adopted in which the constant value is stored in an area and directly embedded in the instruction as a displacement fixing part. However, the values that can be set in the displacement fixing section are subject to certain restrictions from a hardware perspective. For example, if we look at the command format shown in Figure 11, the range of values that the displacement fixing section can take is from 0°'' to "4095'".From now on, the constant value set for the displacement fixing section is below the lower limit (in this case Then, in order to avoid becoming "0"), the base address is set even from the first element of the array, and the base address is set to point to an array element that does not exist.

In the prior art, the base address is always set at a constant value starting from the first element of the array.

That is, in the prior art, the displacement relationship between the base address and the first element of the array is realized in accordance with a predetermined value for the same vehicle.

[Problem to be solved by the invention]

However, as in the prior art, the setting of the base address is
If you configure the array so that it is always set according to a constant value from the first element, if this constant value is small and the constant value of the array fluctuates greatly, the constant value of all array elements will be set equal to or higher than the lower limit value of the fixed displacement section. There was a problem that it could not be set to . In order to avoid this problem, if this constant value is set to a large value with a margin, then there is a problem that the number of objects that cannot go below the upper limit of the displacement fixed part increases. . In this way, values that do not fall within the range of the fixed displacement part must be expressed by adding them to the variable displacement part or the register indicating the base address, which has the disadvantage of slowing down the execution time by the addition instruction. It was.

The present invention has been made in view of such circumstances, and provides an address allocation processing method in a translation processing device in which constant values of an array are appropriately included in the value range of a fixed displacement part. The purpose is to solve such problems.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic configuration of the present invention.

In the figure, 10 is a source program that has an array described according to variable values and constant values, and 20 is a source program that has an array element described in accordance with variable values and constant values. A translation processing device for allocating addresses on a storage device; 30 is this translation processing device 2;
0, which is an object program translated by 0
The translation processing device 20 of the present invention includes a displacement generation means 21, a maximum/minimum detection means 22, a base address allocation means 23, a displacement update means 24, and a hardware instruction generation means 25. Which displacement generating means 21 generates intermediate codes of variable values and constant values of each array element, assuming that the base address is assigned to the first element of the array, and the maximum/minimum detecting means 22 generates a displacement. According to the generation result of the means 21, the maximum value and minimum value of the intermediate code of the constant value are detected for each array, and the base address allocation means 23 allocates the base address and the array according to the detection result of the maximum/minimum detection means 22. The displacement update means 24 allocates the displacement relationship with the leading element, and according to the allocation result of the base address allocation means 23, the intermediate code of the constant value of each array falls within the value range of the displacement fixing part.
The hardware instruction generating means 25 updates the intermediate code of the variable value and the constant value generated by the displacement generating means 21, and assigns the intermediate code of the constant value determined by the displacement updating means 24 to the displacement fixing section, and also updates the intermediate code of the variable value and the constant value. Processing is performed to generate hardware instructions by assigning the intermediate code to the variable displacement section.

[Effect]

In the present invention, the base address allocation means 23 determines that the value of the displacement "Do" from the base address to the leading element is D, 1 . fi≦Do
+D+≦DI+Dt≦D It is determined to satisfy the inequality IIMX. Here, DI: Minimum value of intermediate code of constant value of each array D2: Maximum value of intermediate code of constant value of each array Dllifi' Minimum value of value range of displacement fixed part DIII
IX: Maximum value of the value range of the displacement fixed part. Then, the displacement updating means 24 processes the intermediate code of the constant value generated by the displacement generating means 21 so as to shift it by the value of "D". This process allows the constant values of each array to fall appropriately within the range of the displacement fixing section.

On the other hand, 110. ” does not satisfy this inequality, the displacement updating means 24 generates an intermediate code in a format in which the intermediate code with a constant value that does not fall within the range of the fixed displacement section is absorbed into the variable displacement section. Process as follows.

In this way, according to the present invention, the constant value of the array is automatically and appropriately included in the value range of the displacement fixing part.

〔Example] Hereinafter, the present invention will be explained in detail according to examples.

FIG. 2 shows a system configuration diagram of the present invention. As shown in this figure, a compiler 20a that implements the address allocation processing method of the present invention uses a main memory unit represented by a base address, a variable displacement part, and a fixed displacement part for array elements of a source program analysis part. The above address is assigned and the object program 30 is generated. In order to realize this process, the compiler 20a of the present invention has, as shown in the figure, a source program analysis section 1, a first optimization section 2, an area v1 attaching section 3, Second
The optimization section 4 includes an optimization section 4 and a code generation section 5.

The processing content executed by the source program analysis unit 1 is
As shown in Figure (A), it consists of a source program reading process and an intermediate code creation process for array use, and the processing content executed by the area allocation unit 3 is as shown in Figure 3 (B).
As shown in FIG. 2, the processing consists of base address determination processing and constant value updating processing, and the processing content of the code generation unit 5 consists of hardware instruction generation processing. And the first
The optimization unit 2 optimizes the processing result of the source program analysis unit 1 and passes it to the area allocation unit 3, and the second optimization unit 4 optimizes the processing result of the area allocation unit 3 and passes it to the code generation unit 5.
Process it so that it is passed to.

Next, details of the processing contents of the source program analysis section 1 and the HMi allJ attachment section 3 will be explained according to the flowchart shown in FIG.

In order to better understand the processing contents of the flowchart in FIG. 4, let us assume that the source program 10 shown in FIG. 5 is the source program 10 to be compiled. This source program 10 is a program example of real number type arrays "A" and "B" consisting of 2048 array elements, and "rA(1)=..." is indicated by the variable value ■ of the A array. "...=A (1+1022)J" means a program step that sets a value to an element that is
This means a program step that refers to the element indicated by the variable value I and the constant value 1022 in the A array.

When there is a request for compilation processing, the compiler 20a
First, as shown in step 1, source program 1
Process to read 0. Through this process, the source program shown in FIG. 5 is read. In step 2, an intermediate code is created assuming that the base address is assigned to the first element of the array. Specifically, the generation of the intermediate code in step 2 is as follows: variable value = (source variable value) X (region length of l element) constant value - (source constant value - lower limit value of subscript) (area length). Assuming that the area length of one element in both array A and array B is 4 bytes, and it starts from "1", the intermediate code shown in Figure 6 is generated from the source program in Figure 5 through the processing in step 2. That will happen.

Subsequently, in step 3, the generated intermediate code of the constant value is searched to detect the minimum value D2 and the maximum value D2 of the intermediate code of the constant value for each array. Looking at the intermediate code example in Figure 6, for the A array, there is -4,4084,36'' as the intermediate code for the constant value, so D, =
-4,Dg=4084,For the B array, there is -24,-4'' as the intermediate code of the constant value, so D,=
-24, D, = -4 is detected 0 or more The processing of steps 1 to 3 described above will be repeated until it is confirmed in step 4 that the source program 10 has ended.

In this way, after generating the intermediate code and finding the maximum and minimum values of the intermediate code of constant values, in the next step 5, one array is extracted, and in the following step 6, DI-D-! -DI The value of the displacement D0 from the base address to the first element is calculated for the extracted array. Here, Dl,1 is the minimum value of the range of the displacement fixing section that specifies an address on the main memory, and as described above, is "O" in the instruction format shown in FIG. 11.

What this formula means is that if the maximum value of the value range of the displacement fixed part is expressed as D□8, then the value of D is DmrnS DO
+ D +≦Do+Dt≦D ++i 11 If the inequality of M is satisfied, the constant value can fall within the range of the displacement fixed part, so one Do that satisfies this condition was selected. In the process of step 6, D□7 becomes “0”.
If ゛゛, then D,=4 for the A array and D for the B array.

-24 will be calculated. The processing in steps 5 and 6 is repeated until it is confirmed in step 7 that all arrays have been extracted. When the process of step 7 is completed, the values of Do, Dl, and D2 are determined for each array, and an array management table as shown in FIG. 7 is created.

Next, in step 8, the intermediate code generated in step 2 is extracted, and in the next step 9, Do obtained in step 6 is added to the intermediate code of the extracted constant value to create a new intermediate code of the constant value. Executes arithmetic processing as code. At this time, Do uses the array to which it belongs. Then, in the following step 10, it is determined whether the intermediate code of this new constant value is smaller than the maximum value of the value range of the displacement fixing section specifying the address on the main memory, which is 1. Based on the judgment in step 10, D, 1. When it is determined that the new constant value is smaller, the intermediate code of the new constant value falls within the value range of the displacement fixed part, so the process proceeds to step 14, where it is determined whether all intermediate codes have been extracted, and all intermediate codes are extracted. If there is, terminate the process. If all intermediate codes have not been extracted, the process returns to step 8 and the process is repeated until all intermediate codes are extracted.

On the other hand, when it is determined in step 10 that D is greater than 111111, the process proceeds to step 11, where the constant value ΔD, where ΔD=D, . +Date+1, and find the integer value "t" of the integer part of this calculated value. Then, in the following step 12, use this found integer value "L" to find the variable value of Ix=txΔD. Then, in the next step 13, (tXΔD) is subtracted from the intermediate code of the constant value generated in step 9, and arithmetic processing is performed to obtain the intermediate code of the new constant value.Furthermore, in this step E3, , the intermediate code of the variable value corresponding to the intermediate code of the constant value retrieved in step 8, this! This step 11 performs arithmetic processing to replace X with an intermediate code of a new variable value.
In step 13, the intermediate code of the constant value generated in step 9 was found not to fall within the range of the displacement fixed part, as determined in step 10. In order to keep it within the value range, processing is carried out so that the excess amount (tXΔD) is borne by the intermediate code of the variable value. In this way, when the intermediate code of the constant value is processed so that it falls within the value range of the displacement fixing part, the process proceeds to step 14, and in the same way as the processing from step 10, it is determined whether all the intermediate codes have been extracted. , if all the intermediate codes have been extracted, the process ends; if not all the intermediate codes have been extracted, the process returns to step 8 and the process is repeated until all the intermediate codes are extracted.

The sixth value determined by the processing of steps 8 to 14
An example of conversion of the intermediate code in the figure is shown in FIG. 8. The intermediate code in FIG.
All the intermediate code values of the constant values are □ (here, “
4095"), so the processing of steps 11 to 13 will not be executed, and therefore,
As shown in Figure 8, the variable value does not change and the constant value increases.

It just gets bigger. In addition, in the flowchart shown in FIG. 4, D@=Da! +%-D.

Do was selected according to the formula, but the selection formula for D is
Since it is sufficient to satisfy the following inequalities: * r *≦Do+D, ≦o, +1), ≦D, □, the selection may be made according to, for example, Do−D−−X Dt.

The finally generated intermediate code is finally converted into a hardware instruction by the code generation unit 5.

In this way, in the present invention, instead of setting the base address with a constant value starting from the first element of the array,
Since the value range of the displacement fixing part is determined each time, the constant value will fall within the value range of the displacement fixing part appropriately.For example, the constant value of the source program shown in Figure 9(A) is In order to enter the value range of the fixed part, D a i * S D e + D +≦D, +D,
As can be seen by solving the inequality ≦D, □, the base address needs to be set upward from the first element of the array by 4 to 11 bytes. This positional relationship is shown in Figure 9 (C).
Here, the conditions such as the value range of the displacement fixing part are the same as in the previous explanation. Further, FIG. 9(B) shows the intermediate code obtained in step 2. As is clear from FIG. 9(C), with the conventional technique of uniformly setting the base address and shifting it by, for example, 16 bytes from the first element of the array, some values do not fall within the value range of the fixed displacement part. It is.

In addition, in order for the constant value of the source program shown in Figure 10(A) to fall within the value range of the fixed displacement part, the base address must be 1 byte to 4092 bytes long in the array as shown in Figure 10(C). must be set from the first element down.

Here, FIG. 10(B) shows the intermediate code obtained in step 2. As is clear from FIG. 10(C), the present invention employs a method of shifting the base address below the first element of the array, which was not adopted in the prior art. This allows the constant value to fall appropriately within the range of the displacement fixing section.

Although the illustrated embodiments have been described above, the present invention is not limited thereto. For example, although the value range of the displacement fixing portion has been described as 0° to 4095°, such numerical values are merely examples for convenience of explanation.

〔Effect of the invention〕

As described above, according to the present invention, the constant value of the array is automatically and appropriately included in the value range of the displacement fixed part.

From now on, even if there is a large variation in the constant value, it will be absorbed by the base address, so the number of instructions in the subscript calculation part can be reduced and the execution performance of the program can be improved.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle configuration of the present invention, Fig. 2 is a system configuration diagram of the present invention, Fig. 3 is an explanatory diagram of the processing contents of the source program analysis section and area allocation section, and Fig. 4 is a diagram of the execution of the present invention. Flowchart, Figure 5 is an example of the source program, Figure 6 is an example of the intermediate code determined by the process in step 2, Figure 7 is an example of the array management table determined by the process in step 6, and Figure 8 is the process in step 14. 9 and 10 are detailed explanatory diagrams of the present invention, and FIG. 11 is an explanatory diagram of the instruction format. In the figure, 10 is a source program, 20 is a translation processing device,
21 is a displacement generating means, 22 is a maximum/minimum detecting means, 23 is a base address υ1 attaching means, 24 is a displacement updating means, and 25 is a hardware instruction generating means.

Claims (1)

[Claims] For array elements in a source program (10) written according to variable values and constant values, an address on the main memory device represented by a base address, a variable displacement part, and a fixed displacement part. In an address allocation processing method in a translation processing device for allocating an array, displacement generating means generates intermediate codes of variable values and constant values of each array element, assuming that the base address is allocated to the first element of the array. (21), and maximum/minimum detection means (22) for detecting the maximum and minimum values of the intermediate code of constant values for each array according to the generation result of the displacement generation means (21); A base address allocation means (23) that allocates the displacement relationship between the base address and the first element of the array according to the detection result of (22); and a constant value of each array according to the allocation result of this base address allocation means (23). displacement updating means (24) for updating the intermediate codes of the variable values and constant values generated by the displacement generating means (21) so that the intermediate codes of the displacement fixing section fall within the value range of the displacement fixing section; A translation process characterized in that a hardware instruction is generated by assigning an intermediate code of a constant value determined by (24) to a fixed displacement part, and assigning an intermediate code of a variable value to a variable displacement part. Address allocation processing method in the device.