JPH0241476U - - Google Patents
Info
- Publication number
- JPH0241476U JPH0241476U JP1988120757U JP12075788U JPH0241476U JP H0241476 U JPH0241476 U JP H0241476U JP 1988120757 U JP1988120757 U JP 1988120757U JP 12075788 U JP12075788 U JP 12075788U JP H0241476 U JPH0241476 U JP H0241476U
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- recess
- electronic component
- bump portion
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988120757U JPH0241476U (US06633600-20031014-M00021.png) | 1988-09-14 | 1988-09-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988120757U JPH0241476U (US06633600-20031014-M00021.png) | 1988-09-14 | 1988-09-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0241476U true JPH0241476U (US06633600-20031014-M00021.png) | 1990-03-22 |
Family
ID=31367151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988120757U Pending JPH0241476U (US06633600-20031014-M00021.png) | 1988-09-14 | 1988-09-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0241476U (US06633600-20031014-M00021.png) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275841A (ja) * | 1992-03-30 | 1993-10-22 | Nec Corp | 多層印刷配線板 |
| WO2018042846A1 (ja) * | 2016-08-30 | 2018-03-08 | 株式会社村田製作所 | 電子デバイス及び多層セラミック基板 |
-
1988
- 1988-09-14 JP JP1988120757U patent/JPH0241476U/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275841A (ja) * | 1992-03-30 | 1993-10-22 | Nec Corp | 多層印刷配線板 |
| WO2018042846A1 (ja) * | 2016-08-30 | 2018-03-08 | 株式会社村田製作所 | 電子デバイス及び多層セラミック基板 |
| CN109644559A (zh) * | 2016-08-30 | 2019-04-16 | 株式会社村田制作所 | 电子器件以及多层陶瓷基板 |
| JPWO2018042846A1 (ja) * | 2016-08-30 | 2019-06-24 | 株式会社村田製作所 | 電子デバイス及び多層セラミック基板 |
