JPH0241046A - Transmission system for decoding key - Google Patents

Abstract

PURPOSE:To attain release of scrambling even if C/N(carrier/nose) is deteriorated by sending a decoding key at a comparatively short time interval and sending plural release keys each intermittently or continuously in relation with time information. CONSTITUTION:When the C/N reaches a certain value or below, an output of a C/N discrimination circuit 32 goes to a high level. Then an output of an OR gate 24 goes to a low level, an AND gate 27 is cut off and an output of an inverter 25 goes to a high level and an AND gate 26 is conductive. A time code collation circuit 22 starts the collation after an output of the inverter 25 goes to a high level. Then a data Ks20 of a Ks memory A 20 is read and given to a random number generating circuit 29 via the AND gate 26 an OR gate 28 and a conversion circuit 30 converts a generated random number into a line number. Thus, while the decoding key Ks is being switched continuously, descrambling is continued.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for transmitting a decoding key for descrambling a broadcast system.

[Prior Art] In a pay broadcasting system such as W1-ri Broadcasting, a broadcasting station scrambles a program signal and transmits it in a format so that the program is provided only to subscribers who have a viewing contract. On the other hand, on the subscriber's side, the scrambling key is used to descramble and extract the program signal. This allows only subscribers to view programs on an i'iT basis, thereby preventing unauthorized viewing. A scramble key for descrambling a scrambled program signal is generally transmitted, for example, every second on the same transmission path as the program signal, but in such cases, it is necessary to prevent unauthorized decoding of the scramble key and reliably prevent unauthorized viewing. Therefore, the scramble key sent every second is changed in a short period of time (for example, 4; J10 seconds).

[Problems to be Solved by the Invention] In the method of changing the scramble key in a short time and sending it, the receiving side must take out the scramble key and descramble it every time it is sent. In such a case,
For example, in satellite broadcasting using FM, 07 N (c'a
If the ratio (rarrier to no ise) decreases, a lot of noise will be included in the video, audio, and control signals, making it impossible to extract the scramble key accurately. As a result, descrambling becomes impossible on the receiving side. especially,
In a system in which the scramble key is changed once every 10 seconds, a problem arises in that if the scramble key is incorrectly received once, the scramble cannot be descrambled for 10 seconds.

[Means for Solving the Problems] The decryption key transmission method according to the present invention divides information such as a program on the transmitting side, rearranges the order of the divided pieces, and transmits them to the receiving side. In a transmission method that reproduces information by rearranging it in the original order using a decryption key transmitted over the same transmission path, the decryption key is changed at relatively short time intervals and transmitted at this time interval, At the same time, a plurality of release keys are transmitted intermittently or continuously in association with time information.

[Operation] On the receiving side, the state of the transmission path to C/ is detected, and a key to be used for descrambling is determined in accordance with the state to C/. Since multiple decryption keys are transmitted at once in correspondence with time information, if a decryption key is correctly received even once within a predetermined period of time, even if C/ is low, the previously received key will be used. This makes it possible to descramble.

[Embodiments] Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the broadcasting system according to the present invention. In FIG. 1, A on the left side is a circuit configuration on the transmitting side, and B on the right side is a circuit configuration showing one of the many receiving sides. It is. In this embodiment, as an example, satellite broadcast radio waves are used as the transmission line 10 connecting the transmitting side A and the receiving side B. Therefore, this broadcasting system is a pay broadcasting system using satellites, and both the video signal and the audio signal are scrambled to prevent unauthorized viewing. In the following explanation, only video scrambling will be explained for convenience of explanation. Further, it is assumed that the deterioration of C/to (ratio between carrier and no ise) in the transmission line 10 is within 30 seconds at a time.

The configuration of the circuit shown in FIG. 1 will be explained.

On the transmitting side, 1 is a synchronization board on the transmitting side, 2 is a camera as a signal source (VTR or disk may be used), and 3 is a scrambler that scrambles the video output of camera 2.
4 is a KS generation circuit that generates a key Ks that is a random number >311P for scrambling;
It is synchronized with. &lKs is a decryption key for descrambling. 5 is a timer synchronized with the synchronization board 1; 6 is a signal forming circuit for sending out the key KS and other information in the signal format shown in A and B in FIG. 2; and 7 is a signal forming circuit shown in A or B in FIG. This is a superimposition circuit that superimposes a signal of the same format into one horizontal scanning period of VBr (vertical blanking period) in a television signal.

The timer 5 synchronizes the Ks generating circuit 4 and the signal forming circuit 6. 8 is an RF modulator, and this RF modulator 8
The output is transmitted via satellite to each receiving antenna (not shown) of a large number of receiving stations scattered throughout Japan.

At the receiving side B, from the receiving antenna to L N (not shown)
B (Low No.1se Block down
The output of the RF modulator 8 is supplied to the tuner 11 via a converter. The tuner 11 selects the received signal, converts it to an intermediate frequency (for example, about 4008H7), and performs FM detection in the detection circuit 12. The detection circuit 12 also generates a GCTi pressure, which is fed back to the tuner 11. The tuner 11 and the detection circuit 12 are the same as those of a normal BS tuner. 13 is a field memory for storing the output signal of the detection circuit 12 for two fields;
Consists of two 1-field memories. 14 is an output buffer, and 15 is an R/W controller that controls occupation and reading of the field memory 13. 16 is a synchronization separation circuit that separates the synchronization signal from the television signal output from the detection circuit 12, and 17 is a signal extraction circuit for extracting various signals in the VBI from the television signal. The signals shown in FIGS. 2A and 2B are extracted, sampled, and converted into digital signals. 18
is the so-called BE, which is the same as that used in teletext broadcasting.
This is an error correction circuit called the ST method. The output signal of the error correction circuit 18 is supplied to an error counter 23, a time code extraction circuit 19, and an encryption/charging processing circuit 31.

The information obtained by the encryption/billing processing circuit 31 is stored in the Ks memory A.
20 and KS memory B21, and is stored in each of these memories. Reference numeral 22 denotes a time code verification circuit, and each output of the time code extracting circuit 19 and the KS memory A20 is input to this circuit. Further, 32 is a C/N determination circuit, which is an AGC! output from the detection circuit 12! The C/N condition is determined based on the pressure. Receiving side B also has NOR
Gate 24, inverter 25, AND gate 26°27
, OR gate 28. The NOR gate 24 inputs the outputs of the C/N determination circuit 32 and the error counter 23, and provides the outputs to the inverter 25 and the AND gate 27. Inverter 25 provides its output to KS memory Δ20, time code matching circuit 22, and AND gate 26. The output of the time code matching circuit 22 is input to the remaining inputs of the AND gate 26, and the output of the Ks memory B21 is input to the remaining inputs of the AND gate 27. AND gate 2
Each output of 6.27 is applied to an OR gate 28. 29
30 is a random number generation circuit, and 30 is a line number conversion circuit. Upon receiving the output of the OR gate 28, the random number generation circuit 29 generates a random number. A control signal is given to the device 15.

Next, the operation of the circuit shown in FIG. 1 will be explained.

The operation of scrambling the video signal on the transmitting side A is performed in the video scrambler 3. In the video scrambler 3, the video signal output from the camera 2 is scrambled using a key Ks given from the KS generation circuit 4. The key KS and other signals used for scrambling are sent to a signal superimposing circuit 7 via a signal forming circuit 6, and this signal superimposing circuit 7 scrambles the signals supplied from the video scrambler 3. The signal is superimposed within one horizontal scanning period of the VBI of the video signal, and then sent to the receiving side via the RF modulator 8.

Next, the descrambling operation in the reception IQIB will be briefly described. Using the 24-bit key KS obtained in the Ks memory B21, the random number generation circuit 29 generates a PN sequence (22'
-1), and using this PN611, converter circuit 2
9, the signals are converted into line numbers (horizontal scanning line numbers) according to a predetermined procedure (for example, converting an 8-bit number in a ROM), and this number is used to input signals from the field memory 13 in the correct order. The original screen is read out and displayed on a display such as a CRT via the output buffer 14.

Such operation scrambles the TV screen at the transmitting end and
This is an example of descrambling on the receiving side, which is especially useful for line permutation. In this case, the random number used by the video scrambler 3 on the transmitting side A, the line number based on it, and the order thereof are opposite (complementary) to the actions performed by the random number generation circuit 29 and the conversion circuit 30 on the receiving side. It has become.

The operation of the circuit will be explained in more detail. In the scramble system, it is necessary to send and receive various information in addition to IKs. In the case of Japanese satellite broadcasting currently being broadcast, PCM
In addition to one voice, you can also send data.

In this embodiment, VBI is used as a generally applicable method.
Consider an example using 1H. Using one day for each field,
It is assumed that 184 bits excluding the header are used for control information and other purposes throughout the day. If you change IKs every 10 seconds, wI
Ks may be sent once every 10 seconds. The number of fields during this period is 60 x 10 = 600 fields, and the remaining 5
Information other than RKs can be sent using 99H. Furthermore, if KS is to be sent 10 times per second, 10X 10H, or 100H, will be used in 10 seconds. Therefore, in this case, the 101st day of 6001-1 is I
Used for transmitting FKs. The following explanation will be based on this condition. Remaining 600-101=499H each 1H
144 bits per bit can be allocated to control information regarding various types of υ1111, terminal access, etc.

FIG. 2 shows two types of data packets included in 1H of VBI. A is a data packet that sends JIKS information, and B is a data packet that sends control information other than IKs. In data packet A, the key KS is 24 bits, and the locks KS are sent together, for example, 6 WA (n=6). Further, data packets A and B each contain information such as a 6-bit header and a 40-bit time code. The contents of the header are shown in FIG.

The scrambled video signal output from the detection circuit 12 is stored alternately in the first and second one-field memories in the field memory 13 for each field according to the order of the fields.

R/W III 'ee device 15 is field memory 1
Descrambling on the receiving side is performed by controlling writing and reading in 3. That is, the R/W controller 15 writes the scrambled video signal of the nth field directly from the detection circuit 12 into the first one field memory in the field memory 13, and during this time, the
The video signal of the n-1th field written in the field memory of
Scanning lines are read out in an order that allows a normal image to be seen on a display device such as a T. For the video signal of the (n+1)th field, the video signal output from the detection circuit 12 is directly written into the second 1-field memory, and during this time, the video signal of the nth field is transferred from the first field memory according to the instructions of the conversion circuit 30. , read out each scanning line in an order that allows a normal image to be seen on a display device such as a CRT. By repeating this for each field, the descrambling operation is performed.

Error correction in the error correction circuit 18 is performed on the 190-bit portions shown in FIGS. 2A and 2B.

Of these 190 bits, 144 bits are encrypted. The encrypted part is decrypted by the encryption processing section of the encryption/charging processing circuit 31, and is stored in the Ks memory A20 or the KS memory 821 together with the time code. The Ks memory B21 currently stores a key KS for reading from the field memory 13, and the Ks memory A20 stores a plurality of keys KS to be used for reading from the field memory 13 in the future together with time codes.

Here, consider a case where the C/N decreases and errors increase.

When the C/N decreases, the AGC voltage of the detection circuit 12 increases (or decreases). When C/N falls below a certain value, C/N
The output of the N determination circuit 32 becomes high level. When the output of the C/N determination circuit 32 becomes high level, the output of the OR gate 24 becomes low level and the AND gate 27 is cut off, and the output of the inverter 25 becomes high level and the AND gate 26 becomes conductive. Furthermore, when the number of error corrections in the error correction circuit 18 exceeds a certain value, the error counter 23 outputs a high level, the output of the OR gate 24 becomes a low level, the AND gate 26 becomes conductive, and the AND gate 27 is cut off. be done. In the time code failure circuit 19, the time code of the non-encrypted part other than the control signal in the format shown in FIG.
Receive Δ seconds (4×4=16 bits in BCD). Assuming that this time code is sent every six fields, for example, the time code changes approximately every 0.1 seconds. On the other hand, the KS memory A20 contains six keys KS shown in FIG. 2A along with a time code of X×minutes ΔΔseconds. If △△
Assuming that seconds are 10 seconds, while the time code of 10 to 19 seconds is being sent, the time code of 810 to KS shown in Figure 4 is
20 is sent in the format shown in Figure 2, and when the C/N does not decrease and the number of error corrections is small, the KS
Ks is sent to the memory A20 every time the signal shown in FIG. 2A is received.
10~KsOO 24x6 pits are old.

Assuming that the C/N drops in XX minutes and 15 seconds and the output of the inverter 25 becomes high level, the rewriting of the 11'[KsS memory A20 is stopped thereafter.

The contents at that time are shown in Figure 4. Since the normal bone was 5 until the time of X×minutes and 15 seconds, the stored contents of the KS memory B21 are the same as those of the KS 10 in FIG. The time code verification circuit 22 starts verification after the output of the inverter 25 becomes high level. However, if the C/N is low, the time codes shown in FIGS. 2A and 2B often contain errors. While the output of the time code failure circuit 19 is at a low level (when the C/N is high), the timer is calibrated with the output of the time code failure circuit 19. The C/N drop does not continue throughout the day. Here, the period of C/N drop is considered to be 30 seconds or less, so the timer advances during that time and will not lag. Therefore, the time code is formed into four digits of minutes and seconds in the time-code matching circuit 22, and the code is compared with the minutes and seconds code shown in FIG. Therefore, at XX minutes and 20 seconds, KsS memory A
Data KS20 of xx minutes 20 seconds in 20 is read out, and this is transmitted to the random number generation circuit 29 through the AND gate 26 and the OR gate 28. The random number generation circuit 29 generates a random number based on Ks20, and from this random number. The conversion circuit 30 converts it into a line number. The rest of the operation is the same as when the C/N is high. For example, the C/N becomes high at XX minutes and 44 seconds,
When both the output of the C/N judgment circuit 32 and the output of the error correction counter 23 become low level, the output of the KS memory 821 (K S 50) is output to the AND gate 27 and the OR gate 2.
8 to the random number generation circuit 29 at XX minutes and 50 seconds.

KS memory A20 from XX minutes 44 seconds to XX minutes 50 seconds
A random number generated based on KS40 read from is used. At XX minute 50 seconds, K S shown in FIG.
50-KS 40' is sent and written to KS memory A20. In this case, the KS50 transferred to the KS memory B21 is sent first in FIG. 2B, and in the next field is sent in FIG. 2A. If necessary, fill in Figure 2 B for X x minutes 5
Figure 2 A may be sent following the interval of 0 seconds (more than 2 fields ago). In this way, it is possible to continue descrambling while continuously switching the key KS.

When sending the key KS before the old switching time, the time code matching circuit 22 also checks the time code for the contents of the KS message B21, and also sends the key KS with the time code to the Ks memory 821. All you have to do is remember. In this case too,
Time verification may be stopped only when the C/N drops.

Although the basic operation of the present invention has been explained above, the explanation will be supplemented with respect to FIG. 2 as well as FIG. 3.

As mentioned above, the headers in FIGS. 2A and 2B are 6 bits, and the meaning of each bucket can be associated with the values b-b5 as shown in FIG. 3, for example. For example, instead of sending 6 keys KS used in 1 minute, 60 UKs used in 10 minutes are sent together, and a packet containing multiple keys KS is sent using numbers 1 to 10 indicated by bo to b5 (see Figure 2). If we differentiate between A) and multiply the memory Furukawa of tIIKs in Figures 4 and 5 by 10, including the time code, we can handle the C/N drop of 10 minutes or less using the same concept, and the C/N NU; key KS below
You can continue descrambling if it has been less than 610 minutes since you were unable to receive the message. Note that the contents of the control information shown in FIG. 2B are determined depending on the system.

FIG. 6 shows an example of timing for sending the key KS using vertical bright line periods. In the previous explanation, consider XX minutes and 45 seconds. 81~
Bo indicates the sending time and sending interval of a signal in the format shown in FIG. 2B that is sent every 10 seconds, and B1 and 82 are separated by 600 fields.

Direction Δ, A7. . . . indicates the point in time when the keys Ks are sent together as shown in the present invention. Here B1
~Only the part of the same field as Bo, A1゜...
・A7... is shown. As shown in the enlarged view,
Send 158th KS50, 16) 1st KS50~K
By sending s 40', both can be sent in the same field. Also, when considering in units of 10 minutes, as shown in Figure 7, use 118 for 1 field, and
It is sufficient to send 10 types of FIG. 2A to FIGS. 8112 to 21H.

In the above embodiment, a scrambling method called line permutation was explained, but the present invention can of course be applied to other scrambling methods. Furthermore, when sending a plurality of keys (n keys), they can be sent intermittently or continuously. Furthermore, the basic idea of the present invention can be applied to various pay broadcasting systems other than satellite broadcasting.

[Effects of the Invention] As is clear from the above description, according to the present invention, in addition to transmitting keys individually, the decoding key for descrambling used on the receiving side in a pay broadcasting system is It is associated with information and sent to a storage unit for a predetermined period of time to be stored. Usually, a key that changes from time to time is used to perform descrambling, and when the C/N drops, the time is compared with the previously sent key. Since you can use the appropriate key,
Descrambling is not interrupted on the receiving side.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram showing an embodiment of the present invention, Fig. 2 is an explanatory drawing showing two types of data packets, Fig. 3 is an explanatory drawing showing the contents of Heragu in a table, Figs. FIG. 5 is an explanatory diagram showing the relationship between time and keys in a table, and FIGS. 6 and 7 are explanatory diagrams showing the arrangement state of data packets. [Description of symbols] 3...Video scrambler 4...KS generation circuit 7...Signal superimposition circuit 13...Field memory 15-R/1ItllW 19...Time code failure circuit 2o...KS Memory A 21...KS memory B 22...Time code verification circuit 29...Random number generation circuit 30...Line number conversion circuit 31...llil number/billing processing circuit 32...C/ N judgment circuit

Claims (3)

[Claims] (1) When transmitting information from the sending side to the receiving side, the sending side divides the information and rearranges the order of the divided information, and the receiving side rearranges the information in the original order using a decryption key. In a transmission method for reproducing information, the decryption key is changed at relatively short time intervals, and
A method for transmitting a decryption key, characterized in that the decryption key is transmitted one by one, and the decryption key is also transmitted intermittently or continuously in a plurality of the decryption keys in association with time information. (2) A decryption key transmission method according to claim (1), characterized in that time information is associated with each of the plurality of decryption keys, and the time information and the decryption key are transmitted together. (3) In claim (1) or (2), the receiving side detects a change in the C/N of the signal transmission path, and individually transmits the key to be used in response to the change in the C/N. A decryption key transmission method is characterized in that the decryption key is switched to either a key that is transmitted in correspondence with time information or a key that is transmitted all at once in correspondence with time information.