JPH0241024A - Signal converter - Google Patents

Abstract

PURPOSE:To increase the signal conversion speed without increasing power consumption by turning on a Darlington off-buffer when an output signal goes from a low level to a high level so as to charge a capacitive load quickly connecting to an output terminal. CONSTITUTION:When an output transistor (TR) Q4 is turned off, A Darlington off-buffer circuit 3 is turned on and a TR Q11 is deeply reverse-biased. When the output TR Q4 is turned on and the circuit transits the OFF state, the leading of the output voltage is sufficiently longer than the leading of the base potential of the output TR Q4 and then a clamp TR Q13 keeps the reverse bias state. Thus, the TR Q4 is over-driven through resistors R2, R7 to reduce the turn-on time. Thus, the signal conversion speed is quickened.

Description

[Detailed Description of the Invention] (Summary) It relates to a signal conversion device, and in particular includes an emitter-coupled logic circuit having a differential input stage and two output transistors connected to the differential input stage in a totem pole format. (E
Regarding a signal conversion device that converts an output signal of a transistor-transistor-logic (TTL) signal into a transistor-transistor-logic (TTL) signal, the purpose is to increase the speed of signal conversion without increasing power consumption. Emitter-coupled logic (ECL) has a differential input stage formed by a signal input side transistor and a reference power supply input side transistor, and two transistors connected to this differential input stage in a totem pole format. Transistor-transistor logic (TTL)
A signal conversion device that converts the signal into a signal includes a Darlington off buffer circuit that operates and turns on when the output signal changes from a low level to a high level, a signal input side transistor of the differential input stage, and a reference power input side transistor. The circuit is configured to include a circuit that clamps the collector of the circuit, and a bias circuit that applies a bias voltage to the clamp circuit.

[Industrial application field]

The present invention relates to a signal conversion device, and more particularly, to a signal conversion device that has a differential input stage and two output transistors connected to the differential input stage in a totem-pole manner, and converts the output signal of an emitter-coupled logic (ECL). The present invention relates to a signal conversion device that converts a signal into a transistor-transistor logic (TTL) signal. In electronic computers, etc., logic circuits are constructed using transistor-transistor logic (TTL), which uses the emitter of a multi-emitter transistor as an input to form the logic, and connects the collector output to the base of an amplifier circuit.
) is often adopted.

Furthermore, in recent years, in fields where high speed is required, such as in supercomputers and ultra-large computers, emitter-coupled logic (ECL), which is configured with emitter-coupled transistors and is capable of high-speed operation, is sometimes employed.

By the way, such devices that operate with TTL and ECL
In some cases, a signal from an ECL-operated device is transmitted to a TTL-operated device by combining the ECL-operated device and the TTL-operated device. In such a case, the voltage level and other specifications of the signal of the device using ECL and the signal of the device using TTL are different (for example, -1.8v for ECL).
~-0,8V, TTL voltage is Ov~3v). It is necessary to insert a signal converter between the Konotame and cholera equipment to convert the ECL signal to a TTL signal.

[Conventional technology]

As a conventional signal conversion device as described above, there is one shown in FIG. In the figure, ISO is a current source Ql connected to the negative power supply (VEE), Q2 is the first and second transistors forming a differential stage that receives the output of the ECL circuit, and a reference voltage is applied to the base of the first transistor Q1. (VREF) is
Further, an input signal is input to the base of the second transistor Q2. In addition, in the same figure, R1 and R2 are the first
and the collectors of the second transistor are connected to the positive power supply (VC
Q3.C) and first and second resistors connected to Q3. Q
4 are the third and fourth terminals connected to the ground (GND) in a totem pole manner via the third resistor R3 from this positive power supply.
The base of the third transistor Q3 is connected to the transistor side of the first resistor R1, the base of the fourth transistor Q4 is connected to the transistor side of the second resistor R2, and the base of the third transistor Q3 is connected to the transistor side of the second resistor R2. transistor Q3 and the fourth
The connection point of transistor Q4 is used as an output terminal.

Further, R4 is a fourth resistor that grounds the base of the fourth transistor Q4.

According to this signal conversion device, when the ECL low level signal is input to the input terminal, a current flows through the first transistor Q1 in relation to the reference voltage, and the current flows through the first resistor R1.
voltage decreases, and the third transistor Q3 turns off. At this time, since no current flows through the second transistor Q2, the base of the fourth transistor Q4 is biased by the second resistor R2 and the fourth resistor R4.
Transistor Q4 is in the on state and the output terminal is TTL
A low level signal is output.

Furthermore, when a high level ECL signal is input to the input terminal, current flows through the second transistor Q2 in relation to the reference voltage, the voltage across the second resistor R2 decreases, and the fourth transistor Q4 turns off. state. At this time, since no current flows through the first transistor Q1, the first resistor R
1 rises, the third transistor Q3 turns on, and a TTL high-level signal is output to the output terminal.

With such a signal converter, ECL signals can be converted to TTL.
signal.

(Problems to be Solved by the Invention) However, in the conventional signal conversion device described above, there is a problem that there is a limit to increasing the signal conversion speed.

When the fourth transistor Q4 is in the on state, the fourth transistor Q4 is in a fully saturated state and requires time to recover from the saturated state.
This is because the turn-off time of No. 4 becomes longer.

Also, at this time, in order to turn off the third transistor Q3, the base potential of the third transistor Q3 needs to be lower than the saturation voltage between the collector and emitter of the fourth transistor Q4. Since the base potential of the transistor Q3 is pulled up by the first resistor, the value of the first resistor R1 may be made small in order to increase the speed. In order to keep the resistor R1 in an off state, it is necessary to increase the current flowing through the resistor R1 to ensure a voltage drop across the resistor R1, which results in an increase in power consumption.

Therefore, an object of the present invention is to provide a signal conversion device that can increase the speed of signal conversion without increasing power consumption.

(Means for solving the problems) In the present invention, the means for solving the above problems are as follows:
As shown in FIG. 1, the reference power input side transistor Q1
and a signal input side transistor Q2, and two transistors Q3 . output stage 2 formed by Q4 and an emitter coupling logic (EC
In a signal conversion device that converts an output signal of L) into a transistor-transistor-logic (TTL) signal,
a Darlington off buffer circuit 3 that operates and turns on when the output signal changes from low level to high level;
a first clamp circuit 4 that clamps the collectors of the reference power input transistor Q1 and the signal input transistor Q2 of the differential input stage 1; a bias circuit 5 that applies a bias voltage to the first clamp circuit 4; The second clamp circuit 6 clamps the base-collector of the transistor Q4, which operates when the output signal changes from a high level to a low level, of the two transistors connected in a totem pole manner. .

[Effect]

According to the present invention, the Darlington off-buffer circuit 3 operates when the output signal changes from low level to high level, and rapidly charges the capacitive load connected to the output terminal that is turned on. Improve characteristics. In addition, since the first clamp circuit 4 clamps the collectors of the reference power input side transistor Q1 and the signal input side transistor Q2 of the differential input stage 1, the current flowing through the resistor R1 increases even if the value of the resistor R1 is decreased. Since there is no power consumption, it is possible to operate at high speed without increasing power consumption. In addition, the second clamp circuit 6 reduces the base current of the transistor Q4 by bypassing the base current of the transistor Q4, one of the transistors connected in a totem pole format, to the collector side.As a result, the storage time of the transistor Q4 is shortened. This shortens the turn-off time of transistor Q4.

〔Example〕

Embodiments of the signal conversion device according to the present invention will be described below with reference to the drawings.

FIG. 2 shows an embodiment of a signal conversion device according to the present invention. In the figure, ISO is a current source connected to a negative power supply (VEE), Ql and Q2 are first and second transistors forming a differential stage that receives the output of the ECL circuit, and the first transistor Q1 A reference voltage (V
REF) is inputted thereto, and serves as a transistor on the reference power input side, and an input signal is inputted to the base of the second transistor Q2, making it serve as a transistor on the signal input side.

A clamp circuit is provided in this differential input installation. This clamp circuit consists of three transistors Q5.
Q6. Consisting of QIO and two resistors R4 and R6,
A bias voltage is applied by a bias circuit. The bias circuit here consists of three base-collector coupled transistors Q7. Q8. Q9
and one resistor R5. Note that the forward voltage VDF when the transistors Q7 to Q9 operate as diodes is equal to the pace-emitter forward voltage VBE of the transistors.

In the clamp circuit, by selecting appropriate values for the three resistors R1, R2, and R7, when the transistor Q5 is in the on state, the sonoemitter potential is VDF (Qs) + VDF (
Qa) +VDF (Q7)-VBE (Q6)-V
DF (Qs) = VBE and null. Also, when transistor QIO is on, VDF (Q9) - VBE (QI
O) = (IV Tonal.

In addition, in the same figure, R1 and R2 are the first and second
The collectors of transistors Ql and Q2 are connected to the positive power supply (VC
Q3.C) and first and second resistors connected to Q3. Q
4 are the third and fourth terminals connected to the ground (GND) in a totem pole manner via the third resistor R3 from this positive power supply.
The base of the third transistor Q3 is connected to the transistor side of the first resistor R1 via a Darlington off-buffer circuit, and the base of the fourth transistor Q4 is connected to the transistor side of the first resistor R1. It is connected to the transistor side of R2 via an active pull-down circuit. The above Darlington off-buffer circuit is composed of one transistor Qll, one resistor R8, and a reverse bias prevention transistor Q12.

Further, the above active pull-down circuit is formed of one transistor Q14 and two resistors R9 and RIO. The above Darlington off-buffer circuit is activated and turns on when the output signal changes from low level to high level, and quickly removes the capacitive load of the element connected to the output terminal via the third resistor R3. to improve the rise of the output signal. Further, the active pull-down circuit speeds up the rise of the base potential of the output transistor Q4 and shortens the turn-on time.

Furthermore, in this embodiment, a clamp transistor Q13 is provided between the collector of the output transistor Q4 and the above-mentioned second resistor R2. This clamp transistor Q13 is pace-collector coupled and operates as a diode. This clamp transistor Q13 bypasses the excess base current of the transistor Q4 to the collector side when the output transistor Q4 is turned on, and eliminates excess accumulated carriers to bring the output transistor Q4 into an extremely shallow saturation state, thereby minimizing the accumulation time. The purpose is to shorten the length and speed up the process. Additionally, this clamp transistor Q13 overdrives the base current of the output transistor Q4, and
reduce turn-on time. That is, the output transistor Q
When Q4 is off, the Darlington off buffer circuit is off and transistor Qll is deeply reverse biased. When the output transistor Q4 turns on and the Darlington off-buffer circuit turns off, the fall of the output voltage is sufficiently slow compared to the rise of the base potential of the output transistor Q4, and therefore the clamp transistor Q13 is Maintain bias state. Therefore, the second resistor R2 and the seventh resistor R
7, output transistor Q4 is overdriven to reduce turn-on time. Then, when the output voltage drops to a predetermined level, the clamp transistor Q1
3 becomes conductive and shifts to clamping operation.

Furthermore, the above-mentioned reverse bias prevention transistor Q12 is
Preventing reverse bias between the base and emitter when the transistor Qll transitions from the on state to the off state, and applying a reverse bias voltage to the base of the transistor Q3,
Carriers accumulated in the base of transistor Q3 are flowed out to the base side of transistor Q12 and to the side of resistor R8 to shorten the turn-off time. This is because the base potential of transistor Q3 falls slowly due to the voltage drop across resistor R1.
This prevents the transistor Q12 from being deeply reverse biased between the base and emitter of the transistor Qll. Furthermore, the transistor Q5 is provided to clamp the base potential of the transistor Qll, but since the current flows to the transistor Q1 through the transistor Q5 and the transistor Q6, the current flowing to the resistor R1 can be reduced, and this and the clamping of the transistor Q5 Accordingly, the resistance value of the resistor R1 can be reduced, and the rise of the base of the transistor Qll can be made faster.

Therefore, according to this embodiment, since the above-described circuit is provided, the signal conversion speed of the signal conversion device can be increased. In the above embodiment, the signal conversion device is provided with means such as a clamp circuit, a bias section, a Darlington off-buffer circuit, an active pull-down circuit, a clamp transistor, etc., but it is not necessary to provide these means. The speed of signal conversion can be improved simply by providing a circuit, a bias section, and a Darlington off-buffer circuit.

(Effects of the Invention) As explained above, according to the present invention, since the signal conversion device is provided with a clamp circuit, a bias section, and a Darlington off buffer circuit, the turn-on and turn-off times of the output transistor can be shortened. Yes, EC
This has the effect of increasing the conversion speed of L-TTL signals.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a circuit diagram showing an embodiment of a signal converting device according to the present invention, and FIG. 3 is a circuit diagram showing a conventional signal converting device. 1... Differential input stage 2... Output stage 3... Darlington off-buffer circuit 4... Clamp circuit 5... Bias circuit tree Invention/I &, Figure 1 of theory

Claims (1)

[Claims] A differential input stage formed by a signal input side transistor and a reference power supply input side transistor, and two transistors connected to this differential input stage in a totem pole format, and an emitter cup. The output signal of ring logic (ECL) is converted to transistor transistor logic (TTL).
In a signal conversion device that converts signals into
a first clamp circuit (4) that clamps the collectors of the signal input side transistor and reference power input side transistor of the differential input stage; and a bias circuit that applies a bias voltage to the first clamp circuit (4). (5) and a second clamp circuit that clamps between the base and collector of the transistor that operates when the output signal changes from high level to low level among the two transistors connected in the totem pole format (
6) A signal conversion device comprising: