JPH0239202A - Process control circuit - Google Patents

Process control circuit

Info

Publication number
JPH0239202A
JPH0239202A JP18869088A JP18869088A JPH0239202A JP H0239202 A JPH0239202 A JP H0239202A JP 18869088 A JP18869088 A JP 18869088A JP 18869088 A JP18869088 A JP 18869088A JP H0239202 A JPH0239202 A JP H0239202A
Authority
JP
Japan
Prior art keywords
control
load
circuit
control circuit
deviation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18869088A
Other languages
Japanese (ja)
Inventor
Yoshihisa Uchida
内田 義久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP18869088A priority Critical patent/JPH0239202A/en
Publication of JPH0239202A publication Critical patent/JPH0239202A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To avoid deterioration of the control result despite deterioration of the load for a process control circuit which includes the proportion, integration and differentiation elements by adding a division circuit to the input side to divide the input by the load applied to a process or the manipulated variable. CONSTITUTION:A PID control circuit controls the process of an integral element 2 including an equivalent dead time element 1 via a PID controller 7. This controller 7 includes a proportion element 4, an integration element 5 and a differentiation element 6. At the same time, a division circuit 8 is set at the input side of the element 4. The control deviation between the target value (r) and the controlled variable (x) is inputted to the circuit 8 together with the manipulated variable (m). The circuit 8 has a function to divide the control deviation (r-x) by the variable (m). In such a constitution, the deviation of the variable (x) is gradually reduced as the load is deteriorated. In other words, the control result is improved with deterioration of the load.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 この発明はプロセス制御回路、主としてむだ時間を含む
積分性プロセス又はむだ時間を含む一次遅れプロセスに
対するPTD制御回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a process control circuit, mainly a PTD control circuit for an integral process including dead time or a first-order lag process including dead time.

(ロ)従来の技術 例えば、むだ時間を含む積分性プロセスでは、第4図に
示すように、等価むだ時間(むだ時間T:)要素1を含
む積分性要素(積分時定数↑)2のプロセス3において
、制御量χを目標値rに制御するために、比例(P)゛
要素4と積分(1)要素5と微分(D)要素6からなる
IID調節237が使用される。このプロセス3におい
て、従来、プロセスにかかる負荷Vの変化により、制御
計Xが目標値rから偏位したとき、制御計Xを目標値r
に制御す名ために、PID調節器7の各制御パラメータ
をジーグラ・ニコルスの提唱する値(比例ゲイン:1.
2T/L、積分時間:2■2、微分時間:L/2)に設
定している。このジーグラ・ニコルスの値は、プロセス
に加わる負荷が定格(100%)のときに最適な制御結
果が得られるように決められたものである。
(b) Conventional technology For example, in an integral process that includes dead time, as shown in FIG. 3, an IID adjustment 237 consisting of a proportional (P) element 4, an integral (1) element 5, and a differential (D) element 6 is used to control the control amount χ to the target value r. In this process 3, conventionally, when the control meter X deviates from the target value r due to a change in the load V applied to the process, the control meter
In order to control the PID controller 7, each control parameter of the PID controller 7 is set to the value proposed by Ziegler-Nichols (proportional gain: 1.
2T/L, integral time: 2■2, differential time: L/2). This Ziegler-Nichols value is determined so that the optimum control result can be obtained when the load applied to the process is at the rated value (100%).

(ハ)発明が解決しようとする課題 上記したジーグラ・ニコルスの値を採用した従来のもの
では、負荷が100%の場合、最適な制御結果が得られ
るから問題ないが、プロセスにかかる負荷Vが低下する
につれて、プロセス特性の積分時定数〒、むだ時間rが
大きくなるので、制御結果は、第5図に示すように負荷
の低下につれて、次第に応答が振動的になってくる。第
5図の例示は、定格時におけるプロセスの積分時定数T
=4.75分、むだ時間I、=2.24分とし、負荷が
100%から20%まで、20%ずつ低下していったと
きの計算結果である。100%時の応答曲線は10分、
20分、30分に偏差0となっている。
(c) Problems to be Solved by the Invention With the conventional system that uses the Ziegler-Nichols value described above, when the load is 100%, optimal control results can be obtained, so there is no problem, but when the load V applied to the process As the load decreases, the integral time constant 〒 and the dead time r of the process characteristics increase, so that as the load decreases, the response of the control result gradually becomes oscillatory, as shown in FIG. The example in FIG. 5 shows the integral time constant T of the process at rated
= 4.75 minutes, dead time I = 2.24 minutes, and these are the calculation results when the load decreases by 20% from 100% to 20%. The response curve at 100% is 10 minutes,
The deviation is 0 at 20 minutes and 30 minutes.

以にのように、従来の制御回路では、負荷が低下するに
つれて、制御結果が悪くなるという問題があった。
As described above, the conventional control circuit has a problem in that the control result deteriorates as the load decreases.

この発明は、上記問題点に着目してなされたものであっ
て、負荷が低下しても制御結果が悪くならない、むしろ
良好となるプロセス制御回路をを供することを目的とし
ている。
The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a process control circuit that does not deteriorate the control results even when the load decreases, but rather improves the control results.

(ニ)課題を解決するための手段及び作用この発明のプ
ロセス制御回路は、比例要素、積分要素、微分要素とを
含むものにおいて、入力側に、プロセスにかかる負荷又
は、操作量で入力を割る割算回路を特徴的に設けている
(d) Means and operation for solving the problem The process control circuit of the present invention includes a proportional element, an integral element, and a differential element, and divides the input by the load applied to the process or the manipulated variable on the input side. It features a dividing circuit.

このプロセス制御回路では、負荷が低下した場合、例え
ば、第3図に示すように、負荷が低下するにつれて応答
特性の振動が小さくなり、制御結果が良好となる。
In this process control circuit, when the load decreases, for example, as shown in FIG. 3, as the load decreases, the vibration of the response characteristic becomes smaller and the control result becomes better.

(ホ)実施例 以下、実施例により、この発明をさらに詳細に説明する
(E) Examples The present invention will be explained in more detail with reference to Examples below.

第1図は、この発明の一実施例を示すPID制御回路の
ブロック図である。このPrD制f711 @路も、等
価むだ時間要素lを含む積分性要素2のプロセス3をP
ID調節器7で調節するものであり、PID調節器7は
比例要素4、積分要素5及び微分要素6を備えている。
FIG. 1 is a block diagram of a PID control circuit showing one embodiment of the present invention. This PrD system f711 @ path also converts process 3 of integral element 2 containing equivalent dead time element l to P
It is adjusted by an ID regulator 7, and the PID regulator 7 includes a proportional element 4, an integral element 5, and a differential element 6.

この点、第4図に示す従来のPID制御回路と同様であ
る。
In this respect, it is similar to the conventional PID control circuit shown in FIG.

この実施例PID制御回路の特徴は、比例要素40入力
側に、割算回路8を設けたことである。
A feature of the PID control circuit of this embodiment is that a division circuit 8 is provided on the input side of the proportional element 40.

この割算回路8には、PrD制御回路の入力、つまり、
目標値r−制御量Xの制御偏差が入力されるとともに、
PID調節器7の出力、つまり操作4itmが加えられ
ている。この割1γ回路8は、制御偏差r−xを操作量
mで割算する機能を有する。
This division circuit 8 has the input of the PrD control circuit, that is,
The target value r−control deviation of the control amount X is input, and
The output of the PID regulator 7, that is, the operation 4itm is added. This dividing 1γ circuit 8 has a function of dividing the control deviation r−x by the manipulated variable m.

このPID制御回路において、第4図の回路と同じ特性
のプロセス、つまり定格時の積分時定数T=4.75分
、むだ時間L=2.24分を対象にジーグラ・ニコルス
のPIDパラメータを設定し、負荷Vを100%から2
0%まで20%ずつ低下していったとき、計算結果が第
3図に示すようになった。この第3図の応答特性をみる
と、9、荷100%の応答曲線は10分、20分、30
分に偏差0となり、第5図と同じであるが、制?I@x
の偏差は負荷力)゛低下するにつれて、11111次小
さくなっている。つまり、負荷が低下するにつれて、か
えって制御結果が良好となっている。
In this PID control circuit, the Ziegler-Nichols PID parameters are set for a process with the same characteristics as the circuit in Figure 4, that is, for the rated integral time constant T = 4.75 minutes and dead time L = 2.24 minutes. Then, the load V is increased from 100% to 2
When it decreased by 20% to 0%, the calculation result became as shown in FIG. Looking at the response characteristics in Figure 3, the response curves for 9.100% load are 10 minutes, 20 minutes, and 30 minutes.
The deviation becomes 0 in minutes, which is the same as in Figure 5, but is there a limit? I@x
As the load force decreases, the deviation becomes 11111 times smaller. In other words, as the load decreases, the control results actually become better.

なお、ヒ記T流側では、操作1mで制御偏差r−Xを割
算しているが、操作1mは、常に負荷Vとなるように、
制御回路が働いているので、操作timは負荷■である
と見做してよい。したがって、負荷Vがわかっている場
合、つまり既知の場合は、第2図に示すように、負荷V
を割算回路8に加え、制御偏差r−xを、負荷Vで割算
しても、同様の結果が得られる。第2図のPTD制御回
路において、操作量mで制御偏差r−xを割る回路を除
けば、その他の回路部分は第1図のPID制御回路と同
様である。
In addition, on the T flow side of H, the control deviation r-X is divided by 1 m of operation, but 1 m of operation is always equal to load V.
Since the control circuit is working, the operation tim can be considered to be a load ■. Therefore, if the load V is known, that is, it is known, the load V
A similar result can be obtained by adding the control deviation rx to the division circuit 8 and dividing the control deviation rx by the load V. In the PTD control circuit shown in FIG. 2, except for the circuit that divides the control deviation r-x by the manipulated variable m, the other circuit parts are the same as the PID control circuit shown in FIG. 1.

(へ)発明の効果 この発明によれば、調節器の入力を出力(tW作@)で
割る割tγ回路を設けることにより、プロセスにかかる
負荷の低下につれて、制御量の制御結果が悪(なるとい
う従来の欠点を解消し、負荷の低下につれてむしろ良好
な制御結果を得ることができる。この効果は、むだ1I
iIF間を含む積分性プロセスに対し、ジーグラ・ニコ
ルスの制御パラメータを用いた例示の場合は、もちろん
あらゆるプロセス制御系についてあてはまる。
(f) Effects of the Invention According to the present invention, by providing a division tγ circuit that divides the input of the regulator by the output (tW operation @), as the load on the process decreases, the control result of the controlled variable becomes worse. It is possible to eliminate the conventional drawbacks of 1I and obtain better control results as the load decreases.
The example of using Ziegler-Nichols control parameters for an integral process involving an iIF interval is of course applicable to any process control system.

【図面の簡単な説明】 第1図は、この発明の一実施例を示すPrD制御回路の
ブロック図、第2図は、この発明の他の実施例を示すP
IDffI制御回路のブロック図、第3図は、上記実施
例PID制御回路の応答特性の一例を示す図、第4図は
従来のP r D iIl+御回路を示すブロック図、
第5図は従来のPIDfflII御回路の応答特性の一
例を示す図である。 3:プロセス、  4:比例要素、 5:積分要素、  6;微分要素、 7:PrD調節器、8:割算回路、 m:操作量、   X:制御量、 r:目標値、   ■=負負荷
[Brief Description of the Drawings] Fig. 1 is a block diagram of a PrD control circuit showing one embodiment of the present invention, and Fig. 2 is a block diagram of a PrD control circuit showing another embodiment of the invention.
A block diagram of the IDffI control circuit, FIG. 3 is a diagram showing an example of the response characteristics of the PID control circuit of the above embodiment, FIG. 4 is a block diagram showing a conventional P r D i I + control circuit,
FIG. 5 is a diagram showing an example of response characteristics of a conventional PIDfflII control circuit. 3: Process, 4: Proportional element, 5: Integral element, 6: Differential element, 7: PrD controller, 8: Divide circuit, m: Manipulated amount, X: Controlled amount, r: Target value, ■= Negative load

Claims (1)

【特許請求の範囲】[Claims] (1)比例要素、積分要素、微分要素を含むプロセス制
御回路において、 入力側に、プロセスにかかる負荷又は、操作量で入力を
割る割算回路を設けたことを特徴とするプロセス制御回
路。
(1) A process control circuit including a proportional element, an integral element, and a differential element, characterized in that the input side is provided with a divider circuit that divides the input by the load applied to the process or the manipulated variable.
JP18869088A 1988-07-28 1988-07-28 Process control circuit Pending JPH0239202A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18869088A JPH0239202A (en) 1988-07-28 1988-07-28 Process control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18869088A JPH0239202A (en) 1988-07-28 1988-07-28 Process control circuit

Publications (1)

Publication Number Publication Date
JPH0239202A true JPH0239202A (en) 1990-02-08

Family

ID=16228127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18869088A Pending JPH0239202A (en) 1988-07-28 1988-07-28 Process control circuit

Country Status (1)

Country Link
JP (1) JPH0239202A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266906B2 (en) 2005-09-28 2007-09-11 Mitutoyo Corporation Measuring tool

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266906B2 (en) 2005-09-28 2007-09-11 Mitutoyo Corporation Measuring tool

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