JPH0237783A - Manufacture of end-face light-emitting type optical semiconductor device - Google Patents

Manufacture of end-face light-emitting type optical semiconductor device

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Publication number
JPH0237783A
JPH0237783A JP63188720A JP18872088A JPH0237783A JP H0237783 A JPH0237783 A JP H0237783A JP 63188720 A JP63188720 A JP 63188720A JP 18872088 A JP18872088 A JP 18872088A JP H0237783 A JPH0237783 A JP H0237783A
Authority
JP
Japan
Prior art keywords
wafer
light
face
ohmic electrode
optical output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63188720A
Other languages
Japanese (ja)
Inventor
Koji Nakano
仲野 弘司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63188720A priority Critical patent/JPH0237783A/en
Publication of JPH0237783A publication Critical patent/JPH0237783A/en
Pending legal-status Critical Current

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  • Optical Elements Other Than Lenses (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Led Devices (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To accurately evaluate an optical output characteristic of a light-emitting element on a wafer by a method wherein an optical output face and an optical reflection face are formed on the wafer so as to be faced by utilizing an end face of an element region. CONSTITUTION:A semiconductor substrate 10 and a P-side ohmic electrode 60 are brought into contact only in a contact region 50; this region is separated from the semiconductor substrate 10 in a peripheral part by using grooves 30 which are deeper than a p-n junction region 20. Since an element isolation region 90 is formed in the P-side ohmic electrode 60, light-emitting elements are separated electrically inside a wafer. Accordingly, when an N-side electrode is taken out from the whole surface of an N-side ohmic electrode 70 and an electric current flows to a gold-plated layer 80 on the P-side ohmic electrode 60 of the individual light-emitting elements, a beam is radiated through a silicon nitride film 40 from an optical output face 100; this beam is reflected by an optical reflection face 110 at an end part of an adjacent element facing the optical output face 100; the beam is taken out in a vertically upward direction; accordingly, a photodetector is arranged in parallel with a wafer face. Thereby, it is possible to accurately evaluate an optical output characteristic of the light-emitting elements on the wafer.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は端面発光型光半導体装置の製造方法に関し、特
に端面発光素子の光出力特性の評価を簡便に行い得るウ
ェハーの製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an edge-emitting optical semiconductor device, and more particularly to a method for manufacturing a wafer that allows easy evaluation of the light output characteristics of an edge-emitting element.

〔従来の技術〕[Conventional technology]

従来、端面発光型光半導体装置は、端面発光素子をウェ
ハー上で光出力方向と垂直方向にそれぞれヘキ開して互
いに分離することによって製造され、このとき形成され
るヘキ開面が光出力面として使用される。従って、光出
力特性の測定はウェハーから分離された個々の素子に対
して行われ、このヘキ開面と対面する位置に受光素子を
設置して評価する。
Conventionally, edge-emitting optical semiconductor devices are manufactured by cleaving edge-emitting elements on a wafer in a direction perpendicular to the light output direction and separating them from each other, and the cleavage planes formed at this time are used as light output surfaces. used. Therefore, the optical output characteristics are measured for each element separated from the wafer, and the light receiving element is placed at a position facing the cleavage plane for evaluation.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

このように、従来の製造方法によれば、端面発光型発光
素子の光出力特性の評価は、ウェハー上から個々に分離
された状態で行なう必要があるため、評価試験に手間取
り生産性を著しく阻害している。また、生産管理上必要
なウェハー面内における素子の特性分布評価データも得
にくい等の欠点がある。
As described above, according to the conventional manufacturing method, the evaluation of the light output characteristics of edge-emitting light emitting devices needs to be performed individually separated from the wafer, which takes time and significantly impedes productivity in evaluation tests. are doing. Further, there are drawbacks such as difficulty in obtaining data for evaluating the characteristic distribution of elements within the wafer plane, which is necessary for production control.

本発明の目的は、上記の情況に鑑み、発光素子の光出力
特性評価試験をウェハー上で精度高く行い得る端面発光
型光半導体装置の製造方法を提供することである。
In view of the above-mentioned circumstances, an object of the present invention is to provide a method for manufacturing an edge-emitting optical semiconductor device in which a light output characteristic evaluation test of a light emitting element can be performed with high precision on a wafer.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によれば、端面発光型光半導体装置の製造方法は
、一つの半導体基板上に複数個の端面発光型光半導体素
子を電気的に互いに分離して行列配置する素子形成工程
と、前記端面発光型半導体素子の光出力に対する基板上
方への光反射面を光出力面に対向させてそれぞれの隣接
素子の端部に形成する光反射面の形成工程とを含む半導
体ウェハーの製造工程を備えることを含んで構成される
According to the present invention, a method for manufacturing an edge-emitting optical semiconductor device includes an element forming step in which a plurality of edge-emitting optical semiconductor elements are electrically separated from each other and arranged in rows and columns on one semiconductor substrate; A semiconductor wafer manufacturing process including a step of forming a light reflecting surface to face the light output surface and forming a light reflecting surface upwardly on the substrate for the light output of the light emitting semiconductor element at the end of each adjacent element. It consists of:

〔実施例〕〔Example〕

以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.

第1図および第2図、第3図はそれぞれ本発明をFP型
型光光ダイオード製造に実施した場合の一実施例を示す
半導体ウェハーの部分斜視図およびそのA−A’ 、B
−B’断面図である。
FIG. 1, FIG. 2, and FIG. 3 are partial perspective views of a semiconductor wafer showing an embodiment of the present invention in the production of FP type photodiodes, and AA' and B thereof, respectively.
-B' sectional view.

すなわち、本実施例によれば、半導体ウェハー上には、
片面発光の複数個のFP型型光光ダイオード素子光出力
面100をそれぞれ同一方向に向けると共に、互いに対
向する行の一方の側の素子が他方の側の素子の出力光を
垂直上方向に反射するように光反射面110をそれぞれ
の端部に設けて行列配置される。
That is, according to this embodiment, on the semiconductor wafer,
A plurality of single-sided light-emitting FP type photodiode elements have their light output surfaces 100 facing in the same direction, and the elements on one side of the mutually opposing row reflect the output light of the elements on the other side vertically upward. A light reflecting surface 110 is provided at each end so that the light reflecting surfaces 110 are arranged in a matrix.

まず、n型InP基板10上にエピタキシャル成長によ
りpn接合領域20を形成した後、ホトリソグラフィ技
術を使いこれを選択的にエツチングして、電流狭窄およ
びエピタキシャル層分離のための溝30と光出力面10
0と光反射面110とをpn接合領域20よりもそれぞ
れ深く形成する。この際、電力狭窄およびエピタキシャ
ル層分離のための溝30と光出力面100とは、結晶の
面方位によるエツチング・レートの差が顕著でない条件
をもつブロム系のエツチング液でエツチングし、また、
光反射面110は硫酸系のエツチング液を用い結晶の両
方値によるエツチング・レートの差が顕著な条件でエツ
チングする。
First, a pn junction region 20 is formed by epitaxial growth on an n-type InP substrate 10, and then selectively etched using photolithography to form a groove 30 for current confinement and epitaxial layer separation and a light output surface 10.
0 and the light reflecting surface 110 are each formed deeper than the pn junction region 20. At this time, the groove 30 for power confinement and epitaxial layer separation and the light output surface 100 are etched with a bromine-based etching solution under the condition that the difference in etching rate depending on the plane orientation of the crystal is not significant.
The light reflecting surface 110 is etched using a sulfuric acid-based etching solution under conditions where there is a significant difference in etching rate depending on both crystal values.

ついで、シリコン窒化膜40をプラズマCVD法で成長
させる。このときの成長膜厚は発光波長1.3μmに対
して無反射(AR)条件になるように1800人程度ヒ
ナる。つぎにホトリソグラフィ技術を用い、このシリコ
ン窒化膜40を選択エツチングしてコンタクト領域50
を作り、この上面にクロム−金(Cr−Au)材から成
るp側オーミック電極60を選択形成する。ついで、裏
面研磨を行ない、ウェハー全体の厚さを100μm程度
とした後、金ゲルマニウム−金ニッケル(A u G 
e −A u N i )材から成るN側オーミックN
 % 70を形成し、更にP側オーミック電極60上に
放熱を良くするための金メツキ層80を5μmの厚さに
形成したものである。
Next, a silicon nitride film 40 is grown by plasma CVD. The thickness of the grown film at this time is about 1,800 thick to provide anti-reflection (AR) conditions for the emission wavelength of 1.3 μm. Next, using photolithography technology, this silicon nitride film 40 is selectively etched to form a contact region 50.
A p-side ohmic electrode 60 made of a chromium-gold (Cr-Au) material is selectively formed on the upper surface of the p-side ohmic electrode 60. Next, the back surface is polished to a thickness of about 100 μm, and then gold germanium-gold nickel (AuG
N-side ohmic N made of e −A u N i ) material
% 70, and a gold plating layer 80 with a thickness of 5 μm is further formed on the P-side ohmic electrode 60 to improve heat dissipation.

本実施例の半導体ウェハーは、半導体基板10とP側オ
ーミック電極60とのコンタクトがコンタクト領域50
のみから成る構造に作られ、その周辺の半導体基板10
とはpn接合領域20よりも深い溝30により分離され
ており、また、P側オーミック電極60には素子分離領
域90が形成されるため、FP型型光光ダイオード素子
ウェハー内で個々に電気的に分離された状態にある。従
って、N側オーミック電極70の全面からN側電極を取
り、また、各発光素子のP側オーミック電極60上の金
メツキ層80にプローブを当てて電流を流せば、光出力
面100から無反射(AR)条件に設定されたシリコン
窒化膜40を通して光が効率良く放出され、更にこの光
出力面100と対面するよう形成された隣接素子端部の
光反射面110で反射されてウェハー面と垂直上方向に
取出される。このため、受光素子をウェハー面と平行に
設置すれば、ウェハー状態で発光ダイオード素子それぞ
れの光出力特性の評価が可能となる。
In the semiconductor wafer of this embodiment, the contact between the semiconductor substrate 10 and the P-side ohmic electrode 60 is in the contact region 50.
The surrounding semiconductor substrate 10 is made to have a structure consisting of only
and are separated by a groove 30 deeper than the pn junction region 20, and an element isolation region 90 is formed in the P-side ohmic electrode 60, so that individual electrical connections are made within the FP type photodiode element wafer. are in a state of separation. Therefore, if the N-side electrode is removed from the entire surface of the N-side ohmic electrode 70 and a probe is applied to the gold plating layer 80 on the P-side ohmic electrode 60 of each light emitting element and a current is applied, the light output surface 100 will be free from reflection. Light is efficiently emitted through the silicon nitride film 40 set to the (AR) condition, and is further reflected by the light reflection surface 110 at the end of the adjacent element formed to face the light output surface 100, perpendicular to the wafer surface. It is taken out upwards. Therefore, if the light receiving element is placed parallel to the wafer surface, it becomes possible to evaluate the light output characteristics of each light emitting diode element in the wafer state.

このように、ウェハー状態で光出力特性が評価された後
、ウェハーは第2図および第3図に示すように、発光面
と平行方向の線c−c’および発光面と垂直方向の線D
−D’に沿ってそれぞれ分離され個別の発光ダイオード
素子となる。
As shown in FIGS. 2 and 3, after the light output characteristics are evaluated in the wafer state, the wafer is moved along a line c-c' parallel to the light emitting surface and a line D perpendicular to the light emitting surface.
-D' to form individual light emitting diode elements.

第4図および第5図、第6図はそれぞれ本発明をDFB
型発光発光ダイオード造に実施した堝りの一実施例を示
す半導体ウェハーの部分斜視図およびそのA−A’ 、
B−B’断面図である。
FIG. 4, FIG. 5, and FIG. 6 each illustrate the present invention using a DFB.
A partial perspective view of a semiconductor wafer showing an example of drilling carried out in the fabrication of a type light emitting diode, and its AA';
It is a BB' cross-sectional view.

本実施例によれば、半導体ウェハー上には両面発光の複
数個のrjFB型発光ダイオード素子が、自分自身の光
出力を垂直反射する光反射面110aと隣接素子の出力
面100からの光出力を垂直反射するる隣接素子のため
の光反射面110bとをそれぞれ備えるように行列配置
されて形成される。
According to this embodiment, on a semiconductor wafer, a plurality of double-sided light emitting RJFB type light emitting diode elements reflect light output from a light reflection surface 110a that vertically reflects its own light output and an output surface 100 of an adjacent element. The light reflecting surfaces 110b for adjacent vertically reflecting elements are arranged in rows and columns.

まず、n型InP基板10上にエピタキシャル成長によ
りpn接合領域20を形成後、選択エツチングにより前
実施例と同様に、電流狭窄およびエピタキシャル成長層
分離のための講30と光出力面100とこの素子自身お
よび隣接素子のための光反射面110aおよび110b
とをpn接合領域20よりもそれぞれ深く形成する。す
なわち、実質的には光出力面100と光反射面110a
、110bとを各素子の両側に形成する。前実施例と同
様にシリコン窒化膜40をプラズマCVD法で成長させ
る。このときの成長厚膜は発振波長1.3μmに対して
無反射(AR)条件となるように1800人程度ヒナる
。つぎに、ホトリソグラフィ技術を用い、このシリコン
窒化膜40を選択エンチングしてコンタクト領域50を
作り、この上面にクロム−金(Cr−Au)材から成る
P側オーミック電極60を選択形成する。
First, after forming a pn junction region 20 by epitaxial growth on an n-type InP substrate 10, selective etching is performed to form a structure 30 for current confinement and epitaxial growth layer separation, a light output surface 100, this element itself, and the like, as in the previous embodiment. Light reflecting surfaces 110a and 110b for adjacent elements
and are formed deeper than the pn junction region 20, respectively. That is, substantially the light output surface 100 and the light reflection surface 110a
, 110b are formed on both sides of each element. As in the previous embodiment, a silicon nitride film 40 is grown by plasma CVD. The thickness of the grown thick film at this time is about 1,800 to provide an anti-reflection (AR) condition for the oscillation wavelength of 1.3 μm. Next, using photolithography technology, this silicon nitride film 40 is selectively etched to form a contact region 50, and a P-side ohmic electrode 60 made of a chromium-gold (Cr--Au) material is selectively formed on the upper surface of the contact region 50.

ついで、裏面研磨を行ない、ウェハー全体の厚さを10
0μm程度とした後、N側オーミック電極70の金ゲル
マニウム−金ニッケル(AuGe−AuNi)から成る
金属膜を形成し、更にP側オーミック電極60上に放熱
を良くするための金メツキ層80を5μmの厚さに形成
したものである。本実施例においても、溝30および素
子分離領域90により各素子はウェハー面内において個
々に電気的に分離されているので、前実施例と同様に各
素子に電流を流す事により、素子の両側に形成した光出
力面100から光がそれぞれ放出され、更にこれらの光
出力面100と対面して形成された光反射面110aお
よび110bでそれぞれ反射されてウェハー垂直方向に
取出される。このため受光素子をウェハー面と平行に設
置することにより、ウェハー状態で発光ダイオード素子
それぞれの光出力特性の評価が可能となる。このように
、ウェハー状態で光出力特性が評価され不良素子にマー
キングが行われた後、ウェハーは第5図および第6図に
示すように、発光面と平行方向のc−c’および発光面
と垂直方向のD−D′に沿ってそれぞれ分離され個々の
発光ダイオード素子となる。この際、光反射面110b
からの光出力はモニタ用として使用される。このDFB
型の発光ダイオードはFP型の素子とは異なり、内部の
共振器により光の増幅をしているため、光反射面の反射
率をシリコン窒化膜40によりゼロに調整してやりさえ
すれば鏡面状悪である必要はないので、本発明の実施は
きわめて容易である。
Next, backside polishing is performed to reduce the total thickness of the wafer to 10
After reducing the thickness to approximately 0 μm, a metal film made of gold germanium-gold nickel (AuGe-AuNi) for the N-side ohmic electrode 70 is formed, and a gold plating layer 80 is further formed to a thickness of 5 μm on the P-side ohmic electrode 60 to improve heat dissipation. It is formed to a thickness of . In this embodiment as well, each element is electrically isolated from each other within the wafer plane by the groove 30 and the element isolation region 90, so that by passing a current through each element as in the previous embodiment, both sides of the element can be isolated. Light is emitted from the light output surfaces 100 formed in the wafer, and is further reflected by the light reflection surfaces 110a and 110b formed facing the light output surfaces 100, respectively, and is extracted in a direction perpendicular to the wafer. Therefore, by installing the light receiving element parallel to the wafer surface, it becomes possible to evaluate the light output characteristics of each light emitting diode element in the wafer state. In this way, after the light output characteristics have been evaluated in the wafer state and defective devices have been marked, the wafer is placed in the direction c-c' parallel to the light-emitting surface and the light-emitting surface as shown in FIGS. 5 and 6. and are separated along the vertical direction DD' to form individual light emitting diode elements. At this time, the light reflecting surface 110b
The optical output from the is used for monitoring purposes. This DFB
Unlike FP-type elements, FP-type light emitting diodes amplify light using an internal resonator, so as long as the reflectance of the light-reflecting surface is adjusted to zero using a silicon nitride film 40, it can be mirror-like. Since this is not necessary, the present invention is very easy to implement.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、端面発光
素子を製造するに際し、光出力面と光反射面をウェハー
上にそれぞれ素子領域の端部を利用し対向させて形成す
るので、発光素子の光出力特性をウェハー状態で評価す
ることが可能である。従って、個々に分離した状態で評
価を行う従来の製造方法に比べれば生産性を著しく高め
得る他、生産管理に必要なウェハー面内の特性分布評価
データも容易に入手できるので製造技術の改善に顕著な
効果を奏することができる。
As explained in detail above, according to the present invention, when manufacturing an edge light emitting device, the light output surface and the light reflection surface are formed on the wafer so as to face each other using the edges of the device regions, so that light emitting It is possible to evaluate the optical output characteristics of the device in the wafer state. Therefore, productivity can be significantly increased compared to conventional manufacturing methods in which evaluation is performed in separate states, and it is also possible to easily obtain property distribution evaluation data within the wafer surface, which is necessary for production control, which is useful for improving manufacturing technology. It can produce remarkable effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図、第3図はそれぞれ本発明をFP型
型光光ダイオード製造に実施した場合の一実施例を示す
半導体ウェハーの部分斜視図およびそのA−A’ 、B
−B’断面図、第4図および第5図、第6図はそれぞれ
本発明をDFB型発光発光ダイオード造に実施した場合
の一実施例を示す半導体ウェハーの部分斜視図およびそ
のAA’ B−B’断面図である。 10・・・n型InP基板、20・・・pn接合領域、
30・・・電流狭窄およびエピタキシャル層分離のため
の溝、40・・・シリコン窒化膜、5o・・・コンタク
ト領域、60・・・P型オーミック電極、7゜・・・N
型オーミック電極、80・・・金メツキ層、90・・・
素子分離領域、100・・・光出力面、11o。 Oa。 b・・・光反射面。 笛 図 宋 霞 V茶子分雌傾戊 男 マ 図 図
FIG. 1, FIG. 2, and FIG. 3 are partial perspective views of a semiconductor wafer showing an embodiment of the present invention in the production of FP type photodiodes, and AA' and B thereof, respectively.
-B' sectional view, FIG. 4, FIG. 5, and FIG. 6 are a partial perspective view of a semiconductor wafer and its AA' B- It is a B' sectional view. 10... n-type InP substrate, 20... pn junction region,
30... Groove for current confinement and epitaxial layer separation, 40... Silicon nitride film, 5o... Contact region, 60... P-type ohmic electrode, 7°... N
Type ohmic electrode, 80... Gold plating layer, 90...
Element isolation region, 100...light output surface, 11o. Oa. b...Light reflecting surface. Flute diagram Song Xia V tea subordinate female leaning male Ma diagram

Claims (1)

【特許請求の範囲】[Claims] 一つの半導体基板上に複数個の端面発光型光半導体素子
を電気的に互いに分離して行列配置する素子形成工程と
、前記端面発光型半導体素子の光出力に対する基板上方
への光反射面を光出力面に対向させてそれぞれの隣接素
子の端部に形成する光反射面の形成工程とを含む半導体
ウェハーの製造工程を備えることを特徴とする端面発光
型光半導体装置の製造方法。
An element forming step in which a plurality of edge-emitting optical semiconductor elements are electrically separated from each other and arranged in rows and columns on one semiconductor substrate; 1. A method for manufacturing an edge-emitting optical semiconductor device, comprising a semiconductor wafer manufacturing process including a step of forming a light reflecting surface at an end of each adjacent element so as to face an output surface.
JP63188720A 1988-07-27 1988-07-27 Manufacture of end-face light-emitting type optical semiconductor device Pending JPH0237783A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63188720A JPH0237783A (en) 1988-07-27 1988-07-27 Manufacture of end-face light-emitting type optical semiconductor device

Applications Claiming Priority (1)

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JP63188720A JPH0237783A (en) 1988-07-27 1988-07-27 Manufacture of end-face light-emitting type optical semiconductor device

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JPH0237783A true JPH0237783A (en) 1990-02-07

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07131066A (en) * 1993-10-30 1995-05-19 Nec Corp Light emitting diode
US5632738A (en) * 1991-09-12 1997-05-27 Kewpie Kabushiki Kaisha Plastic blow container for medical fluids
US6583510B2 (en) * 2001-02-19 2003-06-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with varying thickness gold electrode
CN102507931A (en) * 2011-11-16 2012-06-20 厦门出入境检验检疫局检验检疫技术中心 Colloidal gold immunochromatographic assay test strip for pyrethroid pesticides and preparation and use methods

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5632738A (en) * 1991-09-12 1997-05-27 Kewpie Kabushiki Kaisha Plastic blow container for medical fluids
JPH07131066A (en) * 1993-10-30 1995-05-19 Nec Corp Light emitting diode
US6583510B2 (en) * 2001-02-19 2003-06-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with varying thickness gold electrode
CN102507931A (en) * 2011-11-16 2012-06-20 厦门出入境检验检疫局检验检疫技术中心 Colloidal gold immunochromatographic assay test strip for pyrethroid pesticides and preparation and use methods

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