JPH0237776A - Semiconductor device - Google Patents

Abstract

PURPOSE:To miniaturize and to integrate highly densely by a method wherein a continuous and identical metal film covering a passive element is formed on the passive element formed inside a chip, an insulating film is formed on the metal film, which is held at a definite potential. CONSTITUTION:The title device is constituted of a passive element 20 formed inside a chip, a continuous and identical metal film 21 covering the element and an insulating film 22 formed on the metal film 21; the metal film 21 is held at a definite potential. Accordingly, even when the surface of the chip is charged up to be positive under high-temperature and high-humidity surroundings, an effect of its charge is shielded electrically by the metal film 21 covering the whole element; a depletion layer is not formed in a P-type resistor of the element 20; a conductance is not lowered. In a addition, since the metal film 21 is constituted so as to nearly cover the whole chip, a patterning operation may be uniform and can be executed easily. Thereby, an element can be miniaturized and integrated highly dense.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor device that has a package structure in which positive charges are charged up on the chip surface and uses a P-type element inside the chip, which can be manufactured with a small number of steps, and which can be manufactured with a small number of steps. With a structure that facilitates miniaturization and high integration density, the purpose of this is to prevent the effects of the charge-up from affecting the elements inside the chip. A continuous identical metal film is provided to cover the metal film, an insulating film is provided on the metal crotch, and the metal film is held at a constant potential.

[Industrial application field]

The present invention relates to a semiconductor device that is a package IIW in which positive charges are charged up on the chip surface and that uses a P-type element inside the chip.

In recent years, in semiconductor integrated circuits, due to the need to miniaturize elements, the parts originally composed of MO8T transistors have been made smaller and smaller. It is being used instead of a resistor having a 1/2 structure. For example, in the case of an inverter, two MOS transistors Q are originally used as shown in FIG. 4(A).
+, Q2, but this MOS transistor Q2 is replaced with a resistor R as shown in FIG.

In this way, with the miniaturization and higher integration density of elements,
There is an increasing need to use resistors that have a simpler structure than MO8t transistors.

[Conventional technology]

FIG. 5 shows a sectional view of an example of a conventional device. In the figure, a semiconductor substrate (N type) 30 has diffusion regions 31 (P") and 32 (P) having different phosphorus concentrations.

33 (P") is formed, of which the diffusion region 32 constitutes a resistor. The aluminum wiring 34 is in contact with the diffusion region 31, the aluminum arrangement 1135 is in contact with the diffusion region 33, and the resistor It constitutes both terminals of 32. Note that 36° and 37 are silicon oxide films,
38.39 is PSG (Phospho S 1li
cate G 1ass> membrane.

FIG. 6 shows a sectional view of another example of the conventional device. In the figure, a silicon oxide film 4 is formed on the surface of a semiconductor substrate (N type) 40.
1 is provided, and layers 42 (P'') and 43 made of polysilicon, for example, having different phosphorus concentrations are provided on the surface thereof.
(P), 44 (P+) are formed, of which 8
43 constitutes a resistor. Aluminum distribution WA45
is in contact with 1l142, and the aluminum wiring 46 is in contact with w144, forming both terminals of the resistor 43. Note that 47 is a silicon oxide film, and 48.49 is a P
It is an SG film.

[Problem to be solved by the invention]

Normally, semiconductor devices are used by housing devices such as those shown in Figures 5 and 6 in a package, but so-called plastic packages in which chips are injected with resin are used because they can be constructed at a lower cost than ceramic packages. Sometimes used.

However, in a reliability test, when the chip was left in a humidified environment F at about 150°C, for example, if it was a plastic package, moisture would get inside, causing the chip surface to become positively charged, as shown in Figure 7. Can be seen.

In this case, if the resistors 32 and 43 are N-type, even if the chip surface is positively charged up, only a slight electron accumulation layer is formed on the resistor surface, and the change in resistance value is small.
Although this is not a particular problem, if the resistors 32 and 43 are of P type as shown in FIGS. A depletion layer 32a (broken line) is formed in this portion by being repelled by the charge, which causes a disadvantage that the conductance is greatly reduced and the characteristics are changed.

Therefore, in order to eliminate the above-mentioned inconvenience, as shown in Fig. 8,
Inside the PSG film 39, aluminum 1150. ... is provided for shielding, and the influence of the positive charge on the chip surface is transmitted to each resistor 3.
2. There is a device that prevents this from happening. However, in this case, a shielding aluminum layer must be provided independently for each resistor, and its shape and position must be determined at the time of manufacturing, which requires a large number of patterning steps. Wiring must be designed to apply the potential to the shielding aluminum layer, resulting in high costs.Furthermore, a shield electrode and wiring for the shield electrode are provided for each element to be protected, which requires miniaturization. Also, there was a problem that it was difficult to achieve high integration density.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can be manufactured with a small number of steps, has a structure that facilitates miniaturization and high integration density, and can prevent the effects of charge-up from reaching elements inside the chip. .

[Means to solve the problem]

FIG. 1 shows a sectional view of the device according to the invention. In the figure, 20 is a passive element provided in the chip, and 21 is the same continuous metal film covering the element 20.

Reference numeral 22 denotes an insulating film, which is provided on the metal lI film 21, and the gold i film 21 is held at a constant potential.

[Function] Even if the chip surface is positively charged in a high temperature and high humidity environment, the effect of the charge is electrically shielded by the metal film 21 that covers the entire element, and a depletion layer is formed in the P-type paper antibody of the element 20. Therefore, there is no reduction in inductance, and the characteristics can be maintained constant. In this case, since the metal 1!121 is configured to cover almost the entire surface of the chip, patterning can be uniform, and patterning is easier than in the conventional case where a metal layer is provided for each resistor. In addition, it is easy to miniaturize the elements and increase the integration density.

〔Example〕

FIG. 2 shows a manufacturing process diagram of an example of the device of the present invention. In the same figure (A), a silicon oxide film 2 is formed on a silicon substrate 1 to a thickness of, for example, 5000 nm, and a polysilicon layer is deposited on the surface thereof to a thickness of, for example, 5000 nm by CVD (vapor phase epitaxy). Then buttering is done on polysilicon! form 13. Next, in the same figure (B),
For example, silicon oxide lI of 400 people is applied to the polysilicon film 3.
4 and then Resist It! Form J5, 40
Boron is I X 10I5c under the energy condition of kev
Ions are implanted at a concentration ratio of m-2 to form regions 6 (P), i regions 7a (P'), and 7b (P+). Region 6 constitutes a resistor. Next, the resist film 5 is removed, and as shown in FIG.
Then, patterning is performed as shown in FIG. 3D to form a contact hole 9.

Subsequently, in the same figure (E), aluminum wiring layers 10a, 10b, and 10c are patterned on the surface. In this case, the aluminum wiring layer 10a.

10b are in contact with the regions 7a and 7b, respectively, and constitute both terminals of the resistor 6. Aluminum layout 5
11m1oc is formed as a ground wire for the aluminum wiring layer, and is also used as a bonding pad portion of the shielding aluminum layer, which will be described later. next,
In the same figure (F), for example, PSG with a film thickness of 1°0 μm
III is grown and patterned to form bonding pad holes 12a and 12b.

Next, in the same figure (G), an aluminum layer 13 is formed on the surface.
Form a and 13b by buttering. Here, the aluminum layer 13a is an aluminum layer for shielding, and is formed to cover all the active elements (MO3t-transistors) and passive elements (resistors), and the aluminum layer 13a is formed as a bonding pad part in the hole 12a. It is in contact with the wiring layer 10c. One of the signal line aluminum l1i13b is in contact with the aluminum wiring 1iQ10a in the hole 12b.

Subsequently, in the same figure (H), PSGIJ 14 is grown to a thickness of, for example, 0.5 μl, and patterning is performed to form a hole 15a for a bonding pad.

15b is formed. Next, in the same figure (1), a ground bonding wire 16a is attached to the aluminum layer 13a.
is bonded and connected to ground, while a signal line bonding wire 16b is bonded to the aluminum layer 13b.

In this way, all the active elements and passive elements are covered with the shielding aluminum layer 13a, and this is grounded via the bonding wire 16a, so that it can be left in a humidified environment at about 150°C during the reliability test. Even if the chip surface is positively charged up, the influence of this charge is electrically shielded by the aluminum 1113a covering the entire chip. Therefore, the P-type resistor 6 has a seventh
A depletion layer as shown in the figure is not formed, and as a result, no change in resistance occurs, which improves the reliability of the product. Also, in this case, aluminum II for shielding! 13a is a pad hole 15b for the signal line bonding wire 16b
Since the configuration covers almost the entire surface of the chip except for the area near the
Patterning can be uniform, and patterning is easier than in the conventional example shown in FIG. 8, and miniaturization and high integration density are easy to achieve.

FIG. 3 shows a sectional view of another embodiment of the device of the present invention. In the figure, the same components as those in FIG. 2 are given the same numbers and their explanations will be omitted. This one is aluminum III 3
a Aluminum layer 1 as shown in Figure 2 (H) to form a shadow.
3b is not formed, and the aluminum W 113a does not contact the ground wire 10C of the aluminum wiring layer.

Here, the ground bonding wire 16a is bonded to the aluminum layer 13a, while the signal line bonding wire P16b is bonded to the aluminum wiring layer 13a.
Bond directly to a. Since the other configurations and effects are the same as those shown in FIG. 2, their explanations will be omitted.

Note that the metal film for shielding is not limited to aluminum as in the above embodiment, but gold jIIl! can electrically shield positive charges on the chip surface. It is sufficient if it is I. Furthermore, the bonding wire 16a is not limited to being at ground level, for example, 5V.
A similar shielding effect can be obtained even at a potential such as that of the bonding wire 16a, and it is sufficient that the bonding wire 16a is held at a constant potential.

〔Effect of the invention〕

As explained above, according to the present invention, even if the chip surface is positively charged, the P-type paper antibody is not affected by it, and its characteristics can be maintained constant. In addition, in this case, the patterning of the metal film may be uniform, and patterning is easier than in the conventional example in which a metal film is provided for each resistor, and furthermore, it is easier to miniaturize and increase the integration density. .

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the device of the present invention, Figure W2 is a manufacturing process diagram of one embodiment of the device of the present invention, Figure 3 is a cross-sectional view of another embodiment of the device of the present invention, and Figure 4 is a circuit diagram of an inverter. , Fig. 5 is a sectional view of an example of a conventional device, Fig. 6 is a sectional view of another example of the conventional bag U, Fig. 7 is a diagram illustrating the influence of positive charges on the chip surface on the inside of the chip, and Fig. 8 The figure is a sectional view of a conventional device provided with an aluminum layer for shielding. In the figure, 1 is a silicon substrate, 6 is a P-type paper antibody, 7a, 7b are P+ regions, 8.11.14 is a PSG film, 10a, 10b, 10c are aluminum wiring layers, 13a
is an aluminum layer for shielding, 13b is an aluminum layer for signal lines, 16a is a bonding wire for grounding, 16b is a bonding wire for signal lines, 2o is a passive element provided in the chip, 21 is a metal film, 22 is an insulation The membrane is shown. ＋, fire

Claims (1)

[Claims] In a semiconductor device in which a chip is sealed with a molding resin, a continuous and identical metal film (21) is provided on a passive element (20) provided in the chip to cover the passive element. A semiconductor device characterized in that the metal film (21) is provided with an insulating film (22) on the metal film (21), and the metal film (21) is held at a constant potential.