JPH0236232U - - Google Patents
Info
- Publication number
- JPH0236232U JPH0236232U JP11587088U JP11587088U JPH0236232U JP H0236232 U JPH0236232 U JP H0236232U JP 11587088 U JP11587088 U JP 11587088U JP 11587088 U JP11587088 U JP 11587088U JP H0236232 U JPH0236232 U JP H0236232U
- Authority
- JP
- Japan
- Prior art keywords
- digital
- clock
- analog
- interface receiver
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11587088U JPH0236232U (enExample) | 1988-09-02 | 1988-09-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11587088U JPH0236232U (enExample) | 1988-09-02 | 1988-09-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0236232U true JPH0236232U (enExample) | 1990-03-08 |
Family
ID=31357906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11587088U Pending JPH0236232U (enExample) | 1988-09-02 | 1988-09-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0236232U (enExample) |
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1988
- 1988-09-02 JP JP11587088U patent/JPH0236232U/ja active Pending