JPH0236007B2 - KONPAIRANIOKERUJUDOHENSUKASANMEMEIREINOSEISEIHOSHIKI - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention includes a source analysis section, an address allocation section, an optimization section, and a code generation section, and allows a processor to convert a given source program into a target program. In the compiler that generates and supplies
Regarding the generation method of induced variable addition instructions in a compiler that implements induced variable addition with LA (load address) instructions when induced variables are used only as indexes and certain conditions are met. It is something.

[Prior art and problems]

FIG. 1 is a block diagram showing an example of the configuration of a compiler, and FIG. 2 is a diagram showing an example of internal representation by the compiler of induced variable addition. In Figure 1, 1
is a source analysis section, 2 is an address allocation section, 3 is an optimization section, 4 is a code generation section, 31 is a structure analysis section, 32
3 shows an intermediate text optimization section, 33 a register allocation section, and 34 a branch optimization section.

The compiler is configured as shown in Figure 1,
A source program is imported from a storage device to generate a desired target program. The source analysis unit 1 imports the source program from the storage device,
Performs sentence interpretation and develops it into intermediate code (text). The address allocation unit 2 allocates addresses within the storage area corresponding to various data appearing within the program. The optimization unit 3 detects the loop structure, grasps the correlation between data flow, definition of each variable, reference location, etc., and modifies the intermediate code (structure analysis unit 31), enabling the processor at the level of the intermediate code. (intermediate text optimization unit 32), allocates actual resources (registers) to the data appearing in the intermediate code (register allocation unit 33), and performs branch optimization (branch optimization). Part 34). The code generator 4 generates object code.

In the loop detected by the compiler (specifically, carried out by the structure analysis unit 31), I=I+α (here, α is data that has a constant value within the loop;
The addition of a variable I that is regression-defined as (usually a constant) is called the addition of induced variables. Although such an addition operation may be explicitly written by a user as an assignment statement, in many cases it is generated as a result of compiler optimization processing. For example, for a source program (FORTRAN) such as DIMENSION A(10), B(10) DO 5 I=1, 10, 1 A(I)=B(I) 5 CONTINUE, the internal representation by the compiler is The result will be something like the one shown in Figure 2. In FIG. 2, is the initial setting of the induced variables, is the addition of the induced variables, and "4" is the addition constant.

Conventional optimizing compilers generate Add instructions (AR, A) for addition of induced variables (I=I+α). One of the Add instructions is an AR instruction that is implemented using registers, which says, given AR R ₁ and R ₂ , add the contents of register R ₁ and the contents of register R ₂ and put it into register R ₁ . It is a command. The other is the A instruction that is realized using registers and memory. If A R ₁ , m, add the contents of register R ₁ and the contents of memory at address m and put it into register R ₁ .
This is the command. The former instruction uses two registers, and in a loop where the number of general-purpose registers is insufficient compared to the number of data,
The amount of data that cannot be allocated to registers increases accordingly. Furthermore, although the latter instruction only requires one register, it requires memory access, which causes the problem that the processing is slower than the former.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
Realizes the instruction to add induced variables with one register,
The purpose of this invention is to provide a method for generating induced variable addition instructions in a compiler that makes effective use of general-purpose registers and improves the performance of executed programs.

[Structure of the invention]

To this end, the method for generating induced variable addition instructions in the compiler of the present invention consists of a source analysis unit 1 that interprets statements in a source program and develops them into intermediate code; an allocation unit 2, a structure analysis unit 31 that detects loop structures in a program and changes intermediate code, an intermediate text optimization unit 32 that performs optimization to effectively utilize the processor at the level of intermediate code, and an intermediate The optimization unit 3 includes a register allocation unit 33 that allocates actual registers to data appearing in the code, and a branch optimization unit 34 that performs branch optimization, and a code generation unit 4 that generates object code. , The register allocation unit 33 performs processing to collect in-loop information such as the definition reference relationship and usage frequency of data in the loop in the intermediate text after optimization, and allocates registers to local calculation parts in the loop. Performs local register allocation processing where the data is used globally, performs global register allocation processing where registers are allocated to data used globally within the loop, and displays the results of local register allocation and global register allocation on the intermediate text. It is configured to update the intermediate text where it is reflected, check whether there is an unprocessed loop, return to if it exists, and perform register allocation end processing if not. There is.

In this method of generating a guided variable addition instruction in a compiler, the intermediate text optimization unit 32 generates one table element consisting of a load address instruction flag, a guided variable name, an initial value of the guided variable, and an addition constant value of the guided variable. The global register allocation process of the register allocation unit 33 is configured to create a guided variable table having one or more induced variable tables for each loop of the intermediate text after optimization. Count the total number N of variables including induced variables, constants including addition constants to induced variables, and base variables among fixed-point data appearing in one loop in the text, and if the total number N is larger than a predetermined value, is set to load address instruction generation mode, and when set to load address instruction generation mode, whether or not the initial value of the induced variable in the loop is negative;
Checks whether the value of the addition constant is within a predetermined range, whether the induced variable is used only as an index except for its addition, and whether the initial value of the induced variable is non-negative and the addition constant of the induced variable. For induced variables whose numerical values are within a predetermined range and are used only as an index except for addition of induced variables, turn on the corresponding load address instruction flag in the induced variable table corresponding to the loop. The intermediate text update process of the register allocation unit 33 refers to the induced variable table when an intermediate text with an addition code in the RP format is detected, and updates the first operand of the intermediate text with the addition code in the RP format. If it is an induced variable and the load address instruction flag of the induced variable table corresponding to the induced variable is on, the code RR format addition code of the intermediate text will be changed to a code indicating a load address instruction. It is configured.

It is characterized by this.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

Fig. 3 is a diagram showing the LA instruction expression used in the present invention, Fig. 4 is a diagram showing the loop and induced variables, and Fig. 5 is a diagram showing the LA instruction expression used in the present invention.
FIG. 6 is a diagram showing the induced variable table, FIG. 6 is a diagram showing the flow of processing by the register allocation section, and FIG. 7 is a diagram for explaining code change of the induced variable addition text. In the figure, 5 indicates an induced variable table, and 6 indicates intermediate text.

If the induced variable is used only as an index (which is the case in most cases) and certain conditions are met, the LM (load address) instruction can be used as an addition instruction. In consideration of the fact that conventionally generated AR and A instructions require two registers and access to memory when adding integer type induced variables, the present invention reduces the number of registers used to one. It only requires 2 registers, and the execution speed is faster than 2 registers.
Addition is achieved using the LA instruction, which is almost equivalent to the AR instruction. For this purpose, the following conditions are set as the LA instruction generation conditions.

For one loop, the number of data to be allocated to registers (fixed-point data...this also applies to induced variables) is greater than the number of usable general-purpose registers (usually about 10). (This judgment is made as part of the initial processing of register allocation.) The initial value of the induced variable is not a negative value. Initialization of the induction variables is done outside the loop.
For example, 1 shown in FIG. 2 is the initial setting, and the initial value is 4 in this case.

The addition constant value of the induced variable takes a value within a certain range. (Typically, the LA instruction representation contains bits 20 to 31.
Since the addition constant value is given using up to 12 bits, it takes a value within the range of 0 to 4095. ) For example, the second
In the addition of two induced variables shown in the figure, the addition constant value of the induced variables is four.

The induced variable is used only as an index of array elements within the loop, except for its addition.

When all of the above conditions are met, for example, the induced variable addition text as shown in FIG. 2, register allocation to the addition constant 4 of I=I+4 is not performed. On the other hand, a register is allocated to I.

As a result, an LA instruction LA γ,4(γ,0) is generated. Figure 3 shows the LA command expression. In the LA instruction shown in FIG. 3, the second operand address determined from X ₂ , B ₂ , and D ₂ is loaded into bits 8 to 31 of the first operand. Bits 0 to 7 of the first operand
is set to zero.

A detailed explanation will be given below with reference to FIGS. 4 to 7.

FIG. 4 shows the state after the induction variables are generated in one loop as the internal representation after optimization of the intermediate text. In Figure 4, I ₁ to
In is the induced variable, α ₁ to αn are the initial values of the induced variable,
β ₁ to βn represent addition constant values of induction variables, and Ak (Ij) represents a reference to an array element using an index as an induction variable. There are n or more such array elements in the loop. Also, n is the number of induced variables in the loop,
Ak is the array name (k>1), Ij is the induction variable (1j
n).

In the intermediate text optimization section, a guided variable table shown in FIG. 5 is created in the process of generating guided variables. In Fig. 5, I, α, β are the fourth
Corresponding to what is shown in the figure, LA is flag information indicating that addition of each induced variable can be realized by the LA instruction, and is cleared to zero when creating the induced variable table.

Next, the flow of processing by the register allocation section is explained in the sixth section.
This will be explained with reference to the figures. When the induced variable table shown in FIG. 5 is created, control passes to the register allocation control section, which collects in-loop information such as data definitions, reference relationships, and frequency of use within the loop. Perform the following processing.

Allocate a register to a local operation part within the loop (local register allocation) and perform the following processing.

Allocate registers for data that is used globally within the loop (global register allocation). Perform the following processing.

Reflect the results of local register allocation and global register allocation on the intermediate text (updating the intermediate text). Perform the following processing.

Check whether a loop exists.

If it exists, the process returns to step 2, and if it does not exist, it performs the termination process and generates an LA instruction.

In global register allocation processing, selection of global allocation candidate data,
and examine the induction variables. When selecting candidate data for global allocation, count the number of variables, constants, and base constants among the fixed-point data that appears in one loop. (The total number is N. Variables include induced variables, and constants include addition constants for induced variables.) ○B Total N is the total number of general-purpose registers (for example, Fujitsu's M series has 16 general-purpose registers. However, in reality, there is a fixed number of registers used, so the value is somewhat smaller.For the M series compiler mentioned above, 10 to 12 is appropriate)
If it exceeds that, the LA generation mode is set and the induction variables are carefully examined. Otherwise, it assumes that the number of registers is greater than the number of globally allocated data, and enters AR generation mode (conventional method). In examining the induced variables, it is determined whether addition of the induced variables can be realized using the LA instruction as follows.

○C Determination of the initial value of the induced variable: After optimization of the intermediate text, information regarding the induced variable is left as the induced variable table shown in FIG. 5 mentioned above. This induced variable table is sequentially searched to determine whether the initial value (constant value - αk) of the induced variable Ik is a negative value. If it is negative, Ik cannot be converted into LA, but if it is zero or positive, it is determined whether it is an addition constant.

○D Determination of addition constant value: Determine whether the value range of addition constant value βk of Ik is Oβk4095. If it is outside the range, converting Ik to LK is not possible, but if not, the next quotation of the induced variable is checked.

○E Inspection of references to induced variables: Check whether Ik is used only as an index within the loop. If used for something other than an index, Ik's
It cannot be converted into LA, but if it is used only as an index, it appears as a specific operand of intermediate text with predetermined codes (two types). Therefore, by tracing the chain of intermediate text within the loop, it becomes clear whether it is being used for purposes other than indexing.

The above processing of ○C to ○H is sequentially determined as I ₁ , I ₂ , .

Also, in the intermediate text update process, the code of the induced variable addition intermediate text is changed, but this process is performed as one of the intermediate text update processes in the loop when the intermediate text of the addition code is detected. Do it when the time comes. As shown in Figure 7, if operand 1 of an intermediate text with an addition code is an induced variable and the LA flag is on, the code of this intermediate text is '
Change from 'ADD' (addition) to 'LA' (load address). At the same time, R ₁ (register of operand 1) and R ₂ (register of operand 2) contain global register γ assigned to induced variable I ₂ .
Set.

Generation of LA instructions from LA intermediate text is performed in the code generation phase in the same way as general intermediate text.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in global register allocation, in a loop where the number of general-purpose registers is insufficient compared to the number of data, addition of one induced variable is This can be implemented using general-purpose registers. Therefore, data that could not be allocated to registers in the past can be allocated to registers, and the speed of the execution program can be improved.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an example of the configuration of a compiler, Figure 2 is a diagram showing an example of the compiler's internal representation of induced variable addition, Figure 3 is a diagram showing the LA instruction representation used in the present invention, and Figure 4. Figure 5 is a diagram showing the loop and induced variables, Figure 5 is a diagram showing the induced variable table, Figure 6 is a diagram showing the flow of processing by the register allocation section, and Figure 7 is for explaining the code change of the induced variable addition text. This is a diagram. 1... Source analysis section, 2... Address allocation section, 3
...Optimization section, 4...Code generation section, 31...Structure analysis section, 32...Intermediate text optimization section, 33
. . . register allocation section, 34 . . . branch optimization section, 5 . . . induced variable table, 6 . . . intermediate text.

Claims (1)

[Claims] 1. A source analysis unit 1 that interprets the sentences of a source program and develops it into intermediate code; An address allocation unit 2 that allocates addresses in a storage area to various data appearing in the program; and a loop in the program. A structure analysis unit 31 detects the structure and changes the intermediate code; an intermediate text optimization unit 32 performs optimization to effectively utilize the processor at the intermediate code level; an optimization unit 3 having a register allocation unit 33 that allocates a register allocation unit and a branch optimization unit 34 that performs branch optimization; and a code generation unit 4 that generates an object code; This process collects information within the loop such as definition reference relationships and frequency of use of data within the loop in the intermediate text after conversion, and performs local register allocation processing where registers are allocated to local calculation parts within the loop. , Performs global register allocation processing where registers are allocated to data used globally within the loop, and updates intermediate text where the results of local register allocation and global register allocation are reflected on the intermediate text. Generates an induced variable addition instruction in the compiler. In the method, the intermediate text optimization unit 32 creates a guided variable table having one or more table elements each including a load address instruction flag, a guided variable name, an initial value of the guided variable, and an addition constant value of the guided variable. The global register allocation process of the register allocation unit 33 is configured to perform processing to create a global register for each loop in the intermediate text after optimization. The total number N of variables including induced variables, constants including addition constants for induced variables, and base variables among the fixed-point data to be generated is counted, and if the total N is larger than a predetermined value, the mode is set to load address instruction generation mode. , if the load address instruction generation mode is selected, whether or not the initial value of the induced variable in the loop is negative;
Checks whether the value of the addition constant is within a predetermined range, whether the induced variable is used only as an index except for its addition, and whether the initial value of the induced variable is non-negative and the addition constant of the induced variable. For induced variables whose numerical values are within a predetermined range and are used only as an index except for addition of induced variables, turn on the corresponding load address instruction flag in the induced variable table corresponding to the loop. The intermediate text update process of the register allocation unit 33 refers to the induced variable table when an intermediate text with a PR format addition code is detected, and updates the first operand of the intermediate text with the PR format addition code. If it is an induced variable and the load address instruction flag of the induced variable table corresponding to the induced variable is on, the code of the intermediate text is loaded from the PR format addition code.
A method for generating an induced variable addition instruction in a compiler, characterized in that the compiler is configured to change the code to a code indicating an address instruction.