JPH0235686A - Reference voltage generation circuit - Google Patents

Abstract

PURPOSE:To obtain a constant reference voltage in spite of the fluctuation of a source voltage VDD by connecting a P-channel transistor in series to an N-channel transistor, and obtaining the reference voltage from the connecting point of serial connection. CONSTITUTION:The title circuit is provided with a diode D2 provided between a prescribed terminal 5 and prescribed potential Vss, and a P-channel MIS type transistor M1 connected between the prescribed terminal 5 and the power source VDD. When a power source level is set within a level not to operate the diode D2, a voltage Vref outputted from the prescribed terminal 5 is controlled by the P-channel MIS type transistor M1. Also, when the power source level is set within the level to operate the diode D2, the voltage Vref decided by relation between the P-channel MIS type transistor M1 and the diode D2 is outputted to the prescribed terminal 5. In such a way, it is possible to always obtain a stable reference voltage even when the fluctuation is generated in the source voltage VDD.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to, for example, an internal step-down circuit of a RAM. A reference voltage is obtained by providing a P-channel MIS type transistor connected between a predetermined terminal and a power source, and outputting a voltage determined by the relationship between the P-channel MIS type transistor and the diode to the predetermined terminal. By doing so, a constant reference voltage is guaranteed regardless of fluctuations in the power supply voltage, and a stable constant voltage can be obtained.

[Conventional technology]

Static RAM design rules have been miniaturized as memory capacity has increased, and in recent years, memory patterns have been constructed using design rules of, for example, 0.5 μm. If the static R,'kM is constructed using such a finer design rule, the gate oxide film becomes thinner, making it difficult to obtain a sufficient withstand voltage. Therefore, it is possible to improve reliability by setting the power supply voltage low.

Incidentally, the external power supply voltage is normally set to 5 µm, and various devices are designed to operate with a power supply voltage of 5 µm. Therefore, in order to operate static RAM at such a low voltage,
An internal step-down circuit is required to generate a voltage lower than the power supply voltage.

Such an internal step-down circuit can be constructed as shown in FIG.

That is, in FIG. 5, 51 is a reference voltage generation circuit;
52 is an internal voltage control circuit. A reference voltage generation circuit 51 is provided between the power supply terminal 53 and the ground terminal 55. A power supply voltage van (5■) is supplied to the power supply terminal 53, and this power supply voltage VDfl is supplied to the reference voltage generation circuit 51. A reference voltage generation circuit 51 generates reference voltages ① and 1 from the power supply voltage VDD supplied to the power supply terminal 53.

These reference voltages Vr, f are supplied to the internal voltage control circuit 52.

The internal voltage control circuit 52 controls this reference voltage ■1. ．． The power supply voltage VIIO is controlled based on this, and an internal drop voltage VINT (for example, 3V to 4V) is formed. This internal voltage drop Vl
st is output from the output terminal 54. The static RAM is driven by this internally dropped voltage VIN.

In this way, the reference voltage generation circuit 51 generates the power supply voltage ■. .

From this, a reference voltage V ref is formed as a reference for forming the internal drop voltage VIN. Such a reference voltage generation circuit has conventionally been configured as shown in FIG.

In FIG. 6, M51, M52, and M2S are N-channel MOS transistors. The wells and sources of each N-channel MO3) transistor M51, M52, M2S are connected to each other, and each N-channel MO3)
3) The gates and drains of transistors M51, M52, and M2S are connected to each other. Between the power supply terminal 61 and the ground terminal 62, a series connection of N-channel MO3) transistors M5LM52 and M2S whose wells and sources and gates and drains are connected to each other is connected. N-channel MOS transistors M51 and N
Channel MO3) An output terminal 63 of the reference voltage V rat is derived from the connection point with the transistor M52.

These N-channel MO3) transistors M51, M52
, M2S are operated in the linear region. In such a linear region, N-channel MOS transistors M51, M52,
By resistor division by M2S, reference voltages 2, . . . r are obtained from the output terminal 63.

[Problem to be solved by the invention]

However, in this way, the N-channel MOS transistor M
51, M52, and M2S are connected in series, and this N-channel M
Using the linear parts of OS transistors M51, M52 and M2S, reference voltage v4. ．． ■ If you want to form the power supply voltage. When a fluctuation occurs, the reference voltage V rat obtained from the output terminal 63 fluctuates accordingly, and a stable reference voltage V rat cannot be obtained.

Therefore, it is an object of the present invention to provide a reference voltage generation circuit that can always obtain a stable reference voltage even if the power supply voltage VDD fluctuates.

[Means to solve the problem]

This invention has a diode D2 provided between a predetermined terminal 5 and a predetermined potential VSS, and a P-channel MIS type transistor M1 connected between the predetermined terminal 5 and a power supply ■I, o, and the power supply level is Controls the voltage Vrar output from the predetermined terminal 5 by the P-channel MIS transistor M1 when the level is such that the diode D2 is not operated;
A reference voltage generation circuit characterized in that when the power supply level is at a level that operates the diode D2, a voltage V rer determined by the relationship between the P-channel MrS type transistor M1 and the diode D2 is output to a predetermined terminal 5. be.

[Effect]

P channel MOS) transistor M1 and N channel MO
S) Connect in series with transistor M2 to create N-channel MO3
A diode D2 is formed by the junction between the well and the source of the I-transistor M2, and a reference voltage V r@f is obtained from the connection point of the series connection of the P-channel MOS transistor M1 and the N-channel MOS transistor M2. Now, the power supply voltage ■,. Suppose that the value is gradually raised from OV. When the power supply voltage van is very low, the P channel MOS transistor M1 is in a conductive state. Power supply voltage V. As the voltage increases, the resistance of the P-channel MOS transistor M1 increases and the resistance of the diode D2 decreases. Therefore, the reference voltage V raz output from the output terminal 5 increases according to the characteristics of the P-channel MOS transistor M1 and the diode D2. Eventually, the diode D2 becomes conductive, and the reference voltage V rafl output from the output terminal 5 becomes constant at the threshold voltage ■F. For this reason, the power supply voltage ■.

A constant base*i pressure V rafl can be obtained regardless of variations in .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the basic configuration of this invention. 1st
As shown in the figure, a P-channel MO9 with its well and source connected to each other is placed between power supply terminal 1 and ground terminal 2.
A series connection is provided between an I-transistor Ml and an N-channel MO3 I-transistor M2 whose well and drain are connected to each other.

Note that a terminal 3 is connected to the gate of the P-channel MOS transistor M1 and the gate of the N-channel MOS transistor M2.
and 4, respectively, and the power supply voltage V0
P-channel MOS transistor M1 is set to be conductive when the current is low.

Then, a reference voltage V
,. , 1 is derived from the output terminal 5.

In N-channel MO3I-transistor M2, its P
A diode is formed between the type well and its N type source diffusion region. Therefore, the configuration shown in FIG.
As shown in the figure, this is equivalent to connecting a diode D2 in series in the forward direction to a P-channel MOS transistor M1. Hereinafter, the diode formed between the well of N-channel MOS transistor M2 and its source expanded region h6i will be referred to as diode D2. The threshold voltage (1) of this diode D2 is determined by the junction characteristics between the well and the source diffusion region. This threshold voltage is
For example, it is 1.4■.

Now, assume that the power supply voltage van is gradually raised from OV. When the power supply voltage VDD is very low, the P-channel MO
3I--Transistor M1 is conducting.

it source voltage ■I,. As the value increases, along with this,
P channel N03) The resistance of transistor M1 increases and the resistance of diode D2 decreases.

Therefore, the reference voltages output from output terminal 5 ■, □
increases in accordance with the characteristics of the P-channel MOS transistor M1 and the diode D2. Eventually, the diode D2 becomes conductive, and the reference voltages ■, 1□ output from the output terminal 5 become approximately constant at the threshold voltage ■r of the diode D2. Therefore, the power supply voltage VII
A constant reference voltage V rllfl can be obtained regardless of variations in D.

Here, the threshold voltage VF of the diode D2 is determined by the junction characteristics between the well and the source diffusion region in the N-channel MOS transistor M2, as described above. Therefore, by connecting the diodes D2 in multiple stages, it is possible to obtain a constant reference voltage Vrafl at a desired voltage.

FIG. 3 shows an embodiment of the present invention. In this embodiment, based on the above-mentioned operating principle, the power supply voltage D
The reference voltage V r@f is formed from 0. That is, in FIG. 3, P-channel MO3I transistor Mll corresponds to P-channel MOS transistor M1 in FIG.

N-channel MOS transistors M12 to M14 correspond to N-channel MOS transistor M2 in FIG. N-channel MOS transistors M12 to M14
is operated as a diode formed by the junction of the well and the source diffusion region. That is, the embodiment shown in FIG. 3 has a configuration equivalent to that of the three-stage connection of diodes D2 in the principle diagrams shown in FIGS. 1 and 2.

That is, in FIG. 3, the well of P-channel MOS transistor Mll and its source are connected to each other.

In each of the N-channel MOS transistors M12 to M14, the well and the drain thereof are connected to each other. Between the power supply terminal 11 and the ground terminal 12, there is a P whose well and its source are connected to each other in this way.
A channel MOS transistor Mll and an N-channel MOS whose drain is connected to its well.
) A series connection of run disks M12 to M14 is connected.

P channel MO3) transistor M11 and N channel MO
S) Output terminal 13 of reference voltage r1 is derived from the connection point of transistor M12.

Further, in each of the N-channel MOS transistors M15 to M18, the well and the source thereof are connected to each other. At the same time, the gate and drain of each of N-channel MOS transistors M15 to M18 are connected to each other. Connected between power supply terminal 11 and ground terminal 12 is a series connection of N-channel MOS transistors M15 to M18 whose wells and sources and whose gates and drains are connected to each other in this manner.

N-channel MO3I - transistor M16 and N-channel M
OS) Connection point A with transistor M17 is P channel MO
3) Connected to the gate of transistor Mll. Also, N
channel MOS) transistor MI7 and N channel MOS
Connection point B with transistor M1B is N-channel MOS)
Connected to the gates of transistors M12 to M14.

In this embodiment, the power supply voltage ■ supplied to the power supply terminal II. . When the change characteristics of the reference voltages (■, □) outputted from the output terminal 13 with respect to changes in are determined, the characteristics as shown in FIG. 4 are obtained. That is, in this example, P
A channel MO3) transistor Mll and three N-channel MOS) transistors M12 to MI4 are connected in series. This N-channel MOS) transistors M12 to M1
A diode is formed by the junction of each well of 4 and the source diffusion region. Therefore, the supply voltage■. ,
When V0 gradually rises, the reference voltage V0 gradually rises, and assuming that the threshold voltage of this diode is 2, the reference voltage Vraf becomes constant at approximately 3Vr. In other words, the threshold voltage is set to 1.4, for example.
In this case, the reference voltage V raf is approximately constant at 4.2V.

Note that when a MOS transistor is operated in a linear region in this way, temperature characteristics often become a problem. Therefore, in Fig. 4, in order to investigate the change in characteristics due to temperature conditions, the power supply voltage V
. The change in the reference voltage V rat with respect to the change in D is calculated. In FIG. 4, T1 is the characteristic at 25 degrees, T2 is the characteristic at 125 degrees, and T3 is the characteristic at 110 degrees. From the characteristics shown in FIG. 4, it is confirmed that the characteristics do not change significantly even if the temperature conditions change.

〔Effect of the invention〕

According to this invention, the P-channel MOS transistor Ml
and an N-channel MOS transistor M2 are connected in series, a diode D2 is formed by the junction between the well of the N-channel MOS transistor M2 and the source, and a diode D2 is formed by connecting the well and the source of the N-channel MOS transistor M2.
By obtaining the reference voltage □ from the connection point of the series connection between the OS transistor M1 and the N-channel MOS transistor M2, a constant reference voltage can be obtained regardless of fluctuations in the power supply voltage VIIO.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing the basic configuration of this invention, and FIG. 2 is a connection diagram used to explain the basic configuration of this invention. Fig. 3 is a connection diagram of an embodiment of this invention, Fig. 4 is a graph used to explain an embodiment of this invention, Fig. 5 is a block diagram of an internal step-down circuit, and Fig. 6 is a conventional reference voltage generator. It is a connection diagram of a circuit. Explanation of main symbols in the drawings Ml, Mll: P-channel MOS transistor. M2. M12 to M18: N-channel MOS) transistors. 1.11: Power supply terminal, 2, 12: Ground terminal 5, ll reference voltage output terminal. Agent Patent Attorney Tadashi Sugiura Tomo 1 Hon A' I] Figure 1: Motofu SAG's Tomiki Ko 10 Figure 2: Figure 3

Claims (1)

[Claims] A diode provided between a predetermined terminal and a predetermined potential, and a P-channel MI connected between the predetermined terminal and a power source.
and an S-type transistor, when the power supply level is at a level that does not operate the diode, the P-channel MIS transistor controls the voltage output from the predetermined terminal, and the power supply level is at a level that operates the diode. A reference voltage generating circuit characterized in that, at certain times, a voltage determined by the relationship between the P-channel MIS type transistor and the diode is outputted to the predetermined terminal.