JPH0235554B2 - DENRYOKUHENKANSOCHINOSEIGYOSOCHI - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a power conversion device, and particularly to a fifth
The present invention relates to a power conversion device that reduces the next or seventh harmonic.

[Background of the invention]

Conventionally, power converters that obtain DC voltage from AC power sources using thyristors, etc. generally have the disadvantage of poor power factor, but in recent years, control elements using current interrupting functions such as transistors, gates, turn-offs, and thyristors (GTO) have been developed. (Hereinafter, including transistors)
A power conversion device that can improve the power factor using a GTO (referred to as GTO) has been proposed.

One method is the circuit configuration shown in FIG. In Figure 1, E _U to E _W are AC power supplies, l _S and r _S are inductance and resistance on the power supply side, and G ₁ to G ₆ are
GTO, D ₁ to _{D 6} are reverse voltage blocking diodes (GTO
(Can be omitted if the device itself has reverse voltage blocking ability), L and R _L are the inductance and resistance on the load side,
1 is a comparator that determines the deviation between the current command _IC and the DC feedback current _INF , and 2 is a gate signal generator that provides a gate signal to each GTO from the deviation input and power supply voltage information _fS .

With this circuit configuration, for example, when the U-phase voltage _EU is as shown in Figure 2, a gate pulse is always applied to GTO _G5 in Figure 1 to keep _G5 conductive, and GTO
G ₁ and G ₂ open and close; if G ₁ conducts, E _U − L _S −
The power supply voltage is supplied to the load (L-R _L ) by the electric path _{r S} −G _{1 −D 1} −L−R L −D ₅ −G ₅ −r _S −L _{S −EV} , and G ₁ If G ₂ is cut off and conductive, a circulating current flows in the electrical path L-R _L -D ₅ -G ₅ -G ₂ -D ₂ -L due to the inductance L of the load, and no power supply current flows. This kind of operation is performed with a pulse period T _C and a power supply period λT _C
(λ is the conductivity) is controlled repeatedly at equal intervals, 1
The corresponding power supply current _IS is as shown in FIG.

In the device configured as described above, the output voltage of the power conversion device can be controlled by adjusting the power supply period _λTC , that is, the conduction rate λ, and the power supply voltage
By matching the fundamental wave component of the power supply current _IS with respect to _EU , the fundamental wave power factor is also adjusted to 1, so that a high power factor power converter can be obtained.

However, when the power supply period is given at equal intervals as described above, the power supply current _{I S} becomes a rectangular waveform, so the harmonic current becomes large. The 5th and 7th harmonic components I ₅ and I ₇ of the power supply current vary with the conduction rate λ as shown in Figure 3, but they occur approximately 20% of the fundamental wave component I ₁ . .

It is more difficult to reduce lower harmonics such as the 5th or 7th order with a filter than to reduce higher harmonics. Further, there are problems such as interference with the parallel equipment and generation of electromagnetic noise when an electric motor is connected as a load, which is undesirable.

[Purpose of the invention]

The present invention has been made in view of the above, and an object of the present invention is to provide a control device for a power conversion device that can reduce fifth-order or seventh-order harmonic current components.

[Summary of the invention]

A feature of the present invention is that one GTO on one side of the positive side and the negative side of the GTO connected to all arms and two GTOs on the other side are controlled according to the magnitude of the output voltage to control the power supply current. This makes it more similar to a sine wave.

[Embodiments of the invention]

Hereinafter, the present invention will be explained according to examples.

A fourth
Apply the gate signal shown in the figure to G ₁ to G ₆ (the black part is
(indicates the GTO conduction period). In addition,
For pulse synchronization, when the power supply frequency _S and the number of divisions per half cycle of the power supply are N, T _C = 1/(2・_S・N)
It is the time expressed as .

The shaded part of the power supply voltage waveform is the DC output voltage waveform,
The output voltage generation period λT _C is at the center of the pulse period T _C
is located.

At this time, if a gate signal is applied to each GTO to turn it on or off as shown in the figure, the power supply current I _S for each phase during the period when the W-phase voltage is positive becomes an unequal pulse as shown in the figure. , is controlled to be closer to a sine wave. Note that the flow periods T ₁ , T ₂ , and T ₃ have the following relationship.

Here, λ is the conduction rate and α is the sharing rate, which will be explained below.

The operation shown in FIG. 4 will be explained in more detail using FIG. 5.

Figure 5 shows the pulse period T _C1 ~ shown in Figure 4.
It shows the power supply current of only the DC output voltage W phase during the period T _C3 . Pulse period as shown in figure
There is a period λT _C in which the output voltage is generated in the center of T _C , and a shared period αT _C before and after the terminal parts of T _C1 and T _C3 .
There is.

From the relationship of gate pulse application described in Fig. 4,
The output voltage and W-phase power supply current during the period t ₀ to t ₁₂ shown in FIG. 5 will be explained as follows.

During the period from t ₀ to t ₁ , G ₂ and G ₅ are in a conductive state, causing free circulation, and both the output voltage and power supply current are zero.

During the period from _t1 to _t1 , _G2 and _G4 are in a conductive state, the output voltage is the V-U line voltage, and the W-phase power supply current is zero.

During the period from _t2 to _t3 , _G3 and _G4 are in a conductive state, the output voltage is the W-U line voltage, and the W-phase power supply current flows.

During the period from t ₃ to t ₄ to _{t 5} , G ₁ and G ₄ are in a conductive state, causing free circulation, and both the output voltage and power supply current are zero.

During the period from _t5 to _t6 , _G2 and _G4 are in a conductive state, the output voltage is the V-U line voltage, and the W-phase power supply current is zero.

During the period from _t6 to _t7 , _G3 and _G4 are in a conductive state, the output voltage is the W-U line voltage, and the W-phase power supply current flows.

During the period from t ₇ to _{t 9} , G ₁ and G ₄ are in a conductive state, causing free circulation, and both the output voltage and power supply current are zero.

During the period from _t9 to _t10 , _G3 and _G4 are in a conductive state, the output voltage is the W-U line voltage, and the W-phase power supply current flows.

During the period from _t10 to _t11 , _G3 and _G5 are in a conductive state, the output voltage is the W-V line voltage, and the W-phase power supply current flows.

During the period from t ₁₁ to _{t 12} , G ₃ and G ₆ are in a conductive state, causing free circulation, and both the output voltage and power supply current are zero.

Furthermore, the relationship between the power supply currents after T _C4 and other phases can be easily understood from the relationship shown in Figure 4.

As mentioned above, during each pulse period T _C , we focus on the period λT _C in which DC output is generated and the power supply current of one phase during this λT _C period, and the phase current can be controlled by setting the sharing period αT _C. The harmonics are reduced by controlling the power supply current conduction periods T ₁ , T ₂ , and T ₃ so as to approximate a sine wave more closely.

At this time, the sharing ratio α is optimally controlled with respect to the magnitude of the output voltage, that is, the magnitude of the conduction ratio λ.(1)
By adjusting the power supply conduction periods T ₁ , T ₂ , and T ₃ according to the relationship shown in the equation, it is possible to prevent generation of specific harmonic components.

According to experiments, in order to reduce the 5th or 7th harmonics, the relationship between α and λ should be set to α _I5 = 0 or α _I7 = 0, as shown by the dotted line in Figure 6. known. Characteristics of α _I5 = 0, when λ is 0, α is
0.5, and when λ is 1.0, the 5th harmonic component can be made zero by using a curve that varies α to about 0.4, and α _I7 = 0
When λ is 0, α is 0.5, and when λ is 1.0, α is the characteristic of
By using a curve that varies the value to about 0.3, it is possible to control the seventh harmonic component to zero.

As another method, although it is not possible to reduce both the 5th and 7th harmonic components to zero, it is possible to significantly reduce both harmonic components.

If we use the m curve shown by the solid line in Figure 6, which is a curve in which α is varied to 0.5 when λ is 0 and α is approximately 0.35 when λ is 1.0, the fifth and seventh harmonics (I ₅ / I ₁ ), (I ₇ /I ₁ ) are as shown in Figure 6,
Although it is not possible to reduce both harmonics to zero, it is known that they can be reduced to about 8%, which is an improvement to 1/3 compared to the conventional method.

In this way, for the magnitude of conductivity λ, the sharing rate α
By optimally varying , specific harmonic components can be reduced.

Next, what kind of circuit specifically implements pulse generation control will be explained with reference to FIG. 7 and subsequent figures. FIG. 7 is a diagram showing the configuration of the gate signal generator 2 in detail. 210 is a λ-α data table in which the conduction rate λ determined by the current deviation is input and the sharing ratio α is output. Here, α is set as shown in FIG. The relationship shown is adopted. The input/output relationship is a read-only memory where the input is connected to the address terminal and the output is connected to the data terminal. By creating a table of the relationship between the conduction rate λ and the distribution rate α in this way, when the conduction rate is determined by the current command, it is possible to immediately divide the conduction rate without calculating it based on the conduction rate. The rate α can be obtained. Therefore, it has good responsiveness, and even if the current command changes, an output containing almost no harmonics can be immediately obtained. 220 is a synchronous power supply
This is a clock and timing pulse generator that receives _S as an input and outputs a clock to counters 230 and 240 and a flag indicating whether it is an _UP count or a _DN count. Counters 230 and 240 input information λ and α in addition to the clock and counting direction, respectively, and generate waveforms such as P _L1 , P _L2 , P _A1 , and P _A2 in FIG. 8. In other words, at time point A ₀ , data 1-λ/2 T _C , 1+λ/2 T _C , αT _C , (1-α) T are stored in four counters (two counters each in 230 and 240). When data corresponding to time _C is set and started, each counter finishes counting at A ₁ , A ₄ , A ₂ , and A ₃ , the output changes from “0” to “1”, and the carrier frequency period changes. The value is held and the same operation is repeated again at time point _A5 . That is, FIG. 8 shows waveforms for two cycles.
P _L1 , P _L2 , P _A1 , created from this λ and α information,
P _A2 is a signal used as a material for creating a gate pulse pattern, and is input to the configurator 250.

250 is a logic circuit that receives four signals P _L1 , P _L2 , P _A1 , and P _A2 as input and creates 11 types of gate pulse patterns A, B, C, . . . , X, Y shown in FIG. If you have these 11 types of gate pulse patterns, all you have to do is operate the selector to give a pattern to the GTO according to a certain rule. FIG. 9 shows an example of how to provide the gate pulse pattern created by this constructor 250. Looking at the patterns, GTO2 repeats the gate pulse pattern delayed by 120 degrees relative to GTO1, GTO3 repeats the gate pulse pattern delayed by 120 degrees relative to GTO2, and GTO5 repeats the gate pulse pattern delayed by 120° relative to GTO2.
It can be seen that in contrast to GTO 4, the gate pulse pattern of GTO 6 is repeated with a delay of 120° relative to GTO 5. As _{shown in FIG .}
Create a gate pulse pattern with input as input, so if λ and α change, A, B, C, ..., X,
The Y signal also changes. Therefore, Fig. 8 shows certain α, λ
This shows an example of a gate pulse pattern for . This gate pulse pattern may be applied to G ₁ to _{G 6} in the order shown in the lower part of FIG. 9, for example. Selection of this gate pulse pattern is performed by selectors 261 to 266 in the distributor 260 shown in FIG. The output of the selector is
Connected to the gates of G ₁ to G ₆ , the input is the configurer 25
Gate pulse patterns A, B, created with 0
C, _{. .} . , The gate pulse patterns are connected in advance to the input terminals of the selectors 261 to 266 in order to facilitate the selection of pulse patterns from the select terminals. Each selector 2
Select terminals _A0 to _A3 of 61 to 266 are connected to select data _D0 to _D7 of an indicator 268, which will be described later.

Next, how the select data D ₀ to _{D 7} are created will be explained. The selection data includes an indicator 268 that creates time elapsed information from the synchronous power source, and each selector 26 at each point in time with this time elapsed information as input.
It is generated by a determiner 267 which stores which input pulse pattern from 1 to 266 is to be applied to the gate of the GTO in association with each other. Let us now describe the indicator 268 that creates time elapsed information from the synchronous power supply. The indicator 268 inputs the synchronous power supply _fS , divides one cycle of the synchronous power supply into 12 pulse cycles _TC , and indicates in which of the 12 pulse cycles the current state is included QA to _{Q. D} and f have the functions shown by _S.
The output waveforms Q _A to Q _D of this indicator are shown in FIG. 13.

Next, the determiner 267 will be explained. The decider is a ROM of several 10 bytes. That is, the 14th
As shown in the figure, the ROM address input is Q _A ~ Q _D ,
There are five data buses f _S , and eight output data buses D ₀ to D ₇ are select terminals of selectors 261 to 266.
Connect to A ₀ ~ _{A 3} . For connection during this period, the procedure shown in FIG. 12b may be followed. The reason why the selection information of the selector was simplified in this way is the data input of data selectors 261 to 266.
The gate pulse pattern connected to the terminals E ₀ to E ₁₄ is not all the same for 261 to 266, but the gate pulse pattern is connected by taking into consideration the repetition every 120 degrees in advance.

Now, the order in which gate pulse patterns are selected will be specifically shown using FIGS. 9 and 12 to 14. In Figure 13, the moment when the synchronous power supply becomes 0 is f _S
=Q _A =Q _B =Q _C =Q _D =0, so in Figure 14
All ROM address inputs are 0, so the output is D ₀
~ _D7 are all 0, so as shown in FIG. 12, _A0 ~ _A3 of selectors 261~266 are all 0.
Since it is an input, selector data input E ₀ ~
The signal of E ₀ among E ₁₄ becomes the output of the selector. That is, the pulse pattern "F" is output from the selector 261, "B" from 262, "Q" from 263, "Y" from 264, "Y" from 265, and "X" from 266. Ru. This shows the state at the beginning of the gate pulse pattern table in FIG. Next, the first half cycle of the power supply is divided into six.
After the pulse period elapses, as shown in FIG. 13, only Q _A becomes 1, and the other states remain the same as before.
Then, the ROM data output is D ₀ ~ D ₃ = 1 (4 digits 2
D ₄ to _{D 7} = 1 (4-digit binary number), i.e. D ₀
= D ₄ = 1, D ₁ = D ₂ = D ₃ = D ₅ = D ₆ = D ₇ = 0, and E ₁ of the input terminal of the selector is selected, and the pulse patterns are "Y" for 261 and "Y" for 262. "C" is output for 263, "A" for 264, "P" for 265, and "D" for 266.
This is consistent with the pulse pattern table for the second pulse period in FIG. Next, the second part divided into six
When the pulse period ends, the indicator output changes to the first
From Figure 1, Q _B = 1, Q _A = Q _C = Q _D = f _S = 0, and
From FIG. 12, D ₀ to D ₃ are 3, that is, D ₀ =D ₁ =1,
D ₂ = D ₃ = 0, D ₄ to D ₇ are 2, that is, D ₅ = 1, D ₄ =
D ₆ =D ₇ =0, and from Figure 12b, selector 2
For selectors 61-263, respective input terminals _E2 are selected, and for selectors 264-266, respective input terminals _E3 are selected. From the figure a, the output of selector 261 is "Y", 262 is "X", 263 is "Y", 264 is "B", 26
5 is "Q" and 266 is "F", which correspond to the pulse pattern table for the third pulse period in FIG.

As explained above, a logic circuit that generates multiple gate pulse patterns that may be used as GTO pulse signals according to the commands λ and α is provided in advance, and the output pattern signal is used at which point and in what pattern. What to give to GTO
Since the information given to the gate circuit is made into a table in the ROM, it is possible to have a simple circuit configuration with only λ and a synchronous power supply. Therefore, we have a table of gate pulse patterns for 1 λ and select this. ROM capacity and processing time are superior compared to methods that control the

2. The pattern determination ROM table is simple because inputs to the selector are pre-sequenced for gate pulse pattern selection.

3. Superior in terms of load factor and reliability compared to a method in which the microcontroller determines the firing order of the GTO and selects the mode pulse every time an interrupt is processed.

There are advantages in such points.

In the above explanation, we talked about the case of power running, but
When it is necessary to perform regeneration, it is sufficient to perform processing to shift the phase by 180° in order to reverse the synchronous power supply.

Furthermore, although a control example has been described here in which the half cycle of the power supply is divided into six, it is also possible to easily reduce the pulsation rate with respect to the load by dividing it into twelve. This change can be handled by increasing the period of the indicator 268 and adding the ROM contents of the determiner 267, and can be realized without changing the component that creates the gate pulse pattern. Note that although the ROM content is doubled, the absolute amount is only 24 bytes at most, so this is not an actual problem. Figure 15 shows the number of pulse divisions from 6 to 12.
These are the experimental results when the temperature was increased to .

〔Effect of the invention〕

As described above, according to the present invention, the power conversion device itself can solve the problem of low-order harmonic currents that are difficult to reduce with external filters, etc., so power supply distortion can be improved and disturbances to parallel devices can be solved. This has the effect of reducing electromagnetic noise, etc. when an electric motor is used as a load.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a power converter to which the present invention is applied, FIGS. 2 and 3 are explanatory diagrams of conventional operation, and FIGS. 4 to 15 are explanatory diagrams of the present invention. 6 to 6 are diagrams explaining the operating principle of the present invention,
FIG. 7 is an embodiment of the gate signal generator, FIGS. 8 and 9 are operation explanatory diagrams, FIG. 10 is an embodiment of the configurator, FIG. 11 is an embodiment of the distributor,
Figures 1 to 15 are explanatory diagrams of the operation. G ₁ ~ G ₆ ...Switching element with current cutoff function,
2... Gate signal generator, 210... λ-α table, 220... Clock & timing pulse generator, 230... λ counter, 240
...Counter for α, 250...Configurator, 260...
…Distributor.

Claims (1)

[Claims] 1. An AC power supply, a full-wave rectifier circuit connected to this AC power supply, and using a switching means having a current cutoff function on all positive and negative arms, for each pulse period obtained by equally dividing the half cycle of the AC power supply. A circuit that controls the period for generating an output voltage, and this output voltage is controlled using one switching means on one side of the positive side and the negative side of the full-wave rectifier circuit, and two switching means on the other side. The table includes a table for converting a current conduction rate, which is a ratio between the period during which the output voltage is generated and the pulse period, to a sharing ratio of energization by the two switching means on the other side; When the conduction rate is 0, the distribution rate is set to 0.5, and when the conduction rate is 1.0, the distribution rate is set between 0.3 and 0.4. A control device for a power conversion device, characterized in that the distribution of energization of the two switching means on the other side can be changed by obtaining a distribution rate corresponding to the conduction rate from the table in accordance with the above table.