JPH0233217A - Programmable logic circuit device - Google Patents

Abstract

PURPOSE:To shut off a current through a bit line not in use by using a signal representing whether or not a sense amplifier relating to an optional bit line is in use so as to connect or disconnect the bit line and the sense amplifier. CONSTITUTION:When a transistor(TR)7 of a control bit 6 relating to a bit line not in use for or not contributing to the logical. calculation among bit lines a-f is turned off, the relevant sense amplifier 8-i outputs an L level signal. Then a MOS TR11 of a sense amplifier 9-i is turned off and a MOS TR 12 is turned on and the bit line (i) is disconnected from the sense amplifier 9-i. Thus, a current to the bit line not in use from the sense amplifier 9-i is shut off.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable logic circuit device that realizes an arbitrary logic circuit. More specifically, the present invention relates to a programmable logic circuit device including a circuit for cutting off power supply to sense amplifiers connected to unused bit lines.

[Prior art] Conventional programmable logic circuit using EPROM (
In FIG. 3, which shows a simplified configuration of the PLD (hereinafter abbreviated as PLO), the PLD has word lines AA, B, B, C, C,
An AND array 1 composed of D, D and bit lines a, b, c, de, and r, and each sense amplifier 2 to which the current of each bit line a to bit line r is input and detects a change in the current. -1 to 2-6, and an OR gate 3 to which the output signals of the sense amplifiers 2-1 to 2-6 are input. Note that an EPROM is installed at the intersection of each word line and each bit line.
For example, the MOS transistor 5 shown in FIG.
The gate of the OS transistor 5 has word lines A, A,
B, B, C, C, D, D are connected.

The drain of MO9I-transistor 5 is grounded. A logic circuit is defined by whether or not data is written to these transistors 4. In a conventional PLD using the transistor 4 as described above, for example, Y=A-
In order to realize the logical operation B-C-D+AD+C, writing is performed only to the transistor 4 indicated by the cross mark in FIG. Then, input H level signals to all word lines A, B, C, and D, and
,C.

When an L level signal is input to all of the transistors D, unwritten transistors 4 become L level, and the output signal of bit line a becomes H level.

Also, when an H level signal is input to at least one of the word lines A, B, C, and D, at least one of the unwritten transistors 4 becomes the ■] level, and the output signal of the bit line a becomes L level. The output potential of each bit line is detected by the sense amplifiers 2-1 to 2-6, and an H or L level signal is output to the OR gate 3.

Problems to be Solved by the Invention C] In the conventional PLD, for example, in the above-mentioned example, the transistor 4 connected to the bit line d to the bit line r
Although no writing is performed, half of the transistors 4 on the bit line are always on, and current flows from the sense amplifier power supply through the source of transistor 4 to the grounded drain of transistor 4. flows.

Therefore, as the number of bit lines provided in the AND array I increases and the number of unused bit lines increases, the amount of current consumed by the unused bit lines increases.
There is a problem in that the influence on the overall current consumption becomes large.

The present invention was made in order to solve the above-mentioned problems, and an object thereof is to provide a programmable logic circuit device that can cut off the current consumed by unused bit lines in a PLD. do.

[Means for Solving the Problems] The present invention provides a programmable logic circuit device in which a plurality of bit lines and word lines are provided with programmable elements, and a logic output is obtained by a sense amplifier connected to the bit lines. a signal generating section provided corresponding to each bit line and outputting a signal indicating whether or not to use the sense amplifier; and a switching means for connecting or disconnecting the bit line and the sense amplifier according to the signal output from the signal generating section. It is characterized by having the following.

[The effect signal generating section outputs a signal indicating whether or not to use the sense amplifier corresponding to a given bit line to the switching means. The switching means connects or disconnects the bit line and the sense amplifier using a signal output from the signal generating section.

[Embodiment] In FIG. 1, which is an embodiment of the present invention, the same components as in FIG. 3 are given the same reference numerals.

A control bit 6 is provided separately from the AND array 1, and the control bit 6 controls each of the sense amplifiers 9-1 to 9-6 to which the current of the bit line a to bit line f is inputted into an operating state or a non-operating state. Sense amplifier 9-1 outputs a signal to set the state
Transistors 7 are provided in one-to-one correspondence with the sense amplifiers 9-6. The signals output from each transistor 7 are output from sense amplifier 8-1 to sense amplifier 8, respectively.
-6 to sense amplifier 9-1 or sense amplifier 9
-6 will be done manually. The output signals of the sense amplifiers 91 to 9-6 are input to the OR gate 3.

Of the sense amplifiers 9-1 to 9-6, for example, the sense amplifier 9-1 is shown in FIG.

The current of bit line a is n-type MOS) transistor 1.
It is input to the source of MOS transistor 11 and output from the drain of MOS transistor 11 to current sensing unit IO. Further, the output signal of the sense amplifier 8-1 is input to the gate of the MOS transistor II and the gate of the P-type MOS transistor 12. The source of the MOS transistor 12 is connected to the power supply Vcc.
The potential of M is input, and the drain of the MOS transistor 12 is M
Connected to the drain of the OS transistor 11. Incidentally, the Ike sense amplifiers 9-2 to 9-6 have the same configuration.

In the PLD of the present invention configured as described above, the transistor 7 of the control bit 6 corresponding to the bit line a=f that is not used or does not contribute to the logical operation is turned off. Therefore, the sense amplifier 8-n in which the transistor 7 of the control bit 6 is in an off state outputs an L level signal. For example, quoting the example described in the conventional example, transistors 7d to 7
By turning off r, the sense amplifier 8-4 or 8
-6 outputs an L level signal. Therefore, the MOS transistor 1 provided in the sense amplifiers 9-4 to 9-6
Since an L level signal is input to the gates of the MOS transistors 1 and 12, the MOS transistors 11 are turned off, the MOS transistors 12 are turned on, and the bit lines d to f are connected to the sense amplifiers 9-4 to 9.
-6 is separated. Therefore, current from sense amplifier 9 to unused bit lines is cut off. When the MOS transistor 12 is turned on, the first stage MOS transistors of the sense section 10 shown in FIG. 2 corresponding to these bit lines are turned on, and the current to the sense section 10 is also cut off.

On the other hand, for the bit line to be used, by turning on transistors 7a to 7c of control bit 6, sense amplifiers 8-1 to 8-3 output H level signals to sense amplifiers 91 to 9-3. As a result, the MOS transistor 11 is turned on, the MOS transistor 12 is turned off, and the bit lines a to C are connected to the sense amplifiers 9-1 to 9-3.

In this way, the sense amplifier for the bit line in the AND array can be connected or disconnected from the bit line depending on whether or not writing is performed to the control bit. Therefore, for bit lines that are not used or do not contribute to logical operations in the AND array, by disconnecting the sense amplifier corresponding to this bit line, it is possible to prevent the pit line from consuming current.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to separate the bit line that does not contribute to logical operations from the sense amplifier corresponding to this bit line, thereby reducing unnecessary current consumption in the bit line. It is possible to prevent this from happening.

[Brief Description of the Drawings] Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a block diagram showing the configuration of the sense amplifier in Figure 1, and Figure 3 is the configuration of a conventional PLD. FIG. 4 is a block diagram showing the structure of the transistor in FIG. 3. l...AND array 3...OR gate, 4...transistor, 6...control bit, 8-1 to 8-6...sense amplifier, 9-1 to 9-6...sense amplifier , 11...Transistor, 12...Transistor.

Claims (1)

[Claims] (1) In a programmable logic circuit device in which a plurality of bit lines and word lines are provided with programmable elements, and a logic output is obtained by a sense amplifier connected to the bit lines, a sense amplifier is provided corresponding to each bit line. A programmable logic comprising: a signal generating section that outputs a signal indicating whether or not to use an amplifier; and a switching means that connects or disconnects a bit line and a sense amplifier according to the signal output from the signal generating section. circuit device.