JPH0232639B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for displaying on the screen of a CRT (cathode ray tube) or other raster scan display device with a circular cycle of scan lines occurring with or without interlaced field scanning. The present invention relates to a type of data display device that displays a certain amount of stored data that is accessed repeatedly as an independent entity.

In data display devices of the above-mentioned type, the stored data is used in a so-called "bit-map" comprising at least one information bit for each pixel, or dot, produced on the screen of the display device by a scanning operation. ). If the information bits for successive dot rows of the display are read out on the same line of the scan cycle in each field, the display is a static display.

Alternatively, with a data display device of the type described above,
The stored data is so-called "character-based"
(character base).
In this alternative, a library of standard character shapes containing patterns of information bits is stored, the data to be displayed as independent entities is in digitally encoded form, and the selected character shape is fixed. used for. Next, during the scanning operation, the information bits of the character shape are read out and a display is created. This display is also a static display if the information bits for successive dot rows occur in the same line of the scan cycle in each field.

The resulting static display is "scrolled" by modifying the readout operation in each two or three fields so that the information bits for the dot rows of the display are read out in progressively different scan lines.
It is known that you can (scroll). Displayed data can be rotated/wrapped by reinserting dot rows that were "lost" at the top of the display at the bottom. However, when scrolling occurs, it is usually better to change the stored data gradually. If the information bits of each dot row are read on the previous scan line rather than the scan line in which they are currently being read, the displayed data will only move one scan line every 2-3 fields. This results in smooth scrolling. Scrolling can be made harder, ie, less smooth, by reading out the information bits of each dot row at display positions several scan lines apart, rather than at display positions on adjacent scan lines. If the data being stored is in character-based form as described above, this hard scrolling can be based on a character line base, where a character line is made up of several immediately following dot lines. The speed at which scrolling (smooth or hard) occurs is determined by the frequency with which the scan line is changed to read out the information bits of the dot rows.

However, currently known scrolling means for providing smooth or hard scrolling in data display devices of the type described above include an offset register that stores an offset number representing the display offset, and an offset register that stores the offset number representing the display offset and reads out the information in the dot row. This requires an adder to add this stored offset number to the number of scan lines used for There is considerable lack of flexibility. The stored offset number is incremented periodically to achieve a scrolling effect.

An object of the present invention is to provide a highly flexible scrolling means that does not require an adder to increment the scan line offset.

To this end, according to the invention, in a data display device of the type mentioned above, scrolling means are provided which allow the displayed data to be shifted progressively (in the vertical direction) on the screen of the display device. , a delay count register capable of storing a delay count number, a logic circuit for periodically modifying the delay count number, and connected to receive the stored count number from the delay count register, and a delay counter connected to receive scan line pulses in a circulating cycle and operative to generate a start signal after receiving a number of these pulses corresponding to said count number; and a delay counter receiving pulses at a line scan frequency. The dot row counter is connected in such a way that it operates to produce one dot row address for each received pulse after applying the start signal to the dot row counter, and these dot row addresses are used to determine the dot row address for the displayed dot row. A dot row counter used for reading information bits is provided.

In applying the scrolling circuit according to the present invention to a data display device in which data stored for display is in the form of a bitmap,
A dot row counter is provided to provide a dot row address in a rotating cycle, one address for each scan line in the rotating cycle of scan lines.

In applying the scrolling circuit according to the present invention to a data display device in which data stored for display is in a character-based form, the dot row counter can be set to , provided to provide dot row addresses in rotating cycles having one address for each scan line in the group of scan lines, and further connected to provide a scrolling circuit to advance one step for each cycle of dot row addresses. a character line counter for providing a character line address of one cycle belonging to each character line to be displayed on each group of scan lines, and a scrolling circuit further connected to receive the character line address and for registering the contents of the memory. operating accordingly, comprising a line map memory for mapping character line addresses to different character line addresses belonging to other character lines, such that these different character line addresses correspond to stored characters whose information bits are to be read for display. It is characterized by being used for selection.

Let the row map memory be random access memory,
It is preferable to modify its contents according to the requirements of the logic circuit.

The start of the delay counter operation in each scan cycle of the display can be controlled by a "field" synchronization pulse.

The invention will be explained in detail with reference to the drawings.

The known scrolling circuit shown in FIG. 1 is for a data display device in which display data is stored in a memory 1 in bitmap form. The stored information bits that make up the display data can be thought of as being stored as a matrix with y bit rows each containing X bits. It is assumed that a matrix of this size stores an amount of data that should be displayed as an independent entity. Display unit 2 is a conventional display with 625 lines interlaced scanning at 25 fields per second.
Assume that it is a CRT. In this case, the display of each field is, for example, 256 scan lines LO or
It can be configured from 255. If each of these scan lines contains 256 pixels or dots, then in memory 1, X=256, y=256.

The line frequency signal fl is applied to the CRT for each line scan.
The field frequency signal ff drives the CRT for each field scan. The dot frequency signal fd drives the pulse generator 3. The pulse generator 3 applies dot pulses to a dot counter 4 having a modulo 256 count. Dot counter 4 periodically generates 256 dot addresses D0-D255. These dot addresses are y=
Used to address X=256 bit positions within each of the 256 bit rows. One dot pulse is applied to the line counter 5 once per cycle of the counter 4 occurring at the line frequency fl. This row counter 5 also has a modulus low of 256 cycles, 256
outputs a periodic count of row addresses R0-R255. Note that the signal ff synchronizes this row counter 5 with the scanning operation of the display device. The device further comprises an adder 6, an offset register 7 and a logic circuit 8.

Assuming that the offset number applied from the offset register 7 to the adder 6 is initially 0, the row address R0-R255 produced by the row counter 5 is added directly to the memory 1 and starting from the first row y
Addresses the bit line of the book. Then, as each bit row is addressed in turn, all of its bit positions are addressed in turn by dot addresses D0-D255, and the dot information is read out for display on display device 2. Since signals fl and ff are used to drive the display device 2, line scanning and field scanning are synchronized with the readout of dot information. In this way, the bit rows addressed by row addresses R0-R255 are respectively scan line L0
- Contains information displayed in L255.

However, when the offset number added from the offset register 7 to the adder 6 is not 0, the number of each row address addressing the memory 1 at any given time will no longer correspond to the scanning line occurring at that time. For example, if the offset number is 1, the row address R0 (+1=R1) is used to address the second bit row of memory 1, and the dot information in this bit row is read and the first scan line L0 will be displayed. Then the third bit row is read out with row address R1 (+1=R2) and displayed on the second scan line L1, and so on. Then, the last bit row is read out at row address R254 (+1=R255),
Displayed on scanning line L254. In the last scan line L255, the dot information contained in the first bit row R0 is read out or is "lost" and the scan line L255 is blanked or replaced with new dot information and it is scan line
Displayed on L255. Under the control of logic circuit 8,
The offset number in offset register 7 is incremented periodically. If the offset number is incremented by 1, then the offset will be 2 when the first increment occurs. As a result, for the first scan line L0, bit row R0 (+2
=R2) is read out and displayed.
And for the next scan line L1, bit row R1
The dot information within (+2=R3) is read out and displayed, etc. By periodically incrementing the offset number in this manner, the visual effect of scrolling the displayed data is achieved. An offset increment of 1 as described above produces a smooth scroll, the speed of which is determined by the frequency at which the increment occurs. For example, increments of 5 field scans each (ie, 100 ms each) will result in slow scrolling. Obviously, increasing the offset increment will make the scrolling less smooth.

Another known scrolling circuit, shown in FIG. 2, is for a data display device in which the stored display data is character-based. In this example, the data to be displayed as an independent entity is stored in the display memory 9 in a digitally encoded form, and is read out in synchronization with the scanning operation of the CRT display device 10 (this CRT display The device 10 is driven by a line frequency signal fl and a field frequency signal ff), and a character memory 11 containing dot information of a plurality of characters for use in display.
address. Characters are defined by selected dots of a dot matrix that constitute the character format for the character. For example, the character format may be a 12×10 dot matrix with 10 dot rows of 12 dots each. The dot row is intended to be displayed on a group of 10 scan lines, and each such group
It has 40 character positions with a width of 12 dots, forming one character line. The addressing of memories 9 and 11 for character display (in the absence of scrolling) is such that for each character line to be displayed, all the characters in that line are assembled from one scan line to the next; Characters will be assembled sequentially one dot line at a time, and character lines will be assembled sequentially line by line. Thus, for the first scan line in each group (of ten), the memories 9 and 11 supply dot information from the first dot row of the first character of that character row; Then the first of the second character in that line of characters
The dot information from the dot line is supplied and the same process is performed for successive characters in the character line. For the second scan line of the group, each character in the character line is provided with dot information from the second dot line, and so on for the remaining scan lines of the group.

For addressing memories 9 and 11, several counters 12, 13, 14 and 1
A pulse counting chain comprising 5 is provided. This pulse counting chain is supplied with dot pulses of frequency fd from a pulse generator 16. The first counter 12 is a modulo 12 column counter and outputs column addresses C0 to C11. these column addresses
C0-C11 are used to address the 12 dot columns of the character matrix in character memory 11. Counter 13 receives one stepping pulse per cycle of counter 12, but this is a modulo 40 character counter, character position address P0 ~ which fixes 40 character positions of one character line. Generates P39. These addresses, along with character row addresses R0' to R23' (described later), are used to read character codes from display memory 9 and address character matrices in character memory 11. Counter 14 receives stepping pulses once per cycle of counter 13, but
A ten line counter provides dot row addresses DR0-DR9 corresponding to successive groups of ten line scan pulses of display 10. This counter 14 receives the field synchronization signal and sets itself to the display device 1.
Synchronize with 0 scanning operation. As will be explained below, the dot row addresses DR0-DR9 are modified to become dot row addresses DR0'-DR9', which are used to address the ten bit rows of the character matrix in character memory 11. Counter 15, which receives stepping pulses once per cycle of counter 14, is a modulo 24 line counter and produces character line addresses R0-R23. These character line addresses are modified (as described below) to become addresses R0' to R23' corresponding to character lines, and are added to the display memory 9, as described above. Character position addresses P0 to P39 and character line addresses R0′ to
The combination with R23' serves to identify all digital symbols in the display memory 9. counter 15
is also synchronized with the scanning operation of the display device by the signal ff.

For scrolling the displayed data, two adders 17 and 18 are provided with offset registers 19 and 20, respectively. Logic circuit 21 controls the incrementing of the offset numbers in offset registers 19 and 20. Since the display is character-based, with character lines assembled from bit rows on each group of scan lines, the offset numbers provided for the scrolling function are not on a continuous line basis as in Figure 1, but on a combined line basis. Based on bit row/line and row basis. A line offset number of 0 to 10 lines is provided from an offset register 19 to an adder 17. For example, assuming the increment is 1, the offset number in offset register 19 is incremented by 1 ten times to scroll each character line sequentially into the space occupied by the previous character line on the display. The character memory 11 is addressed using the incremented dot row addresses DR0' to DR9', and once per cycle the row counter 15 is advanced by one step to lead the next character row address to the display memory 9. Alternatively or additionally, row addresses R0-R23 can be incremented by adder 18 according to an offset number added from offset register 20 (giving addresses R0'-R23'). Apparently the offset number, which is periodically incremented by one, scrolls the display one character line at a time (ie, hard scrolling). As in Figure 1,
The speed at which the offset number is incremented determines the speed at which the display is scrolled. Further, as shown in FIG. 1, the display (character line) scrolled out at the top can be redisplayed at the bottom or replaced with new display data.

The scrolling device according to the present invention shown in FIG. 3 is second in that it is adapted to character-based display.
This is equivalent to the scrolling device shown in the figure. For convenience of explanation, some of the circuit elements in FIG.
The same reference numerals as corresponding circuit elements in the figure are given.

The device of FIG.
2. This device differs from the device shown in FIG. 2 in that it is replaced with a delay count register 23 and a row mapping memory 24. The dot row counter 14 is driven to read the dot row addresses DR0 to DR9, as shown in FIG.
will occur. However, the response of this dot row counter 14 is now under the control of the start pulse sp sent from the delay counter 22. counter 1
The pulse generated once per cycle of 3 (or equivalently, the line frequency signal fl) is detected by the delay counter 22.
, and this delay counter 22 is set to count the number of these pulses before producing the start pulse SP. The delay counter 22 is set by the delay count register 23 by the logic circuit 21.
It is determined by the number of counts given to . Therefore, in this example, the start of operation of counter 14 is simply delayed for several dot rows (or scan lines). This count is progressively incremented in register 23 by logic circuit 21;
Creates a scrolling effect. Also, as in FIG. 2, counter 15 is advanced one step per cycle of counter 14. Character line addresses R0 to R23 are stored in the line mapping memory 24
used to address.

This line mapping memory 24 stores mapping data that allows each character line address R0 to R23 to be "mapped" in relation to an arbitrary character line. This provides a good degree of flexibility in the addressing of character codes in the display memory 9, so that any stored character line can be displayed on any character line on the display. In this way, not only traditional scrolling but also other character line positioning can be achieved.
One advantage of this is that display data that does not fill the entire display screen can be easily centered. Preferably, the row mapping memory 24 is a random access memory so that the mapping data therein can be changed as required by the logic circuit 21. A dashed line 25 indicates this.

Evidently, the invention is also readily applicable to scrolling circuits for data stored in bitmap form. In this case, the circuit of FIG. 1 is modified by replacing adder 6 and offset register 7 with delay counter 22 and delay count register 23. In this case, the start of dot row counter 5 is the start pulse SP from the delay counter.
(same as Figure 3). Mapping memory is not required.

The video display terminal schematically illustrated in FIG. 4 has a data display device that utilizes a scrolling circuit according to the invention. This data display device is for displaying data expressed in digital codes, and the displayed data consists of discrete characters.
The shape of a character is defined by the selected dots of a dot matrix forming the character format for the character. This video display terminal is capable of transmitting, in digitally encoded form, selected data for display on a television set at the subscriber's end via a public telephone line to a telephone subscriber who has the terminal on his side. It can be included in a data display device used in telephone data services that provides the ability to access data sources. Examples of such telephone data services include the British and German videotex services Prestel and
Bildschirmtext can be mentioned.

The video display terminal includes a modem 26 that connects the terminal to a data source 28 via a telephone line 27 (i.e., switched public telephone network).
can be accessed. Logic and processing circuitry 29 provides the signals necessary to make the telephone connection to data source 28. This logic and processing circuit 29 also forms part of a decoder which receives and processes data sequentially coming in from telephone line 27. Command keypad 30 provides user control instructions to this logic and processing circuit 29. Common address/data bus 31
interconnects logic and processing circuit 29 with display memory 32 and character memory 33. Under the control of circuit 29, digital codes extracted from the sequentially received data representing characters for display are output in parallel to data bus 31 and assigned to appropriate locations in display memory 32. Addressing means within circuit 29 then accesses the display data stored in display memory 32 and uses this to selectively address character memory 33 to produce character dot information. The shift register 34 receives this character dot information and stores it in the color lookup table 35.
is driven, a digital color code is created therefrom, and this is applied to the D/A converter 36. The output signal from the D/A converter 36 is an R, G, B character generation signal which drives a television receiver 37 to display the characters represented by the display data on its screen. Attribute logic 38 is also provided that includes control data relating to various display attributes, such as "flash,""underline," and "color selection." Data identifying various attributes to be added to the displayed characters is included within the received data and stored in display memory 32 along with the character data. circuit 29
is responsive to the attribute data stored in display memory 32 and initializes associated attribute controls by attribute logic 38 when the character is displayed;
Give the relevant attribute. Timing circuit 39 provides timing control to the data display.

[Brief explanation of drawings]

1 and 2 are block diagrams of a known scrolling circuit, FIG. 3 is a block diagram of a scrolling circuit according to the present invention, and FIG. 4 is a data display device including a scrolling circuit according to the present invention. FIG. 2 is a block diagram of a video display terminal. DESCRIPTION OF SYMBOLS 1... Memory, 2... Display device, 3... Pulse generator, 4... Dot counter, 5... Line counter, 6... Adder, 7... Offset register,
8...Logic circuit, 9...Display memory, 10...
CRT display device, 11...Character memory, 12-1
5...Counter, 16...Pulse generator, 17,
18...Adder, 19, 20...Offset register, 21...Logic circuit, 22...Delay counter, 23...Delay counting register, 24...Row mapping memory, 25...Memory 2 by logic circuit
Broken line indicating changing 4, 26...modem, 2
7...Telephone line, 28...Data source, 29...Logic and processing circuit, 30...Command keypad, 3
1... Address/data bus, 32... Display memory, 33... Character memory, 34... Shift register, 35... Color lookup table, 36
...D/A converter, 37...television receiver, 38...attribute logic device, 39...timing circuit.

Claims (1)

Claims: 1. A data display for displaying as an independent entity on the screen of a raster scan display a quantity of stored data that is repeatedly accessed for display in a circular cycle of scan lines. a delay count register capable of storing a delay count number in a scrolling circuit in the device capable of progressively (vertically) shifting the displayed data on the screen of the display device;
a logic circuit for periodically modifying the delay count; and a logic circuit connected to receive the stored count from the delay count register and connected to receive a rotating cycle of scan line pulses. and a delay counter operative to generate a start signal after receiving a number of these pulses corresponding to said count number, and connected to receive pulses at a line scanning frequency and transmit said start signal to a dot row counter. A dot row counter is operated to produce one dot row address for each received pulse after being applied to the display, and these dot row addresses are used to read out information bits about the dot rows of the display. A scrolling circuit characterized by providing. 2. In the scrolling circuit according to claim 1 in a data display device in which data stored for display is in the form of a bit map, the dot row counter is set for each scanning line in a cycle in which the scanning lines circulate. 1. A scrolling circuit characterized in that the scrolling circuit is provided to provide a dot row address in a rotating cycle having one address. 3. In the scrolling circuit according to claim 1 in a data display device in which data stored for display is in a character-based format, the dot row counter is used to display a character row. provided for providing dot row addresses in a rotating cycle having one address for each scan line in the group of scan lines, such that
The scrolling circuit further includes a character line counter connected to advance one step for each cycle of the dot row address and providing a character line address of one cycle belonging to each character line for display in each scan line group. , a scrolling circuit is further connected to receive the character line address and comprises a line map memory for operating according to the contents of the memory and mapping the character line address to different character line addresses belonging to other character lines, A scrolling circuit characterized in that character line addresses are used to select stored characters from which information bits are to be read for display. 4. The scrolling circuit according to claim 3, wherein the four-row map memory is a random access memory, and its contents are modified in accordance with a request of a logic circuit. 5. The scrolling circuit according to claim 3 or 4, wherein the character line counter is also connected to receive a start signal from the delay counter. 6. The scrolling circuit according to any one of the preceding claims, characterized in that the operation of the delay counter in each scan cycle of the display is synchronized with a (field) synchronization signal for the display device. 7. A scrolling circuit in a data display device substantially as described with respect to FIG. 3 in conjunction with FIG. 1 or 2. 8. Claims: A data display device substantially as described in FIG. 4, including a scrolling circuit according to any of the preceding claims.