JPH023255A - Evaluation method for integrated circuit device and semiconductor device for integrated circuit device evaluation - Google Patents

Abstract

PURPOSE:To clarify which technical element the problem is in by dividing an integrated circuit device that a circuit constituting element is arranged into the specified scales, and evaluating the yield rates of the connection of a wiring layer, the interline leakage of a wiring layer, and the leakage between wiring layers so as to seek the yield rate of an integrated circuit device from the results. CONSTITUTION:For example, the area of 256K bits is properly divided so that the yield rate may be easily evaluated. 256K bits area is divided into three areas of 64K bits and three area of 16K bits, and the residual is made a drawing-out area to a pad. That is, they are made to be a pad 10 and areas A1, B1, C1, A2, B2 and C2. For example, the area A1 and A2 are made up based on the aluminum Al1 of the first layer of a memory cell such that breaking of a word line 20, breaking of a power source line 21, and interline leakage of Al1 can be evaluated. Also, they are made up based on the aluminum Al2 of the second layer of the memory cell such that breaking of a bit line 22, breaking of an earth line 23, and interline leakage of the Al2 can be evaluated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention aims to evaluate the yield for each technical element of manufacturing when evaluating the yield in manufacturing memory circuits and logic circuits consisting of repeated unit circuits. The present invention relates to a highly efficient yield evaluation method that makes it possible to estimate the yield of an integrated circuit device as a whole and clarify the yield factors of each technical element, and a device that implements the method.

[Conventional technology]

Conventionally, when evaluating the yield of integrated circuits at the development stage, the target integrated circuit itself was prototyped and the yield was evaluated. There was a drawback that there was.

Meanwhile, in parallel, a dedicated test element group (TEG) pattern is formed on the same wafer as the target integrated circuit or on a different wafer, and these are measured to evaluate the yield for each technological element. This method was also used (see "Kondo et al., Journal of the Institute of Electronics and Communication Engineers, Vol. 62, No. 4, p. 393, April 1978"). An example of a conventional yield evaluation TEG pattern is shown in FIG. FIG. 5(a) is a pattern diagram showing an example of a pattern for measuring disconnection of the wiring and short-circuit or leakage between the lines when the wiring passes orthogonally over a step. Further, FIG. 5(b) is a pattern diagram showing a structure in which lower layer wiring and upper layer wiring are connected in multiple stages through contact holes, and is used to evaluate the yield of contact connection.

[Problem to be solved by the invention]

Such conventional examples had the following drawbacks.

(2) In order to perform various evaluations within one chip, it is necessary to allocate areas within the limited chip area, but as a result, the area allocated to one evaluation item becomes small. For example, in the case of FIG. 5 (al), the total length of the wiring was approximately 20 mm.On the other hand, if we take the case of a 256-bit static RAM (256KSRAM) as an example, the total length of the first layer aluminum wiring is approximately 20 mm. .8 m.Here, it is assumed that the yield Y at which the wiring does not break is expressed by the following equation.

Y=exp (-D-L) Here, D is the defect rate and L is the wiring length. 256KSR
Assuming that AM yield is determined by disconnections and shorts in six important mask layers, the yield level at the time of evaluation was 10.
%, and if the yield for each element is equally distributed, it will be about 83%. If the yield for each element is Y-83%, D
= 6.6X 10-5/mm, so the above TE
In the case of G, the yield YT is 99.9%. - 45 chips per wafer (10mm opening, 4 inch wafer)
If this is possible, the number of defective products in 10 wafers (25 wafers) will be 1 to 2, and the accuracy of yield evaluation will be extremely poor. If the yield level increases further, it becomes completely impossible to evaluate. This situation is almost the same in the case of FIG. 5(b).

[Means to solve the problem]

In order to solve these problems, the present invention provides a method for evaluating the yield of integrated circuit devices consisting of repeating unit circuits, in which an integrated circuit device in which circuit components are arranged is divided into predetermined scales, and the divided integrated circuits are The yield of connections between wiring layers, leaks between wiring layers, and leaks between wiring layers is evaluated for each circuit device part, and the yield of the integrated circuit device is determined from the yield results.

In addition, in integrated circuit devices consisting of repeating unit circuits, the integrated circuit in which circuit components are arranged is divided into a scale that allows for yield evaluation, and wiring layers are connected and wiring layers are connected on the divided integrated circuit device parts. A pattern is formed so that the yield of leakage between lines and between wiring layers can be measured.

[Effect]

In the present invention, the yield reaches an evaluable level, it becomes possible to evaluate the yield, and it is possible to clarify which technical element has a problem.

〔Example〕

The present invention uses the lower layer of the wiring of a memory circuit device or logic circuit device whose yield is to be evaluated as is, divides it into an appropriate size that allows yield evaluation, and forms a dedicated wiring layer above it. This enables yield evaluation for each technical element that contributes to yield.

Next, the features of the present invention and the differences from the prior art will be described. The present invention is characterized in that, in the yield evaluation of integrated circuit devices consisting of repeated unit circuits, the integrated circuit devices in which circuit components such as transistors, diodes, capacitors, and resistors are arranged are divided into predetermined scales. , a method for evaluating the yield of connections between wiring layers, leakage between wiring layers, and leakage between wiring layers for each divided integrated circuit device part, and determining the yield of an integrated circuit device from the above yield results, and a test element therefor. Group (TEG). In conventional technology, the underlying pattern of the integrated circuit device for which the yield is to be evaluated is used as is, and there is no concept of dividing the scale so that it is possible to evaluate the yield even if the yield fluctuates greatly. Either the yield of the integrated circuit itself was evaluated, or a relatively small-scale TEG was independently designed for each element, and this was mounted on a single chip and evaluated.

In the embodiment of the present invention, 256-bit MO3 type static random access memory (256KSRA
M) yield evaluation method and evaluation T used at that time
EG will be described in detail.

Here, it can be considered that the yield of a MOS memory is almost determined by the yield of each of the following items in cells, which account for most of the total. That is, (1) junction region: junction leak; (2) gate region: gate insulating film; (2) word line; disconnection or short; (2) bit line: disconnection or short.

In the present invention, the semiconductor memory device is manufactured by the same process as the MOS memory until immediately before the contact hole is formed, and the steps after the contact hole are performed by separately preparing a pattern that can evaluate each of the above items.

At this time, the area in focus at 256 is divided appropriately to facilitate yield evaluation. In this example, 256
K was divided into 64 and 3 regions and 16 and 3 regions. The rest is a drawer area up to the pad. This situation is the first
As shown in the figure. In FIG. 1, 10 is a pad, Am B
l, C1, A2°B2. C2 indicates an area. Each area in 64 and 16 is of the following three types (area A1 and A2,
It is divided into regions B1 and B2 and regions C1 and C2).

First, areas A1 and A2 will be explained.

Figure 2 (al is the first layer of aluminum (A
ll), and is designed to evaluate disconnections in the word line 20, disconnections in the power supply line 21, and leaks between ANI lines. Figure 2 (bl is created based on the second layer of aluminum (A#2) of the memory cell, and evaluates the disconnection of the bit line 22, the disconnection of the ground wire 23, and the gap between the lines of A7!2. It is now possible to do so.

Next, regions B1 and B2 will be explained.

FIG. 3 +al similarly shows An of the memory cell, which enables evaluation of disconnection of the word line 30 and forms the Aj71 electrode for evaluation of leakage between aluminum layers. Figure 3 (bl is Aβ for evaluating leakage between aluminum layers)
It forms two electrodes. Figure 3(c) shows how An and A12 overlap on the plane, and Figure 3(d) shows the first layer of aluminum (,6/21) 31 and the second layer of aluminum (A#2). 32 is shown in the cross section.

Next, regions C1 and C2 will be explained.

FIG. 4(a) shows the pattern of All, in which the gate 40, p junction 41 and n
It is connected to the well 42, and leakage of each of the above items can be evaluated. FIG. 4(b) shows the interconnection in the process after the contact hole.

Measure the insulation resistance of each TEG above when DC is applied,
By evaluating each yield, the target 256
The yield of KSRAM can be estimated.

The above explanation is for 256KSRAM, but it is also applicable to LSIs with relatively regular patterns such as mask slice LSIs and standard cell type logic LSIs.
The same applies to

〔Effect of the invention〕

As explained above, the present invention has the effect that by dividing the product into a scale that allows yield evaluation, the yield reaches an evaluable level and yield evaluation becomes possible. Furthermore, by conducting separate evaluations for each technical element, it is possible to clarify which technical element has a problem. Therefore, it is possible to shorten the period of LSI development and improve efficiency.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, FIG. 2 is a wiring pattern diagram for 4 bits in areas A1 and A2 of the embodiment of the present invention, and FIG. 3 is an area of the embodiment of the present invention. A pattern diagram showing the wiring pattern for 4 bits in the B1 and B2 portions and the overlapping state of the wiring, FIG. FIG. 5 is a pattern diagram showing conventional wiring connection and contact multi-stage connection yield evaluation TEG. IO...Pad, 20.30...Word line, 21.
...Power supply line, 22...Bit line, 23...Earth wire, 31...First layer aluminum, 32...Second layer aluminum, 40...Gate electrode, 41...n゛Diffusion layer, 42...n well.

Claims (2)

[Claims] (1) In a method for evaluating the yield of an integrated circuit device consisting of repeating unit circuits, the integrated circuit device in which circuit constituent elements such as transistors, diodes, capacitors, and resistors are arranged is divided into sizes capable of evaluating the yield; An integrated circuit characterized in that the yield of connections between wiring layers, leakage between wiring layers, and leakage between wiring layers is evaluated for each divided integrated circuit device part, and the yield of the integrated circuit device is determined from the yield results. How to evaluate equipment. (2) In an integrated circuit device consisting of repeating unit circuits, the integrated circuit in which circuit components such as transistors, diodes, capacitors, and resistors are arranged is divided into a scale that allows yield evaluation, and the divided integrated circuit is 1. A semiconductor device for evaluating an integrated circuit device, characterized in that a pattern is formed on a circuit device portion so that the yield of connections between wiring layers, leakage between wiring layers, and leakage between wiring layers can be measured.