JPH0232446A - Bus control system - Google Patents

Abstract

PURPOSE:To make another line unit accessible, and to suppress a fault to a minimum by segmenting a fault generating part when the bus fault occurs, making them rewritable, and masking a request signal for the unrewritable fault. CONSTITUTION:When the fault exists on a communication control bus 19, a memory access request signal LMRQ and a time-out signal TMO after the arbitration of an arbiter are active, first time-out generation interrupting signal LUIPT1 is continuously generated, and a line unit LU31 recognizes the generation of the fault on the control bus 19. On the other hand, as soon as the LU fault generation, a time-out detecting circuit 8 generates interruption to a microprocessor 6. In addition, when the fault of the control bus 19 is transient, an LUIPT1 signal becomes inactive, and the LU31 starts retrying action. For the fault, for which retrying is impossible, the request signal is masked, and an effect on the system can be suppressed to minimum.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a bus control system, particularly a communication processor in which a communication processing device that performs data processing and a communication control device that controls a line are connected via a bus. This paper relates to a bus control method.

(Prior Art) FIG. 8 is a diagram showing an example of the configuration of a computer system to which the present invention is applied. In the figure, 16 is a system bus. This system bus 16 includes a central processing unit (CP).
U) 13 and the main memory (MEM) under the CPU 13.
) 12, and a system control device 1 that controls the entire system.
1, a communication processor 14 and other modules (FDD controller, etc.) 15 are connected.

FIG. 9 is a configuration block diagram of the communication processor 14 in FIG. 8. This communication processor 14 consists of a communication processing device 16 and a communication control device 17, both of which are connected by a communication control bus 19. The communication processing device 16 mainly performs protocol control, and the communication control device 17 mainly performs line control. The communication processing device 16 has a local memory (LM) 5, a bus, and an interface unit (hereinafter referred to as BU).
SINFB) 2, and the communication control device 17 includes a line unit (L
U) 3□~3n and bus interface section (hereinafter referred to as BUS)
It is composed of 1 (sometimes called INFA).

FIG. 2 is a detailed block diagram of a conventional example of the communication processor 14 shown in FIG. 8, particularly regarding the interface section between the communication control device 17 and the communication processing device 16.

In the figure, 4 is an arbiter, 5 is an LM, 6 is a microprocessor, and A and D buses are memory address lines and data lines.

MRQA+NMRQAn, MRQB+~MRQB,
indicates a memory access request signal, and LMREQ indicates a memory access request signal after arbitration by the arbiter 4. DMAE
ND1 to DMAENDn, DMAEND indicates a memory access end signal. BRQI to BRQn represent communication control bus acquisition request signals, and BGNT+ to BGNT represent memory access permission signals. LMSEL, 5ELI~5
ELn indicates an access request selection signal.

The MRQA, -MRQAn signals and A and D buses from each LU 31 to 3n are input to BtlSINFAl. In addition, a signal DMAEND that becomes active from BUSINFAI to each LU3+ to 3r1 when memory access ends
, ~DMAENDn are output. BUSINFAI
is the BRQ+ corresponding to each MRQA, ~MRQAn signal.
~BRQn signal is generated. These BRQ+ to BRQn signals are input to BUSINFB2 via the communication control bus 19. BUSINFB2 has each B RQ l=B
MRQBt to MRQBn signals are generated from the RQn signal. The MRQB, -MRQBn signals are input to an arbiter 4 for arbitrating conflicts. The output of arbiter 4, ie, the LMREQ signal, is input to 1M5.

Also, the DMAEND signal output from 1M5 is BUSI
The data is input via NFB2 and BUSINFAI to the LU that is actually permitted to access among the memory access request sources.

In addition, FIG. 3 shows LU3 in FIG. A data transfer sequence chart between any of LU3n and 1M5, and FIG. 4 is a timing chart showing the timing of each control line during this data transfer. Data transfer control will be explained according to the numbers shown in these figures.

(2) LU3□ activates the DMA request signal (CMRQAI). (2) BUSINFAI activates the BRQ+ signal for the communication control bus 19; ■BL]5I
NFB2 performs MRQ when the BRQ+ signal becomes active.
B. Activate the signal. (2) The arbiter 4 selects one MRQB from among a plurality of MRQB signals. ■
Furthermore, arbiter 4 outputs the LMREQ signal to 1M5. 01M5 is LMSEL from LMREQ signal
Generate a signal. ■The arbiter 4 selects the LU corresponding to the MRQB signal that has been granted access as a result of arbitration.
Returns the SEL+ signal. ■BUSINFB2 is S
When the EL+ signal becomes active, BGNT+ is activated. (iBtlsINFAl performs data transmission and reception between LU3. and 1M5 via the A and D buses, such as address transfer, read data or write data transfer, and single read/write operation for 1M5.01M5
issues a DMAEND signal when data transmission/reception is completed.

The DMAEND signal is connected to BUSINFB2 and BUSIN
Memory access request source LU3. reach. @Ll who received DMAEND] 3+ is MRQ
Make the A+ signal inactive.

@ When MRQAI signal becomes inactive, BRQ+
The signal is made inactive.

(Problem to be Solved by the Invention) However, in the conventional bus control method described above, if a failure occurs in the LU and the MRQA from the LU continues to be output, the BRQ also continues to be output. Become,
There is a problem in that the communication control bus is monopolized by this faulty LU, which affects the operation of the entire system.

Also, if a failure occurs in the LU or communication control bus, MRQ,
If the error continues to be output, the system itself cannot distinguish whether the failure is caused by the LU or the communication control bus, so it is not possible to try accessing between the LU and LM. There was a problem.

The present invention solves these problems in conventional bus control methods, enables failure situation analysis when a failure occurs, and
The purpose is to provide a bus control method that allows retries using the system's own functions.

(Means for Solving the Problems) In the present invention, a plurality of access circuits that generate access request signals to a bus and an arbiter circuit that arbitrates access request signals from the plurality of access circuits are connected via the bus. In the bus control method of the system, the first timeout detection means time-monitors the output of the arbiter circuit, and when the first timeout detection means detects a timeout, the first timeout detection means acquires the bus from among the plurality of access circuits. means for latching a code indicating an access circuit in the arbiter; means for notifying the access circuit that is acquiring the bus of the occurrence of a first timeout; and a second means for time-monitoring the output of the arbiter circuit after the latching. timeout detection means; means for notifying a host device of the occurrence of a second timeout when the second timeout detection means detects a timeout; and an instruction from the host device that has been notified of the occurrence of the second timeout. This bus control system is characterized by further comprising means for masking an access request signal from the access circuit that is acquiring the bus.

(Function) The functions of each means particularly provided in the bus control system of the present invention (hereinafter sometimes referred to as the system of the present invention) will be described below.

The first timeout detection means detects the BRQ due to the occurrence of a failure.
When I remains output, it is monitored whether the memory access request signal (LM1'IQ) from the arbiter circuit becomes active and then becomes inactive after a certain period of time. When a timeout occurs, a timeout signal (TMO) is sent to the latch means at the next stage and the first timeout occurrence notification means.

The latch means latches a code indicating an access circuit that is acquiring the bus when a failure occurs.

The first timeout occurrence notification means notifies the access circuit that is acquiring the bus of the first timeout occurrence by an interrupt. The TMO signal becomes inactive when the MRQB signal becomes inactive.

The second timeout detection means monitors whether the BRQ+ signal becomes inactive after a certain period of time after the first timeout occurrence notification.

The second timeout occurrence notification means notifies the host device of the second timeout occurrence. This host device can know the source of the access request where the failure has occurred based on the code latched by the latch means.

The masking means masks the MRQB+ signal of the relevant access request source in response to an instruction from the host device, makes the input to the arbiter circuit inactive, and forcibly terminates the access.

Since each of the above-mentioned means of the present invention system has such a function, if a failure occurs in the LU31 that is the source of the access request, the MRQ
When A+ remains output, the higher-level device can detect this fact by the second timeout occurrence notification, and the first timeout occurrence notification is performed and the MR
B even though the QAI signal became inactive
When the RQ+ signal remains output, LU3. It can be determined that a failure has occurred in the communication control bus.

The host device collects such detection results as fault information using the I10 command and recognizes the fault situation.

After that, a retry is possible by issuing a reset and performing initialization.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, and is a detailed block diagram of the communication processor 14 in FIG. 8, similar to FIG. 2.

In the figure, 7 is a timeout detection circuit (I) as a first timeout detection means, which monitors the LMRQ signal over time. 8 is a timeout detection circuit (II) as a second timeout detection means, and the timeout detection circuit (I) sends out a TMO signal, monitors the TMO signal over time, and issues a timeout occurrence interrupt to the microprocessor 6 when a timeout occurs. Generates a signal (TMOI PT). Reference numeral 9 denotes an error LU number storage register (RG) as a latch means and a first timeout occurrence notification means, and as shown in FIG. 5, the SEL sample REG20. It consists of a buffer memory (BUF) 21 and a TMO signal falling differentiation circuit 22. The error number storage RG9 is stored in the LU3. SEL sample REG2 by the trigger from the falling differentiation circuit 22
In addition to latching it to 0 and storing it in the BUF 21 so that it can be read by the processor, it also generates an interrupt signal (LtlIPTI) to notify the LU 31 of the occurrence of the first timeout. Further, 10 is a LUMRQ mask RG as a masking means,
A mask signal (MSK
, ) are generated according to instructions from the microprocessor 6. The circuit of FIG. 1 is similar to the conventional circuit of FIG. 2 except for these specifically mentioned components.

Therefore, description of similar components will be omitted. It should be noted that the abbreviations of signals in the figure that are similar to those in FIG. 2 are also given the same symbols.

LMRQ is a memory access request signal after arbitration by the arbiter 4, similar to LMREQ in FIG.

Next, with reference to FIGS. 1, 5, and 6, the control operation when DMA transfer is normally performed between LU3+ and 1M5 in the circuit of FIG. 1 will be explained. Note that the symbols such as ■ in the explanatory text are those shown in FIG. 6, and the same symbols are used for operations similar to those of the prior art.

■The MRQA+ signal is output from LU3. ■B
USINFAI outputs a BRQ signal. ■BUS
INFB2 creates an MRQBI signal from the BRQs signal and inputs it to the arbiter 4. ■Arbiter 4 has multiple MRs
One MRQB+ signal is selected from the QBI to MRQBn signals and an LMRQ signal is output. ■LM5 outputs the LMSEL signal from the LMRQ signal and LU3. memory access.

■Arbiter 4 selects the s corresponding to the selected MRQB+ signal.
Activate the EL+ signal. ■BUSINFB2 activates the BGNT+ signal by the SEL signal.

BUSINFAl performs data transfer between LU3+ and 1M5 via the A and D buses when the BGNT signal becomes active. ■LM5 uses DMA at the end of data transfer.
Issue END. DMAEND signal is BUSINF
The memory access request source LU3+ is reached via B2 and BUSINFAI. [Phase] Upon receiving the DMAEND signal, the LU 31 makes the MRQA signal inactive. ■MRQA, BUS when signal becomes inactive
The INF light makes the BRQI signal inactive. B.R.
When the Q signal becomes inactive, the MRQB signal becomes inactive and the LMRQ signal also becomes inactive.

Next, referring to FIG. 7 instead of FIG. 6, LU3
The control operation in the circuit of FIG. 1 when a failure occurs in □ will be explained.

First, the MRQA signal is output from Lt13□, and the M
The sequence from when the RQA+ signal is output to when the BGNT+ signal is output (■ to ■) is the same as the normal sequence, but
Despite issuing the BGNT I signal, the BRQI
If the signal remains active, the LMRQ signal also remains active (■), so the time required for the LMRQ signal to go from active to inactive during normal operation is
It is assumed that the timeout will be approximately 6 times as long. The LMRQ signal timeout detection circuit (I) 7 times out,
Outputs the TMO signal (0). SEL is sampled at the rising edge of the TMO signal in Figure 5 and reset at the falling edge.
The LU number (i) for which the bus is being acquired is stored in sample REG20.

Furthermore, the corresponding LU3 from the error Lt1 number storage RG9
゜, the LtlIPT signal is generated and the second
The timeout detection circuit (II) 8 starts operating.

At this time, if a failure occurs in LU3+, for example in a runaway or stop state, LU3+ does not make the MRQA signal inactive despite sending the LUH'T signal, so LMRQ remains active. In this case, the timeout is approximately 5 to 6 times the time from when MRQA+ becomes inactive to when the TMO signal becomes inactive after issuing LtlIPT. The timeout detection circuit (II) 8 times out and generates an interrupt to the microprocessor 6 (■).
Q. To prevent the communication control bus 19 from being locked due to a signal, read the LIJ number (i) stored in the error LU number storage REG 9. LUMR (1'scregiog: 1n set (0) As a result, the MSK signal corresponding to the corresponding LU3 becomes active, the MRQB becomes inactive, and the other L
U's access to LM5 becomes possible. Subsequently, the microprocessor 6 sends BRQl,
B (JNT collects failure information using the non-dependent /○ command and recognizes that LU3 is the failure. After that, issues a reset to the corresponding U31 in order to perform a retry operation. , performs initialization and starts restarting operation.

Next, a control operation in the circuit shown in FIG. 1 when a failure occurs in the communication control bus 19 will be described. The time chart in this case is the same as that in FIG. 7 except that the MRQAI in FIG. 7 is as indicated by a broken line.

LMRQ signal timeout detection circuit (1) 7 times out and operates until it issues the LUIPTI signal (■
~0) is the same as at the time of LU failure. By sending the LUIPT signal, the corresponding LL]3+ makes MI'tQAl inactive. At this time, if the communication control bus 19 is normal, the MRQAI is made inactive, the TMO signal becomes inactive, the LUIPT+ signal also becomes inactive, and the access ends. However, if there is a failure in the communication control bus 19, LMRQ remains active and the TMO signal is also active, and for this reason LUIPT+ continues to occur, so L
U3. recognizes that a fault has occurred in the communication control bus 19. On the other hand, for the microprocessor 6, L
As in the case of U failure, the timeout detection circuit (■) 8 times out and generates an interrupt (0). The subsequent operation is L.
The operation is the same as in the case of an SI failure, but when the microprocessor 6 collects LU failure information using the I10 instruction, the microprocessor 6
L] Notified by 3+ that there is a communication control bus failure. In this manner, the microprocessor recognizes communication control bus failures.

Additionally, communication control bus failures may be temporary. Assume that the first timeout occurs at such a time. L
The operation up to the occurrence of UIPT is the same as when an LSI failure occurs. LUIPT, by sending a signal, LU3. is MRQA
Let r be inactive. Since the failure is temporary, the inactivity of the MRQA+ signal causes the BRQ+
The BRQ signal becomes inactive, the MRQB signal becomes inactive, and the LMRQ signal also becomes inactive. When the LMRQ signal becomes inactive, the timeout detection circuit (■) 7 is reset and the error LU number storage RE is reset.
G9 is also initialized, which causes the LUIPTI signal to become inactive and LU3. can know how to recover from a failure. Therefore, LU3□ starts a retry operation.

(Effects of the Invention) As described in detail above, according to the present invention, when a bus failure occurs, it is possible to isolate the location of the failure (due to the LU or the bus failure) and to perform a retry. Furthermore, in the event of a failure that cannot be retried, by masking the request signal, access by other LUs will be possible when the failure occurs.
The impact on the system can be kept to a minimum.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention, and FIG.
8 is a detailed configuration block diagram of the conventional example of the communication processor 14, FIG. 3 is a data transfer sequence chart in FIG. 2, FIG. 4 is a timing chart during data transfer in FIG. 2, and FIG. is a configuration block diagram of the error LU number storage RG9 in Figure 1, Figure 6 is a time chart of the circuit in Figure 1 during normal operation, and Figure 7 is a diagram of the circuit in Figure 1 when a failure occurs in LU31. Time chart, No. 8
The figure shows an example of the configuration of a computer system.
2 is a configuration block diagram of a communication processor 14 in the figure. FIG. 7... Timeout detection circuit (I), 8... Timeout detection circuit (II), 9... Error LSI number storage RG. 10...LUMRQ mask REG, LMRQ...memory access request signal after arbiter arbitration, TMO...timeout signal, LUIPT,...first timeout occurrence interrupt signal,
TMOIPT...second timeout occurrence interrupt signal,
MSK+...Mask signal. Patent Applicant: Oki Electric Industry Co., Ltd. 2-Digital Day! Transfer time swimming chart Figure 4

Claims (1)

[Scope of Claims] Bus control of a system in which a plurality of access circuits that generate bus access request signals and an arbiter circuit that arbitrates access request signals from the plurality of access circuits are connected via the bus. In the method, a first timeout detection means for time-monitoring the output of the arbiter circuit, and a code indicating an access circuit that is acquiring a bus among the plurality of access circuits when the first timeout detection means detects a timeout. means for notifying the access circuit that is acquiring the bus of the occurrence of the first timeout; second timeout detection means that further monitors the output of the arbiter circuit over time after the latching; means for notifying a host device of the occurrence of a second timeout when the second timeout detection means detects a timeout; and access during the bus acquisition based on an instruction from the host device that has been notified of the occurrence of the second timeout. 1. A bus control method comprising: means for masking an access request signal from a circuit.