JPH0231580A - Interpolating signal formation circuit - Google Patents

Abstract

PURPOSE:To eliminate the necessity of a line memory by forming interpolating signals for moving and still pictures by using a three-port field memory equipped with one input terminal and two output terminals as a delay line. CONSTITUTION:A luminance signal Y is supplied to a field memory 11 constituting a delay line and the memory 11 is constituted of a so called three-port memory equipped with the 1st output terminal having delay time of 263H and 2nd output terminal having a delay time of 1H. When the input signal of the memory 11, output signal of the 1st output terminal, and output signal of the 2nd output terminal are respectively represented by (h), (j), and (i), the output signal h+i/2 of an adder 602 becomes the interpolating scanning line signal of a moving picture part and, at the same time, the output signal (j) of the 1st output terminal of the memory 11 becomes the interpolating scanning line signal of a still picture part. Therefore, an interpolating scanning signal Yc in which the interpolating scanning signals of the moving and still picture parts are added to each other in a rate corresponding to the degree of movement is outputted from the adder 604. Therefore, no line memory is required.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Example G1 Description of the first example (Fig. 1) (Figure 1) G2 Description of the second embodiment (Figure 2) G. Description of the third embodiment (Figures 4 and 5) C9 Description of the fourth embodiment (Figure 8) H Invention Effect A: Industrial Application Field The present invention provides an interpolation signal forming circuit suitable for forming an interpolation signal at a cost of 4 for a television receiver that performs high image quality processing such as scanning line interpolation, such as a so-called 10TV. Regarding.

B. Summary of the Invention The present invention uses a 3-port field memory having one input terminal and two output terminals as a delay line to form a moving image interpolation signal and a still image interpolation signal. This eliminates the need for a line memory, reduces the number of patterns on the substrate, reduces the circuit area, and makes the structure more economical.

C. Prior Art FIG. 9 shows the configuration of an example of a television receiver.

In the figure, the video signal from the input terminal (62) is A
After being converted into a digital signal by a /D converter (63), it is supplied to a Y/C separation circuit (64) where it is separated into a luminance signal Y and a color signal C.

The luminance signal Y output from the Y/C separation circuit (64) is
It is supplied to the scanning line interpolation circuit (65Y). The color signal C output from the Y/C separation circuit (64) is supplied to a chroma decoder (66) and color demodulated. The time-division signal R-Y/B-Y of the red difference signal R-Y1 and the blue difference signal B-Y output from this chroma decoder (66) is supplied to a scanning line interpolation circuit (65C), and this scanning line interpolation circuit From the circuits (65Y) and (65C), the main scanning line signal Y
In addition to m, Rm-Ym/Bm-Ym, interpolated scanning line signals Yc, Rc-Yc/Bc-Yc are output simultaneously.

Further, the luminance signal Y output from the Y/C separation circuit (64) is supplied to a motion detection circuit (50), and the motion detection signal from this motion detection circuit (50) is sent to a coefficient generator (51).
supplied to Scanning line interpolation circuit (65Y), (65C
) is generated by this coefficient generator (51), and the value is changed depending on the magnitude of the motion detection signal. For example, in a still image portion, Q is set, and the maximum value of K is set to 1.

The scanning line interpolation circuit (65Y) is configured as shown in FIG. In the same figure, the Y/C separation circuit (64)
The luminance signal Y supplied from the line memory (601) is supplied to a line memory (601) that constitutes a delay line. This line memo IJ
The input signal and output signal of (601) are sent to the adder (601).
02) for addition and averaging, and this adder (602
) The output signal of K (K≦
1) After being multiplied, it is supplied to the adder (604).

Furthermore, the luminance signal Y is supplied to a field memory (605) that constitutes a delay line. This field memo IJ
The delay time at (605) is 263H. This field memo! The output signal of J (605) is multiplied by (1-K) by a coefficient unit (606) and then supplied to an adder (604).

FIG. 11 is a diagram showing the scanning line structure on the time-vertical plane, and the ◯ marks indicate the scanning lines of each field. Memo the above human signal on h1 line! 11 field memo of the output signal of J (601)! Assuming that the output signal of I (605) is J, these signals h-j have the positional relationship shown in FIG.

In the scanning line interpolation circuit (65Y), the adder (60
2), and the output signal J of the field memory (605) becomes an interpolated scanning line signal for the still image portion. Therefore, the adder (604) outputs an interpolated scanning line signal Yc in which the interpolated scanning line signals of the moving image part and the still image part are added at a ratio according to the degree of movement.

The interpolation scanning line is located at the position marked 2 in FIG.

Further, the input signal Y is directly used as the main scanning line signal Ym.

Although the description is omitted, the scanning line interpolation circuit (65C) is similarly configured.

Main scanning line signals Ym, Rm -Ym/Bm output from the scanning line interpolation circuits (65Y) and (65C)
-Ym, interpolated scanning line signal Yc, Rc -Yc/
Bc - Yc are respectively time compression circuits (j7Y),
(67C). This time compression circuit (67
Y), (67C) is the main scanning line signal Ym.

Rm −Ym/Bm −Ym and interpolated scanning line signal Yc,
Rc-Yc/Bc-Yc are each time-axis compressed to 1/2 and output continuously. In this case, the time compression circuit (67C) separately outputs a red difference signal and a blue difference signal.

The double-speed luminance signal and color difference signal output from the time compression ports (67Y) and (67C) are converted into analog signals by D/A converters (68Y), (68R), and (68B), respectively.

D/A converter (68Y), (68R), (68B)
The double-speed luminance signal and color difference signal outputted from the matrix circuit (73) are respectively supplied to a matrix circuit (73). The double-speed red, green, and blue signals R1G and B outputted from this matrix circuit (73) are outputted from the amplifier (74R), (7
4G>, (74B) to the color picture tube (75
), and non-interlaced scanning display with twice the number of scanning lines is performed on this color picture tube (75).

A television receiver such as the example shown in FIG. 9 is described in, for example, NEc Technical Report Vol. 1.41 No. 3/19881. :
Are listed.

D Problems to be solved by the invention In this example of FIG. 9, a scanning line interpolation circuit (65Y).

(65C) is configured using a line memory (6 old) in addition to a field memory (605) as shown in FIG.

Therefore, there were many patterns on the substrate. Also, since the memory size is determined by the number of pins, line memory (601
) was not much smaller than the field memory (605), and the circuit area on the board was larger. Furthermore, the price of line memory (601) was not much cheaper than field memory (605), and was relatively expensive.

Therefore, an object of the present invention is to reduce the number of patterns on the substrate, reduce the circuit area, and further reduce the cost.

E Means for Solving the Problems This invention uses a three-port field memory (11) having one input terminal and two output terminals as a delay line, and calculates the time difference between the signals between the three terminals by A video interpolation signal is formed by adding the two signals whose time difference is 1 horizontal period, respectively, with a time difference of 1 horizontal period, 262 horizontal periods, and 263 horizontal periods, and a time difference of 263 horizontal periods with respect to one of the two signals. A still image interpolation signal is formed using this signal.

F Effect In the above configuration, line memory is not required, so
The number of circuit patterns on the substrate is reduced, the circuit area is also reduced, and the structure can be made more inexpensively.

G Example G1 First Example (FIG. 1) First, a first example of the present invention will be described with reference to FIG. This example is an example applied to a scanning line interpolation circuit for luminance signals, and parts corresponding to the example in FIG. 10 are designated with the same reference numerals.

In the figure, a luminance signal Y is supplied to a field memory (11) that constitutes a delay line. This field memory (11) is configured as a so-called 3-port memory, and has a first output terminal with a delay time of 263H and a second output terminal with IH.

This field memo! The input signal of J (11) and the output signal of the second output terminal are supplied to an adder (602) and averaged, and the output signal of this adder (602) is multiplied by a coefficient multiplier (603). After that, it is supplied to an adder (604). In addition, field memory (1
The output signal of the first output terminal of 1) is sent to the coefficient multiplier (606).
After being multiplied by (1-K), the signal is supplied to an adder (604).

The values of the coefficient units (603) and (606) are the 10th
Similar to the example shown in the figure, it is generated by a coefficient generator, and its value is changed depending on the magnitude of the motion detection signal.

Field Memo 'J (11) If the human input signal is h1, the output signal of the first output terminal is J, and the output signal of the second output terminal is i, these signals h-j are located at the positions shown in FIG. It becomes a relationship.

In the above configuration, the output signal of the adder (602) field memo! The output signal j of the first output terminal of J (11) becomes an interpolated scanning line signal of the still image portion. Therefore, the adder (604) outputs an interpolated scanning line signal Yc in which the interpolated scanning line signals of the moving image part and the still image part are added at a ratio according to the degree of movement.

The interpolation scanning line is located at the position marked by two in FIG. Further, the input signal Y is output as is as the main scanning line signal Ym.

In this way, according to this example, a 3-port field memory is used and no line memory is required, so the number of circuit patterns on the board can be reduced, the circuit area can be reduced, and the configuration can be made at low cost. .

G2 Description of Second Embodiment (FIG. 2) Next, a second embodiment of the present invention will be described with reference to FIG. This example is also an example applied to a scanning line interpolation circuit for brightness signals, and parts corresponding to those in the example in FIG. 10 are denoted by the same reference numerals.

In the figure, the luminance signal Y is supplied to a field memory (12) that constitutes a delay line. This field memory (12) is composed of a so-called 3-port field memory, with a first output terminal having a delay time of 263H and a first output terminal having a delay time of 263H.
and a second output terminal of H.

The output signals of the first and second output terminals of this field memo IJ (12) are supplied to an adder (602) and averaged, and the output signal of this adder (602) is sent to a coefficient multiplier (603). ) is doubled and then supplied to the adder (604). In addition, the human input signal in the field memory (12) is processed by the coefficient unit (606) (
After being multiplied by 1-K), it is supplied to an adder (604).

The values of the coefficient units (603) and (606) are the 10th
Similar to the example shown in the figure, it is generated by a coefficient generator, and its value is changed depending on the magnitude of the motion detection signal.

FIG. 3 is a diagram showing the scanning line/structure in the time-vertical plane, and Q marks indicate the scanning lines of each field. The input signal of the above-mentioned field memo 'J (12) is h', the first
Assuming that the output signal of the second output terminal is j/, and the output signal of the second output terminal is 1', these h' to J' have the positional relationship shown in FIG.

In the above configuration, the output signal i"' of the adder (602) becomes the interpolated scanning line signal for the moving image part, and the human input signal h' of the field memo!I (12) becomes the interpolated scanning line signal for the still image part. Therefore, the adder (604)
, outputs an interpolated scanning line signal Yc in which the interpolated scanning line signals of the moving image portion and the still image portion are added at a ratio corresponding to the degree of movement. The interpolated scanning line is shown in Figure 3! 1. It is considered to be the position of the mark. Moreover, the output signal of the second output terminal is
It is output as is as the main scanning line signal Ym.

In this way, also in this example, a 3-port field memory is used and no line memory is required, so that the same effects as in the example of FIG. 1 can be obtained.

G. Description of Third Embodiment (FIGS. 4 and 5) Next, a third embodiment of the present invention will be described with reference to FIGS. 4 to 7.

FIG. 4 shows the configuration of an example of a television receiver.

In the same figure, the video signal from the input terminal [1] is a Y
The signal is supplied to the /C separation circuit (2) and separated into a luminance signal Y and a color signal C.

The luminance signal Y output from the Y/C separation circuit (2) is A
After being converted into a digital signal by the /D converter (3Y), it is supplied to the signal processing circuit (5Y). The color signal C output from the Y/C separation circuit (2) is sent to the chroma decoder (4).
) for color demodulation. This chroma decoder (4
) red difference signal R-Y and blue difference signal B-Y output from
is converted into a digital signal by an A/D converter (3C) and then supplied to a signal processing circuit (5C) as a time-division signal RY/B-Y.

The signal processing circuits (5Y) and (5C) perform signal processing such as scanning line interpolation.
The double-speed luminance signal and color difference signal output from (5C) are sent to D/A converters (6Y), (6R), and (6), respectively.
B) is used as an analog signal.

(7) is a clock generation circuit, and this generation circuit (7)
A horizontal synchronizing signal HD separated from the video signal is supplied to the generator circuit (7), and a clock CLKH phase-locked to the horizontal synchronizing signal HD is output from this generating circuit (7).

A/D converter (3Y), (3C) to D
The digital processing system up to the /A converters (6Y), (6R), (6B>) is supplied with a clock CL of H from this generation circuit (7).

Double-speed luminance signals and color difference signals output from the D/A converters (6Y), (6R), and (6B) are each supplied to a matrix circuit (8). This matrix circuit (8
) are supplied to the color picture tube (10) via amplifiers (9R), (9G), and (9B), respectively. In (10), non-interlaced scanning display with twice the number of scanning lines is performed.

FIG. 5 shows the configuration of the signal processing circuits (5Y) and (5C). First, the luminance signal system signal processing circuit (5Y) will be explained.

In the figure, a luminance signal Y converted into a digital signal by an A/D converter (3Y) is supplied to a field memory (501Y) forming a delay line. This field memory (501Y) is configured as a so-called 3-port field memory, and has a first output terminal with a delay time of 263H and a second output terminal with a delay time of 262H. The output signal of the first output terminal of this field memory (501Y) is the field memory (502Y) that constitutes the delay line.
Y). This field memo'J (502
The delay time in Y) is 262H. This field memo! The output signal of J (502Y) is the field memo! that constitutes the delay line. J (503Y).

The delay time for this field memo + J (503Y) is
263H.

Field memo! J (501Y) input signal and field memo! The output signal of J (502Y) is sent to the adder (
504Y) and is averaged.
The output signal of 04Y) is converted to 1-K(K
≦1) and then supplied to the adder (511Y). Field memo! The output signals of the first output terminal and second output terminal of J (501Y) are output from the adder (505Y).
The output signal of this adder (505Y) is doubled by a coefficient unit (508Y) and then supplied to an adder (511Y). Field memo IJ (5
01Y)'s first output terminal output signal and field memo! The output signal of J (503Y) is sent to the adder (506Y
) and is averaged by this adder (506Y).
The output signal is multiplied by 1- by a coefficient multiplier (509Y) and then supplied to an adder (512Y).

Field memo! The output signal of the first output terminal of J (501Y) is doubled by a coefficient multiplier (510Y) and then supplied to an adder (512Y).

The values in the coefficient units (507Y) to (510Y) are controlled based on a motion detection signal, which will be described later, and are changed depending on the degree of motion. For example, in a still image portion, K=0, and the maximum value of K is 1.

Field memory (501Y) to (503Y) mentioned above
, adders (504Y) to (506Y), (511Y)
, (512Y), coefficient unit (507Y) ~ (510Y)
A scanning line interpolation circuit (500Y) is configured.

FIG. 6 is a diagram showing the scanning line structure in the time-vertical plane, and O
The marks indicate the scan lines of each field.

Field memo of the above-mentioned scanning line interpolation circuit (500Y)! The input signal of J (501Y) is a, the output signal of its first output terminal is bl, the output signal of its second output terminal is 0
If the output signal of 1 field memory (502Y) is d, and the output signal of 1 field memory (5 (13Y) is e),
These signals a-e have the positional relationship shown in FIG.

In the scanning line interpolation circuit (500Y), the output signal of the first output terminal of the field memory (501Y) becomes the main scanning line signal of the moving image portion, and also serves as the adder (506Y). Therefore, from the adder (512Y), the main scanning line signal Ym, which is obtained by adding the main scanning line signals of the moving image part and the still image part at a ratio according to the degree of movement, is output as the interpolated scanning line signal of the output still image part. At the same time, it becomes an addition line signal. Therefore, the adder (511Y) outputs an interpolated scanning line signal Yc in which the interpolated scanning line signals of the moving image part and the still image part are added at a ratio according to the degree of movement. On the right, the interpolated scanning line is located at the position marked ':] in FIG.

The main scanning line signal Ym and the interpolated scanning line signal Yc outputted from the scanning line interpolation circuit (500Y) in this way are respectively supplied to the time compression circuit (521Y). In this time compression circuit (521Y), the main scanning line signal Ym and the interpolation scanning line signal Yc are each compressed in time by 1/2 and output continuously. In other words, this time compression circuit (521
A double-speed luminance signal is output from Y).

Also, in Figure 5, field memo! J (501
Y) input signal and field memo IJ (502Y)
The output signal is supplied to a subtracter (531A) and subtracted.

The frame difference signal output from this subtracter (531A) is filtered by a low-pass filter (532A) to remove high-frequency noise components and dot interference components, and then passed to an absolute value circuit (532A).
533A) and is converted into an absolute value and supplied to an adder (534). The first output terminal of field memo IJ (501Y) and the output signal of field memo U (503Y) are supplied to a subtracter (531B) and subtracted therefrom. The frame difference signal output from the subtracter (531B) is filtered by a low-pass filter (532B) to remove high-frequency noise components and dot interference components, and then is filtered by an absolute value circuit (53
3B), the signal is converted into an absolute value and then supplied to an adder (534).

Field memory (501Y) to (503Y) mentioned above
, subtractor (531A), (531B), low-pass filter (532A).

(532B), Absolute value circuit (533A)', (533B
), a motion detection circuit (530) with an adder (534)
is configured. In this case, the greater the degree of movement, the greater the output signal of the adder (534).

The output signal of this adder (534) is supplied to a coefficient generator (541) as a motion detection signal. The values of the coefficient units (507Y) to (510Y) described above are generated by this coefficient generator (541), and the values are changed according to the magnitude of the motion detection signal.

Next, the color signal system signal processing circuit (5C) will be explained. This signal processing circuit (5C) is a scanning line interpolation circuit (5C).
00C) and a time compression circuit (521C), and the scanning line interpolation circuit (500C) is composed of the above-mentioned signal processing circuit (521C).
Since the configuration is similar to that of the scanning line interpolation circuit (500Y) of Y), the corresponding parts will be designated by the reference numerals with "C" instead of rYJ, and detailed explanation will be omitted. Note that the values of the coefficient units (507C) to (510C) of this scanning line interpolation circuit (500C) are also generated by the above-mentioned coefficient generator (541).

The field memory (500C) of this scanning line interpolation circuit (500C)
501C) are supplied with time-division signals R-Y/B-Y of the red difference signal RY and the blue difference signal B-Y, which have been converted into digital signals by the A/D converter (3C). Then, from the adder (512C), the main scanning line signal RmYm/B
m -Ym is output, and the adder (511C) outputs an interpolated scanning line signal Rc -Yc/Bc -Yc.

In this way, the main scanning line signal Rm-Ym/Bm-Ym and the interpolated scanning line signal RC-Yc/13c-Yc output from the scanning line interpolation circuit (500C) are respectively supplied to the time compression circuit (521C). . In this time compression circuit (521C), the main scanning line signal Rm -Ym/B
m -Ym and interpolated scanning line signal RC-Yc/Be -Y
c and are compressed in time axis to 1/2 and output continuously.

In this case, the time compression circuit (521C) separately outputs a red difference signal and a blue difference signal. In the end, this time compression circuit (521C) outputs a double-speed color difference signal.

In this case, in the scanning line interpolation circuit (500Y), since it is a static signal, the dot interference component (color signal component) contained in the luminance signal Y is canceled out and removed. Further, since similar processing is performed in the scanning line interpolation circuit (500C), the cross color components included in the time-division signals RY/BY are also canceled out and removed.

That is, the color signal output from the Y/C separation circuit (2) is expressed by the conceptual formula Yn + Co51n27r f 5 (t. Here, YH is the luminance signal component,
,. is the color subcarrier frequency. Therefore, demodulating this color signal results in the following equation.

Color signal xsin2W f5cj = YH0sln2πf sct + C.

Therefore, the cross color component YH-5ln2πf s
et has the same phase as the color signal component and has a phase inversion relationship between frames, so as mentioned above, the scanning line interpolation circuit (
500C) and are removed.

Also, scanning line interpolation circuit (500Y), (500C)
In the still image part, inter-frame addition processing is performed, so noise that exists randomly in the time direction is reduced to 1/
, /2, and the S/N of the luminance signal and color signal increases.

Furthermore, since the motion detection circuit (530) obtains the motion detection signal from the two frame difference signals, it is also possible to detect fast motion between fields (1/60 sec). For example, signals a, b, d, and e, respectively, to E'! , C, D, the subtractor (5
The output signals of 31^) and (531B) are shown in E of the same figure, respectively.

It becomes as shown in F. Therefore, with only the output signal of the subtracter (531A), the portion P is determined to be a still image portion,
Movement between fields cannot be detected. Therefore, even more? By using the output signal of the Ja calculator (531B), the detection signal becomes as shown in G in the figure, and fast movements between fields can also be detected.

In this way, also in this example, the scanning line interpolation circuit (500Y
), (500C) use 3-port field memories (501Y), (501(:), and no line memory is required, so the same effect as in the example of FIG. 1 can be obtained.

G4 Description of Fourth Embodiment (FIG. 8) Next, a fourth embodiment of the present invention will be described with reference to FIG. This example is an example applied to a scanning line interpolation circuit for brightness signals, and parts corresponding to those in the example in FIG. 5 are denoted by the same reference numerals.

In the figure, the luminance signal Y is supplied to a field memory (13) that constitutes a delay line. The delay time in this field memo IJ (13) is 262H. This field memo! The output signal of J (13) is the field memo! which constitutes the delay line. J (14).

This field memory (14) is composed of a so-called 3-port field memory, and has a delay time of 263H.
and a second output terminal of IH. The output signal of the first output terminal of this field memory (14) is transmitted to the field memory (14) constituting the delay line.
5). This field memo! J (15)
The delay time is 263H.

Field memo! J (13) input signal and field memo! The output signal of the first output terminal of j (14) is supplied to the adder (504Y) and averaged, and the output signal of this adder (504Y) is averaged by the coefficient multiplier (507Y).
After being multiplied by -K (K≦1), it is supplied to the adder (511Y).

Field memo! I (13) output signal and field memo! The output signal of the second output terminal of 7 (14) is supplied to the adder (505Y) and averaged, and the output signal of this adder (505Y) is doubled by the coefficient unit (508Y) and then added. is supplied to the container (511Y).

The output signal of the second output terminal of the field memory (14) and the output signal of the field memory (15) are transmitted to the adder (
506Y) and is averaged.
The output signal of 06Y) is multiplied by l − by a coefficient multiplier (509Y) and then supplied to an adder (512Y). Field memo! The output signal of the second output terminal of j, (14) is doubled by the coefficient multiplier (510Y) and then sent to the adder (510Y).
12Y).

The values in the coefficient units (507Y) to (510Y) are generated by a coefficient generator as in the example in FIG. 5, and the values are changed depending on the degree of movement.

Field Memo 'J (13)'s input signal is al its output signal is 01 Field Memo! If the output signal of the first output terminal of J (14) is dl, the output signal of its second output terminal is b1, field memo + the output signal of J (15) is e, these signals a - e are expressed as shown in Fig. 6. The positional relationship is as shown in the figure.

In the above configuration, the output No. 41 of the second output terminal of the field memo IJ (14) becomes the main scanning line signal of the moving image part, and the output signal of the adder (506Y) is also input to the adder (512Y). outputs a main scanning line signal Ym obtained by adding the main scanning line signals of the moving image portion and the still image portion at a ratio corresponding to the degree of movement. This becomes an interpolated scanning line signal and is also applied to an adder (505Y). Therefore, the adder (511Y) outputs an interpolated scanning line signal Yc in which the interpolated scanning line signals of the moving image part and the still image part are added at a ratio according to the degree of movement. Incidentally, the interpolation scanning line is located at the position marked by 2 in FIG.

In this way, also in this example, a 3-port field memory is used and no line memory is required, so that the same effects as in the example of FIG. 1 can be obtained.

H Effects of the Invention According to this invention, a 3-port field memory is used and no line memory is required, so the number of circuit patterns on the board can be reduced, the circuit area can be reduced, and the configuration can be made at a lower cost. .

[BRIEF DESCRIPTION OF THE DRAWINGS] 1rlA is a block diagram showing the first embodiment of the present invention, FIG. 2 is a block diagram showing the second embodiment of the present invention, and FIG. 3 is a scanning diagram of the time-vertical plane. Diagrams showing the line structure, Figures 4 and 5
6 is a diagram showing a scanning line structure in the time-vertical plane, FIG. 7 is an explanatory diagram of a motion detection circuit, and FIG. 8 is a diagram showing a third embodiment of the present invention. FIG. 9 is a block diagram showing an example of a television receiver, and FIGS. 10 and 11 are diagrams for explaining the same. (11) ~ (15), (501Y) ~ (503Y) (
501C) to (503C) are field memories, (50
4Y) ~ (506Y) (504C) ~ (506C) (
511Y) (512Y) (511C) (512C
) (602) (604) is an adder, (507Y) ~
(510Y) (507C) ~ (510C) (603
) (606) is a coefficient unit. Attorney: Fujisada Domatsu Hide Kuma Mori Proceedings Amendment

Claims (1)

[Claims] A three-port field memory having one input terminal and two output terminals is used as a delay line, and the time difference of the signals between the three terminals is set to 1 horizontal period, 262 horizontal periods, and 262 horizontal periods, respectively. 263 horizontal periods, the above two signals with a time difference of 1 horizontal period are added to form a moving image interpolation signal, and one of the above two signals is used for still image interpolation using a signal with a time difference of 263 horizontal periods. An interpolation signal forming circuit characterized by forming a signal.