JPH0231523B2 - - Google Patents
Info
- Publication number
- JPH0231523B2 JPH0231523B2 JP59231547A JP23154784A JPH0231523B2 JP H0231523 B2 JPH0231523 B2 JP H0231523B2 JP 59231547 A JP59231547 A JP 59231547A JP 23154784 A JP23154784 A JP 23154784A JP H0231523 B2 JPH0231523 B2 JP H0231523B2
- Authority
- JP
- Japan
- Prior art keywords
- amplification
- circuit
- inverting amplifier
- voltage
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003321 amplification Effects 0.000 claims description 28
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 28
- 230000000295 complement effect Effects 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 1
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、相補型絶縁ゲート電界効果トランジ
スタから成る半導体集積回路内に構成される電圧
増幅回路に関し、特にチヨツパ型電圧増幅回路に
関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a voltage amplification circuit configured in a semiconductor integrated circuit comprising complementary insulated gate field effect transistors, and particularly relates to a chopper type voltage amplification circuit. .
従来、この種のチヨツパ型電圧増幅回路として
第2図に示すものがある。同図において、1およ
び2はそれぞれの入力端子、3は出力端子、4,
5,6はそれぞれ絶縁ゲート型電界効果トランジ
スタ(以下MOS−FETと略す)で構成されるス
イツチ、7は入力用のコンデンサ、8は相補型
MOS−FETから構成される反転増幅器であり、
この反転増幅器8の入力端子と出力端子との間に
は、前記各スイツチ4,5の動作に関係づけられ
て動作するスイツチ6が挿入されている。ここ
で、反転増幅器8を相補型MOS−FETの回路で
構成した場合、入出力特性は一般に第3図に示す
ようなグラフとなり、その消費電流は第4図に示
すように入力電圧と出力電圧が等しくなる付近で
最大となり、入力電圧が接地電位または電源電位
に近くなると殆んど流れなくなる。
Conventionally, there is a chopper type voltage amplifying circuit of this type as shown in FIG. In the figure, 1 and 2 are the respective input terminals, 3 is the output terminal, 4,
5 and 6 are switches each composed of an insulated gate field effect transistor (hereinafter abbreviated as MOS-FET), 7 is an input capacitor, and 8 is a complementary type.
It is an inverting amplifier composed of MOS-FET,
A switch 6 is inserted between the input terminal and output terminal of the inverting amplifier 8, and operates in conjunction with the operation of the switches 4 and 5. Here, if the inverting amplifier 8 is configured with a complementary MOS-FET circuit, the input/output characteristics will generally be a graph as shown in Figure 3, and the current consumption will be expressed as the input voltage and output voltage as shown in Figure 4. It reaches a maximum when the voltages are equal to each other, and almost no flow occurs when the input voltage approaches the ground potential or power supply potential.
ところが、第2図のチヨツパ型電圧増幅回路で
増幅を行なうには、スイツチ4,5および6を例
えば第5図a,bおよびcに示すようなタイミン
グでそれぞれ導通、遮断させているため、必ず反
転増幅器8の入力電圧が出力電圧と等しくなるタ
イミングが生じることになり、大きな消費電流が
流れる。また、増幅を行なわない時は、スイツチ
4,5および6をどのように操作してもコンデン
サ7に漏れ電流が流れるため、反転増幅器8の入
力電圧を安定に接地電位または電源電位に保つこ
とはできず、大きな消費電流が流れることにな
る。 However, in order to perform amplification with the chopper type voltage amplification circuit shown in FIG. A timing occurs when the input voltage of the inverting amplifier 8 becomes equal to the output voltage, and a large current consumption flows. Furthermore, when no amplification is performed, leakage current flows to capacitor 7 no matter how switches 4, 5, and 6 are operated, so it is impossible to stably maintain the input voltage of inverting amplifier 8 at ground potential or power supply potential. This will result in large current consumption.
〔発明が解決しようとする問題点〕〕
このように従来の回路は、反転増幅器8の入力
電圧を安定に接地電位または電源電位に保つこと
ができないため、増幅を行なわない場合にも大き
な消費電流が流れるという欠点があつた。[Problems to be Solved by the Invention] As described above, the conventional circuit cannot stably maintain the input voltage of the inverting amplifier 8 at the ground potential or power supply potential, and therefore consumes a large amount of current even when no amplification is performed. The problem was that it flowed.
本発明は上記のような従来の欠点を除去するた
めになされたもので、その目的は、簡単な構成に
よつて消費電流を大幅に低減できる電圧増幅回路
を提供することにある。 The present invention has been made to eliminate the above-mentioned drawbacks of the conventional art, and its purpose is to provide a voltage amplification circuit that can significantly reduce current consumption with a simple configuration.
本考案に係る電圧増幅回路は、チヨツパ型電圧
増幅回路を構成する相補型MOS−FETから成る
反転増幅器の入力端子と接地電位または電源電位
のいずれか一方との間に、その通電路を導通、遮
断可能なスイツチ回路を設け、このスイツチ回路
を、増幅を行なう時(増幅時)に遮断させ、かつ
増幅を行なわない時(非増幅時)には導通させる
ようにしたものである。
The voltage amplification circuit according to the present invention conducts the current-carrying path between the input terminal of the inverting amplifier composed of complementary MOS-FETs constituting the chopper voltage amplification circuit and either the ground potential or the power supply potential. A switch circuit that can be cut off is provided, and this switch circuit is cut off when amplification is performed (during amplification), and made conductive when amplification is not performed (during non-amplification).
本発明においては、増幅を行なわない時に反転
増幅器の入力電圧を接地電位または電源電位に安
定に保つことができるので、消費電流を大幅に減
らすことが可能になる。
In the present invention, since the input voltage of the inverting amplifier can be stably maintained at the ground potential or power supply potential when no amplification is performed, current consumption can be significantly reduced.
以下、本発明を図面に示す実施例に基いて説明
する。
Hereinafter, the present invention will be explained based on embodiments shown in the drawings.
第1図は本発明の一実施例によるチヨツパ型電
圧増幅回路の構成図である。ここで第2図との異
なる点は、反転増幅器8の入力端子と接地電位1
0との間にMOS−FETで構成されるスイツチ9
を回路素子として設け、このスイツチ9を増幅時
に遮断させ、かつ非増幅時には導通させることに
より、反転増幅器8の入力電圧を接地電位に保つ
ようにしたことである。なお、第1図において第
2図と同一部分は同一符号を付している。 FIG. 1 is a block diagram of a chopper type voltage amplification circuit according to an embodiment of the present invention. Here, the difference from FIG. 2 is that the input terminal of the inverting amplifier 8 and the ground potential 1
Switch 9 composed of MOS-FET between
is provided as a circuit element, and the input voltage of the inverting amplifier 8 is maintained at the ground potential by turning off the switch 9 during amplification and making it conductive when not amplifying. In FIG. 1, the same parts as in FIG. 2 are given the same reference numerals.
上記実施例構成のチヨツパ型電圧増幅回路によ
ると、増幅を行なう場合は、常にスイツチ9は遮
断されており、スイツチ4,5および6は上記し
た従来の回路と同様に第5図に示すごときタイミ
ングで導通、遮断する。従つて、この時の動作は
従来の回路と何ら変わるところはない。次に、増
幅を行なわない時には、スイツチ4と5のいずれ
か一方または両方を遮断し、かつスイツチ6も遮
断して、スイツチ9を導通させる。この状態で
は、反転増幅器8の出力は、いずれにも接続され
ず、また入力電圧は接地電位に完全に等しくな
る。従つて、反転増幅器8の消費電流は第4図の
グラフから明らかなように殆んど流れず、また回
路のいずれにも電源電位と接地電位の間に直流が
流れる通路はない。すなわち、この実施例の増幅
回路は増幅を行なわない場合の消費電流は殆んど
流れないようにすることが可能になる。 According to the chopper type voltage amplification circuit configured in the above embodiment, when amplification is performed, switch 9 is always cut off, and switches 4, 5, and 6 are operated at the timing shown in FIG. 5, as in the conventional circuit described above. Continuity and interruption. Therefore, the operation at this time is no different from the conventional circuit. Next, when amplification is not performed, one or both of switches 4 and 5 are cut off, switch 6 is also cut off, and switch 9 is made conductive. In this state, the output of the inverting amplifier 8 is not connected to anything and the input voltage is completely equal to ground potential. Therefore, as is clear from the graph of FIG. 4, the current consumption of the inverting amplifier 8 is almost negligible, and there is no path in any of the circuits through which direct current flows between the power supply potential and the ground potential. That is, in the amplifier circuit of this embodiment, almost no current consumption can be made to flow when no amplification is performed.
なお、上記実施例では、スイツチ9を接地電位
10との間に設けたが、電源電位との間に設けて
も同様の効果が得られる。また、スイツチ4,5
およびコンデンサ7に対応するものが複数個接続
されていてもよい。 In the above embodiment, the switch 9 is provided between the switch 9 and the ground potential 10, but the same effect can be obtained even if the switch 9 is provided between the switch 9 and the power supply potential. Also, switches 4 and 5
And a plurality of capacitors corresponding to the capacitor 7 may be connected.
以上のように、本発明に係る電圧増幅回路によ
れば、増幅を行なわない時の消費電流を極めて微
小にすることができるので、常時増幅を行なう必
要のないシステムの半導体集積回路に組込んだ場
合、システム全体の消費電流を低減でき、特に電
池で動作させた場合の寿命が延び、高性能化でき
る効果がある。
As described above, according to the voltage amplification circuit of the present invention, the current consumption when no amplification is performed can be made extremely small, so that it can be incorporated into a semiconductor integrated circuit of a system that does not require constant amplification. In this case, the current consumption of the entire system can be reduced, the lifespan of the system can be extended, and the performance can be improved, especially when operated on batteries.
第1図は本発明の一実施例によるチヨツパ形電
圧増幅回路の構成図、第2図は従来例を示すチヨ
ツパ型電圧増幅回路の構成図、第3図は相補型
MOS−FETで構成した反転増幅器の入出力特性
図、第4図はその入力電圧と消費電流の関係を示
す図、第5図は第1図および第2図の回路で増幅
を行なうためにスイツチを導通、遮断させるタイ
ミング図である。
1,2……入力端子、3……出力端子、4,
5,6……スイツチ、7……コンデンサ、8……
反転増幅器、9……スイツチ。
Fig. 1 is a block diagram of a chopper type voltage amplification circuit according to an embodiment of the present invention, Fig. 2 is a block diagram of a chopper type voltage amplification circuit showing a conventional example, and Fig. 3 is a complementary type voltage amplification circuit.
An input/output characteristic diagram of an inverting amplifier composed of MOS-FETs. Figure 4 is a diagram showing the relationship between its input voltage and current consumption. Figure 5 is a diagram showing the relationship between the input voltage and current consumption of the inverting amplifier configured with MOS-FETs. FIG. 1, 2...Input terminal, 3...Output terminal, 4,
5, 6...Switch, 7...Capacitor, 8...
Inverting amplifier, 9...switch.
Claims (1)
成された半導体集積回路において、チヨツパ型電
圧増幅回路を構成する反転増幅器の入力端子と接
地電位または電源電位のいずれか一方との間に、
増幅時に遮断動作しかつ非増幅時には導通動作す
るスイツチ回路を具備したことを特徴とする電圧
増幅回路。1. In a semiconductor integrated circuit composed of complementary insulated gate field effect transistors, between the input terminal of an inverting amplifier constituting a chopper voltage amplifier circuit and either ground potential or power supply potential,
1. A voltage amplification circuit characterized by comprising a switch circuit that operates to cut off during amplification and to conduct when not amplified.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59231547A JPS61109308A (en) | 1984-11-02 | 1984-11-02 | Voltage amplifier circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59231547A JPS61109308A (en) | 1984-11-02 | 1984-11-02 | Voltage amplifier circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61109308A JPS61109308A (en) | 1986-05-27 |
JPH0231523B2 true JPH0231523B2 (en) | 1990-07-13 |
Family
ID=16925201
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59231547A Granted JPS61109308A (en) | 1984-11-02 | 1984-11-02 | Voltage amplifier circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61109308A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57142032A (en) * | 1981-02-27 | 1982-09-02 | Toshiba Corp | Self substrate bias circuit |
JPS57202118A (en) * | 1981-06-08 | 1982-12-10 | Nippon Denso Co Ltd | Chopper type mos comparator |
JPS6146614A (en) * | 1984-08-13 | 1986-03-06 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1984
- 1984-11-02 JP JP59231547A patent/JPS61109308A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57142032A (en) * | 1981-02-27 | 1982-09-02 | Toshiba Corp | Self substrate bias circuit |
JPS57202118A (en) * | 1981-06-08 | 1982-12-10 | Nippon Denso Co Ltd | Chopper type mos comparator |
JPS6146614A (en) * | 1984-08-13 | 1986-03-06 | Hitachi Ltd | Semiconductor integrated circuit device |
Also Published As
Publication number | Publication date |
---|---|
JPS61109308A (en) | 1986-05-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |