JPH02310587A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To effectively constitute a system with plural types of velocity environment by constituting plural circuit blocks composing identical functions by means of circuit structure which differs for each block. CONSTITUTION:An n high speed side circuit blocks 1-1 to 1-n (first circuit blocks) possessing ECL (emitter logic) type circuit structures respectively and an n' low speed side circuit blocks 1-1' to 1-n' (second circuit blocks) possessing Bi-CMOS (bipolar/CMOS compound logic) type circuit structures are integrated and formed in an identical semiconductor substrate (SUB). Thus the first circuit blocks are constituted of the circuit structures suitable for speed heightening and the second circuit blocks are constituted of the circuit structures suitable for low power consumption and high integration. Thus the system with plural types of velocity environment is effectively constituted.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having multiple operating speeds and a system using the same, and in particular to a multi-board memory used in image processing technology and a system using the same. Related to techniques effective for use in the image processing system used [Prior art] Generally, integrated circuit devices for digital signal processing are classified into series according to their operating speeds.

When creating one system, various actual product circuits within a series with the same operating speed are organically combined,
The entire system is configured.

For example, multi port random, access memory (multi port random acc
essmemory (hereinafter also abbreviated as multi-board RAM) has multiple word lines and multiple data lines connected to each memory cell in order to have multiple input/output terminals (input/output ports) in one memory cell. .

For example, in order to provide a static memory cell with two input/output ports, two word lines and two pairs of complementary data lines are connected to one memory cell. Two systems of decoder circuits and two systems of read/write circuits are provided within the memory device in order to independently perform a write operation and a read operation for each input/output boat. These two systems of decoder circuits and read/write circuits are constructed in circuit formats having similar operating speeds. In other words, both of these two circuits are CMOS
(Complementary MO8: O8: Complementary Oxide Semiconductor Complementary M
etal Oxide Sem1conductor
) consists of circuits.

color palette LSI with built-in dual-port memory (large scale semiconductor integrated circuit device: large-
scale semiconductor
rated circuit devices), these two circuits are products consisting only of 0M08 circuits and ECL (emitter coupled logic).
c) Two types of products are available: one consisting only of circuits. Then, depending on the operating speed of the image processing system to be formed, the above two types of color palettes) LSI
are used differently.

Regarding dual port memory, Japanese Patent Application Laid-Open No. 62-4
3888 etc.

[Problem to be solved by the invention]

However, the present inventors have found that the above-mentioned technique has the following problems.

In other words, since conventional semiconductor integrated circuit devices are formed with the assumption that they will be used in a single speed environment, there is a problem in that it is not possible to efficiently configure systems or devices that have multiple speed environments. there were.

For example, a cathode ray tube controller (c-athode ray tube controller) using multi-boat R, AM
tube controller: In the case of CRTC or Cl1 (hereinafter abbreviated as IT=r controller), the memory image stored in the multi-board RAM is transferred to the cathode, ray,
The reading operation (display operation) for displaying on a cathod ray tube (hereinafter abbreviated as CRT) must be performed at high speed in order to synchronize with the display speed of the CRT. However, multi-boat RA
The rewriting operation (drawing operation) of the memory image stored in M is performed by C.
Since it is not necessary to synchronize with the display speed of RT, it may be performed at a relatively low speed. Even in such a case, the conventional multi-board RAM was configured entirely to match the maximum operating speed.9 In other words, the conventional multi-board RAM
Both the circuits used for read operations that require high speeds and the circuits used for rewrite operations that do not necessarily require high speeds, are typically constructed in a circuit format suitable for high speed operations. As a result, conventional multi-board RAMs have been forced to suffer disadvantages such as increased power consumption and reduced integration scale in exchange for increased speed.

In a system or device that requires high-speed operation, there are very few cases in which the need for high-speed operation extends to all circuits, and only the main circuit part or a part of the circuit is formed to be capable of high-speed operation. The inventor's studies have revealed that there are many cases where this is the case.

An object of the present invention is to efficiently configure a semiconductor integrated circuit device having multiple speed environments and a system using the same.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A summary of typical inventions disclosed in this application is as follows.

That is, one semiconductor integrated circuit device includes a plurality of first and second circuit blocks constituting the same type of function, and the circuit formats of the first and second circuit blocks constituting the same type of function are mutually mutual between the blocks. be made different.

[Effect]

According to the above means, among circuit blocks having the same type of function, the first circuit block that requires high-speed operation has a circuit structure suitable for high-speed operation, and the second circuit block that does not necessarily require high-speed operation has a low power consumption. It also has a circuit structure suitable for high integration.

As a result, a semiconductor integrated circuit device having multiple speed environments and a system using the same can be efficiently configured.

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

In addition, in the figures, the same reference numerals indicate the same or corresponding parts. .

FIG. 1 shows a schematic configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention.

The semiconductor integrated circuit device engineer C1 shown in the same figure is
n high-speed side circuit blocks 1-1 to 1-n (first circuit blocks) having a CL (emitter logic) type circuit structure;
The n° low-speed circuit blocks l-1 to 1-nl (second circuit blocks), each having a Bi-0MO8 (bipolar/CMO, S complex logic) type circuit structure, are on the same semiconductor substrate (SUB). It is formed in an integrated manner. The input signals IN and IN' are divided into those that require high-speed processing and those that do not, and are sent to each circuit block l-
It is input to the input terminals of 1-1-n, 1-1'-, and 1-n'. Input signals IN that require high-speed processing are input to high-speed side circuit blocks 1-1 to 1-n, and input signals IN' that do not require high-speed processing are input to low-speed side circuit blocks 1-1'' to 1-1.
-n'.

- Also, the output signals OUT processed at high speed by the high-speed side circuit blocks 1-1 to 1-n1c and the low-speed side circuit block 1-
The output signals OUT' processed at low speed in steps 1' to 1-n' are respectively outputted to the outside from external terminals of the semiconductor substrate integrated circuit device 1tIc1.

Here, the above two types of circuit blocks 1-1 to 1-
Although n and 1-1'' to 1-n' have different circuit structures that determine their operating speeds, the corresponding symbols are considered to have the same or similar functions.

For example, the circuit units constituting the low-speed side circuit blocks 1-1' to 1-n' are as shown in FIG.
An L (bipolar/CMOS complex logic) circuit is used. The BCL circuit shown in the figure is also called a Bi-0M08 circuit, and has an input logic section composed of a low power consumption 0M08 circuit including p-channel MOS transistors Mpl, Mp2 and n-channel MOS transistors Mfll to Mr15, and a power supply voltage It includes an output section composed of NPN bipolar transistors Qn 1 +Qn 2 having a large current driving ability and connected in a toten ball manner between Vcc and ground potential GND. Although the BCL circuit is inferior to the ECL circuit described later in terms of high speed, it has characteristics far superior to the ECL circuit in terms of low power consumption and suitability for high integration.

Note that the Bi-0M08 circuit shown in the figure forms a two-manpower NOR circuit. Vcc and GND are the positive power supply potential and ground potential (sV and Ov or OV and -5,2V), A
'ToB'& indicates logic input, and O' indicates logic output.

Further, the circuit units constituting the high-speed side circuit blocks 1-1 to 1-n are, for example, ECs as shown in FIG.
An L (emitter coupled logic) circuit is used. The ECL circuit shown in the figure operates in an unsaturated state while passing a relatively large operating current through the bipolar transistors Qn3 to Qn5 for current switches, so although there is a problem in that the power consumption increases, it is extremely Can operate at high speed. Note that the ECL circuit shown in the figure forms a two-manpower NOR. GND is the ground potential (0■) serving as a high level reference, and VILH is the negative TIt source potential (-5, 2
■), A and B are logic inputs, 0 is logic output, ' L 1
+RL2 is a load resistance, Qn6 is an NPN output bipolar transistor, and Qn7 has a reference potential Vcc at its base.
Bipolar transistor for current source receiving current, ltl,)
t2 and R3 each represent resistance. Further provided is a reference potential VI3B generation circuit formed from an NPN bipolar transistor Qn8, resistors R4 to R6, and diodes DI and D2. Incidentally, since the operation of this ECL circuit is well known, the explanation thereof will be omitted.

FIGS. 4 and 5 show other examples of combinations of low-speed circuit blocks and high-speed circuit blocks formed within the same semiconductor integrated circuit device.

That is, the circuit units forming the low-speed side circuit blocks 1-1' to 1-n' include pure CMOS logic circuits as shown in FIG. 4, for example.

This pure CMOS circuit is a two-way NOR circuit, and as shown in the figure, p-channel MO8FETMp3. Mp4 and N channel MO8FET? Contains vIn 6 and Mn7. Since the operation of this 0M08 circuit is well known, its explanation will be omitted. Further, the circuit units constituting the high-speed side circuit blocks 1-1 to 1-n include, for example, a TTL circuit as shown in FIG. 5. This TTL circuit consists of PNP type input bipolar transistors Qpl and Qp2, and an npn bipolar transistor for phase gater Qn9.
and QnlO1 output transistors Qn 11 and Qr
l12, diodes D3 to D5, and resistors R7 to all
including.

Incidentally, since the operation of the TTL circuit described above is well known, the explanation thereof will be omitted.

As described above, a plurality of circuit blocks having the same type of function are formed in the same semiconductor integrated circuit device, and the circuit structures of the circuit units forming each circuit block are made different between the blocks.

That is, circuit blocks that require high-speed operation should have a circuit structure suitable for high-speed operation, and circuit blocks that do not necessarily require high-speed operation should have a circuit structure that is suitable for low power consumption and high integration.

This makes it possible to efficiently configure a system or device that has multiple speed environments, and to optimize the configuration of a system or device that requires high speed.

Next, a case where the present invention is applied to a color palette LSI will be described.

First, an image processing system incorporating a color palette LSI will be explained using FIG. This image processing system consists of a microprocessor unit (m1cropr
(hereinafter referred to as MPU) 6-5
°, graphic controller (graphic c
controller) 6-5a, multiple video memories or 7L/-memories.

frame buffer mem
ory) 6-5b, color palette (color p
alette ) or color lookup table (c
color 1lookup table) CPLT
and an analog car y-CRT display 6-8. MPU 6-5° connects the graphic controller 6-53 and color palette CPLT to the data bus DB.
and a graphics controller 6-5a and a color palette C.
Controls the operation of the PLT.

The graphic controller/F6-5a is a raster scan type Advanced C released by Hitachi.
RT: r controller (Advanced CRT)
Controller: A CRT controller with a graphic drawing and display function, such as AC TC) HD63484, can be used. That is, in the case of a display operation in which image data already stored in the video memory 6-5b is displayed on the CRT display, the graphic controller 6-5b displays the video memo 1J6-5b in synchronization with the display timing of the CRT display. Generates a display address for access (display access). Furthermore, in the case of a drawing operation that rewrites image data already stored in the video memory 6-5b, the graphic controller 6-5a identifies the drawing command supplied from the MPU 6-5° and accesses the video memo 1J6-5b. (Drawing access) Generates a drawing address to be used. In the case of this drawing operation, the graphic controller 6-5b performs a read operation of image data stored in the video memo 'J 6-5b or a video memo IJ 6-5
Both the write operation of the image data to be written in b can be performed.

The graphics controller 6-58 also provides a horizontal synchronization signal (H8YNC) and a vertical synchronization signal (V8YNC) required for displaying graphics on the CRT display 6-8.
It constantly generates various display synchronization signals such as a horizontal/vertical synchronization signal (SYNC) (hereinafter referred to as horizontal/vertical synchronization signal (SYNC)) and a display timing clock DISP (not shown).

The above and Deomemo') 6-5b are, for example, 64Kwo
It is constructed by using two high-speed semiconductor memories of rdX4bit configuration. Therefore, the video memory 6-5b is connected to the graphics controller 6-5.
8-bit pixel data is output according to one display address supplied from a.

The color palette CPLT receives 8-bit pixel data (display data) output from the video memory 6-5b at pixel data input terminals PO to P7, and converts the color data at the address corresponding to the 8-bit pixel data into an analog color. Output from signal output terminals R0G and B. That is,
The video memory 6-5b stores address data for accessing the memory array provided in the color palette CPLT as pixel data. As understood from the above, the color palette CPLT holds (2')=256 words of data therein, so the analog CRT display 6-8
The CR and T screens of the 2015 can display 256 colors at the same time. Each of the 256 words of color data consists of 12 bits of digital color information including 4 bits of red, 4 bits of green, and 4 bits of background information. Therefore, when pixel data from the video memory is input to the color palette CPLT, the 12-bit digital color information stored at the address according to the pixel data is read out, as well as the 4-bit red color information.

Each of the green and back information is converted from a digital signal to an analog signal by a corresponding digital-to-analog converter in the color palette CPLT, and is outputted from analog color signal output terminals R, G, and B. .

T output from analog color signal output terminals R, G and B
The TL level analog color signals AR, AG and AB are supplied to the CRT of an analog CRT display 6-8.

If the display screen of the analog CRT display 6-8 includes, for example, 400 scans m (rasters) each consisting of 640 dots, the color palette (CPLT) is adjusted to display one dot on the display screen. On the other hand, the analog color signals AR, AG and AB are outputted once. Therefore, the above analog color signal A of color palette) CPLT
The output operations of R, AG and AB are performed on the CRT display 6.
-8 is synchronized with the display timing. Ie the video memo above! J6-5b is accessed for display by the graphic controller 6-5b in synchronization with the display timing of the analog CR, T display 6-8, and in synchronization with the display timing,
Supply pixel data to color palette CPLT. The color palette CPLT then supplies the analog color signals AR, AG, and AB to the display 6-8 in synchronization with the display timing.

The horizontal display time and vertical display time of the analog CRT display 6-8 are 30.4 μS and 16.5 μS, respectively.
If the area is 11m5, the display time of one dot is 30.4
μs ÷ 640 dots = 47.5 ns = 21,05 MH
z, a 21.05 MHz dot clock is input from an oscillation circuit (not shown) to the dot clock terminal DOTCK of the color palette CPLT. Also, the horizontal/
Vertical synchronization signal 5YNC is supplied to synchronization signal terminal 8YNC of color palette CPLT. Therefore, the analog color signals AJAG and AB are the synchronization signal 5YNC.
and CRT display 6- in synchronization with the dot clock.
8. The display access operation speed of the color palette CPTL is, for example, 80-150 MHz.

On the other hand, the color palette CPTL is capable of converting digital color information stored therein in response to instructions from the MPU 6-5''.

In other words, this color palette CPLT has 2 colors as described above.
Although the color information of 56 colors is stored, the color information of the 256 colors is selected from among 4096 (212) colors by the MPU6-
5'. Therefore, M.P.
U6-5' executes rewriting of the 12-bit digital color information in the color palette CPLT as necessary. The color information changing operation does not need to be synchronized with the display time of the CRT display 6-8, and may be synchronized with the operating speed of the MPU 6-5', for example, 1 to 10 MHz. This color information rewriting operation is performed by transmitting the register selection signal, read control signal, write control signal, chip select signal supplied from the MPU 6-5', and the rewriting address and rewriting color data supplied via the data bus DB to external terminals, respectively.几So
, R8I, WR.

It is executed by receiving RD, C8 and Do-D7.

As understood from the above, in the image processing (graphic processing) system shown in FIG.
' is a low-speed external operation system, and the graphic controller 6-5a and video memory 6-5b are used as a high-speed external operation system 6-5.

FIG. 7 shows a block diagram of the color palette CPLT shown in FIG.

Color palette CPLT includes a memory array 6-1 for storing digital color information.

The memory array 6-1 has, for example, 256 words x
An address latch circuit (AD-LATCH) that includes a 12-bit dual port memory cell and latches 8-bit pixel data supplied from the pixel data input terminals PO to P7 in synchronization with the clock signal CLK.
A pixel data decoding circuit (P-DEC) decodes the output signal of 6-3 and selects a plurality of memory cells (12 pieces) according to the above-mentioned pixel data. A rewriting address decoding circuit D-DEC6-4 decodes the 8-bit rewriting address supplied to the address register 6-3' through the 7A I10 and selects a plurality of memory cells (12 pieces) according to the rewriting address. ° and can be accessed from both.

The digital color data stored in the plurality of memory cells selected by the pixel data decoder 6-4 is read out by the sense circuit P-8NS6-6, and in synchronization with the clock signal CLK, the digital color data is read out by the sense circuit P-8NS6-6.
It is held in the latch circuit in NS6-6. Then, 4 bits are supplied to each of the latched color terminals, and converted into analog color signals AR, AB, and AG. supplied to

On the other hand, data can be written to and read from the 12 memory cells selected by the decoder circuit D-DEC6-4'. In the case of data write (rewrite) operation,
The color data to be written into the memory cells is sent to the MPU.
It is output from 6-5° and connected to registers R, -RE via external terminals DO to D7 and the above input/output/(Tuffa I10).
G.

Four bits are stored in each register of G-BEG and B-REG. Then the register R-.

The data held in G- and B-REG is written into the selected memory cell by the write amplifier WA, which is activated in response to the low level of the write pulse signal "W". In the case of a read operation, the data stored in the selected memory cell is transferred to the sense amplifier D-
The signal is amplified by the 8NS6-6' and supplied to the data input/output terminals DO to D7 via the data multiplexer D-MPX and the input/output buffer 10.

The control circuit C0NT includes a chip select signal C8, a read control signal n, a write control signal n, and a register selection signal)
Based on LSO and R81, internal register selection signal R
8S, an internal read control signal R, a multiplexer control signal MPXC1 output enable signal OE, and a write pulse φWR are generated.
Internal clock signals CLK and CLK are generated based on the dot clock DOTCK and synchronization signal 5YNC.

The data multiplexer D-MPX responds to the high level of the multiplexer control signal MPXC,
The input/output buffer I10 outputs the supplied 12-bit data in response to the low level of the output enable signal OE. It is considered as a buffer circuit,
It is set as an input buffer circuit in response to the high level of the output enable signal OE.

The internal register selection signal R8S is used as a register selection signal for the address register (ADD-REG) 6-3' and the rewriting data registers R-, G-, and B-REG. When the rewriting address signal is input from the input/output buffer I10, the internal register selection signal R8
The above address register (ADD-REG) 6 is set by S.
−3° is the selected state. When the R, G, and B color data to be rewritten from the input/output buffer I10 is supplied in a time-division manner in 4 bits each, the internal register selection signal R8
By S, three rewrite data registers, R-I(,E
G, G-REG and B-REG are selected one after another, and the desired color data is stored in their data registers R.
-, G-, and B-REG.

FIG. 8 shows a part of the memory array 6-1 shown in FIG. 7, a pixel data decoder 6-2, a rewrite address decoder 6-2°, and a sense circuit (P-8NS).

D-8NS) 6-6 and 6-6', and light amplifier W
It shows A. Note that this figure shows a portion corresponding to one bit of the 12-bit color data. It should be noted that in reality, there are 11 sets of decoder circuits 6-4 and other parts excluding 6-4°.

1 memory unit) MU is 256 memory cells MCO
~MC255, word line WO~W64゜WO'-W64
' and complementary data line pair DO, DO.

DO', Do'~D3. D3. Contains D3' and D3'. Each memory cell is connected to two word lines and two pairs of complementary data lines to form a pool port memory cell. For example, the memory cell MCO is connected to the first word #JWQ coupled to the pixel data decoder 6-2.
It is coupled to a second word line WO' coupled to a rewriting address decoder 6-2', a first complementary data line pair Do, Do, and a second complementary data line pair DO°, DOo. Similarly, corresponding first and second word lines and first and WJ2 complementary data line pairs are coupled to other memory cells.

N-channel load MO8FET'r□,'r□,TQ
・.

A respective source-drain path is coupled to a terminal Vcc to which a first operating voltage (K) is supplied, and a respective gate electrode is coupled to said terminal Vcc to bias each complementary data line.

The first common data pair CDLO, CDLO is a column switch N-channel MO8FET pair CSO.

The first complementary data line pair Do, Do-D3, D3 is connected via the source-drain path of C8O-C83, C83.
is combined with

The second common data line pair CDLO°, CDLO' is a column switch N-channel MO8FET pair C8Q'.

The second complementary data line pair Do' is connected to the second complementary data line pair Do' through the source-drain path C8o° to C83' and 083'.

Do' to D3' and D3' are combined.

The first sense amplifier (P-8NS) 6-6 has a base electrode corresponding to the first common data line pair CDLO.
, CDLO, and a pair of differential NPN bipolar transistors D with their respective emitter electrodes commonly coupled.
Q1. DQ2. The above differential bipolar transistor DQI
, a current source MO8F' that supplies its operating current to DQ2.
ETC8MI and the above differential bipolar transistor DQ
l , main amplifier MA coupled to the collector of DQ2
Contains I. The source/drain path of the current source MO8FETC8MI is a bipolar transistor DQI.

It is coupled between the common emitter of DQ2 and the GND terminal to which the circuit ground potential (second operating potential) is supplied, and its gate electrode is supplied with a voltage Vcs to always keep MO8F'ETC8MI in the on state. Ru.

Therefore, the first sense amplifier (P-8NS) 6-6
By being always in an active state, it is possible to perform high-speed reading.

The bias circuit BC connects the first common data line pair CDLO.

CDLOK coupling, which always biases it to a predetermined potential and enables high-speed reading. The bias circuit BC is an N-channel MO8FETQBI whose respective gate electrodes are connected to the vcc terminal.

QB2. Consists of QB3 and QB4.

Each of the MO8FETs QB1 and QB3 is a first common data line pair CDLO corresponding to a terminal VCDB to which a common data line bias potential is supplied.

CDLO, and each of the MO8FETs QB2 and QB4 is provided between the corresponding first common data line pair CD
Lo, is provided between CDLo and the ground terminal GND. The common data line potential supplied to the terminal VCDB is the potential of the first common data line pair CDLO, CDLO biased by the bias circuit BC, that is, the potential of the differential bipolar transistors DQ1. The base potential of DQ2 is determined to be lower than the collector potential of each differential bipolar transistor in the standby state. Therefore, the differential bipolar transistor DQI
, DQ2 are devised so as not to operate in saturation.

The second sense amplifier 6-6' is the first sense amplifier 6-6.
Similarly, it includes differential NPN bipolar transistors DQ3 and DQ4, a current source N-channel MO8FET C3M2, and a main amplifier MA2.

The difference from the first sense amplifier 6-6 is that the source drain bust is connected between the Vcs terminal and the gate electrode of the current source MO8FET C3M2, and the gate electrode is connected to receive the internal read control signal R. A switching N, MO8FET SW having the following characteristics is provided. Therefore, the second sequence is kept in operation only during the read period when the internal read control signal R is at a high level, thereby preventing an increase in power consumption.

When reading data stored in memory cells according to pixel data, the pixel data decoder (P-DE
C) 6-4 is an address latch circuit (ADD-LATC
H) Internal complementary address signal pdo supplied from 6-3
, pdo to pd7. J) Decode d7 and write any one of the first word, IJWO-w53, for example, word line w
□ is the selection level, and the first column selection line Yo
-Y3, for example, the column selection line YO is set to the selection level. Depending on the selection level of word line WQ,
When the memory cell MCO is brought into a selected state, the first complementary data lines Do,
The potential of Do is changed. On the other hand, depending on the selection level of the column selection line YO, the column switch MO8FETC8Q
and σ101 are turned on, and the first complementary data line DQ
, DQ are transmitted to the first common data line pair CDLQ and CDLO. As a result, the differential bipolar transistor DQ1. DQ2 detects the potential change of its base electrode and supplies a detection output to the main amplifier MAI. The main amplifier MAI supplies read data RDO corresponding to the data stored in the memory cell MCO to its output.

On the other hand, when selecting a memory cell according to the address signal stored in the address register (ADD-REG) 6-3', the address decoder (D-DEC) receives the internal address signal supplied from the address register 6-3'. a
one second word line decoding d O-a d 7 and following said internal address signal a d O-a d 7;
For example, the second word line WO and the second column selection line YQ'
~Y3', for example, the second column selection line Y3
By setting K to the selection level, respectively, the memory cell MC3 is brought into the selected state. When reading data from the selected memory cell MC3, the data of the memory cell MC3 is transferred to the second complementary data line pair D3', D3.
' , column switch MO8FET turned ON
C83', source drain bus of C8a', second
Common f-evening line pair CD L O'.

Through CDLO', differential bipolar transistor DQ
3, transmitted to the base of DQ4. In the case of a read operation, a high level internal read control signal R is sent to the switch MO.
Since it is supplied to the gate of 8FET 8W, the current source MO
8FETC8M2 is a differential bipolar transistor DQ3
, DQ4, the differential bipolar transistors DQ3, DQ
4 detects the potential change of the base and connects the main amplifier MA.
The detection output is supplied to the input of 2. In response, main amplifier MA2 supplies read data RDQ' corresponding to the data stored in the memory cell MC3 from its output. On the other hand, the memory cell MC brought into the selected state
When the data of 3 is rewritten, the memory cell MC
The data RWo to be stored in the write amplifier WA activated by the write pulse φWR is
Accordingly, the second common data line pair CDLO', C1) LO
transmitted to o. Therefore, the potential of the second common data line pair CDLO', CDLO' is the same as the potential of the second common data line pair CDLO', CDLO'.
It is set to high level and low level or low level and high level corresponding to O. Said second common data line pair CD
The potential difference between LO' and CDLO' is the source/drain path of the column switch MO8F'ET C83', C83', and the second complementary data line pair D3'.

D3'' is transmitted to the memory cell MC3.

As a result, the data corresponding to the above data RWOK becomes
It is stored in the memory cell MC3.

That is, the data in memory cell MC3 is rewritten.

FIG. 9(5) shows the pixel data decoder (p-D
EC) 6-4 shows a partial circuit diagram.

As can be understood from the figure, the illustrated circuit corresponds to a column decoder that drives the column switch selection lines YO, Yl, Y2, and Y3. In the figure, the logic circuit symbol whose output stage is marked with a black mark is a bipolar CMOS circuit BCL. FIG. 9(B) shows the logic symbol and equivalent circuit diagram of the bipolar 0MO8 type two-man power NAND circuit that constitutes the column decoder. As seen from FIG. 9(5), the column decoder is as follows: 12 bipolar CMOS circuits BCLO to BCL
Contains I1. 8 bipolar CMOS circuits BCL
An address latch circuit (ADD) is connected to the inputs of O to BCL8.
-LATCH) internal complementary address signal p supplied from
do, pdQ to pd3. pd3 is applied. Each bipolar 0M08 circuit consists of a Kp channel MO8FET MP20.MP21.N channel MO8FET Mn20-Mn24 and a pair of output NPN bipolar transistors Qn10, Qn as shown in FIG. 9 (E9).
It consists of 11 parts. The row decoder of the pixel data decoder (P-DEC) 6-4 (not shown) is also configured by a bipolar 0M08 circuit.In this way, the high-speed side peripheral circuit 6-4 has circuit units that are bipolar components. It is constituted by a CMOS composite type logic circuit, that is, a Bi-cMOS logic circuit BCL.

FIG. 10 (5) shows the address decoder (D-DEC).
) shows a circuit diagram of a part of 6-4°.

The illustrated circuit is the column switch selection line YO'.

This corresponds to a column decoder that drives Yl', Y2', and Y3'. This column decoder has internal complementary addresses ado, ado-ad3 . 8 CMOS type NAND circuits receiving ad3 CMOS゜~CMOS7
and the above CMOS type O8 power NAND circuit CMOSO-0
4 CMOS type O8 power NAN receiving the output of MO87
Includes D circuits CMOS8 to CMOS11. No. 101)
shows the logic circuit symbol of the CMOS type O8 NAND circuit and its corresponding equivalent circuit diagram. In this way, the CMOS type O8 power NAND circuit is
FETMI)30. Mp31. and NMO8FETMn
30. It is composed of Mn31. The row decoder of the address decoder (D-DEC) 6-4', which is not shown, is also constructed of a CMOS logic circuit in the same manner as described above. In this way, the low-speed side peripheral circuit 6-4' has its component circuit units constructed from pure CMOS type logic circuits.

FIG. 11 shows a specific circuit configuration of one of the memory cells MCO to MC2550.

As shown in the figure, the static type memory cell MC is
n-channel MO8) transistor M n 10 + Mn
11 and a load resistor RIO made of polysilicon.

Two sets of transfer gate MOS transistors Mn 12 are provided for one holding circuit section formed by R11.

It has Mn13, Mn12', and Mn13'. One transfer gate MO8) transistor M n12,
Mn13 is controlled on/off via the word mW on the high speed side. This transfer gate MOS transistor M
n12. Via Mn13 and high speed side data #JD,
Reading/writing of stored data is performed. In addition, the other transfer gate MO8) transistor Mn12'
+Mn 13' is controlled on/off via the low-speed side word line W'. Reading/writing of stored data is performed via transfer gate MOS transistors Mn 12', Mn 13' and low-speed side data line D'.

Note that the load resistance R of the memory cell shown in the same figure has a high resistance value.
1O and R11 may be changed to p-channel MO8FETs. In that case, the memory cell MC is a general CMOS
Type static memory cell.

FIG. 12 shows the main amplifier MA1 of FIG.
Figure 3 shows the main amplifier MAI'.

As shown in FIG. 12, the main amplifier MA1 includes NMO8FETM100-M2O3 for a constant voltage i source, and a constant voltage Vcs is applied to their gates.

be done. The emitters of each of the grounded space transistors BQ and Bl are connected to the differential bipolar transistor DQI.
, DQ2 are connected to each other, and the detection outputs supplied from the collectors C1 and C1 are amplified. Between the collectors of the transistors Bo and Bl and the Vcc terminal, a load MO8FETM107. M108. and diode-connected bipolar transistors B3 and B4 for level clamping are connected in parallel. A diode-connected bipolar transistor B2 is also connected between the common space of the transistors BO and Bl and the Vcc terminal.
are provided, and differential bipolar transistors DQ1 . DQ
The potential of collector CI2 and CI is clamped to the value of VCCT2VBE. Therefore, the bias circuit BC and the bipolar transistors BO, Bl, and B2 prevent saturation of the differential bipolar transistors DQI and DQ2. The collectors of bipolar transistors Bo and Bl are each emitter follower transistor B5
゜It is input to the pace of B6. The outputs of the emitter follower transistors B5, B5 are input to the launch circuit. The latch circuit is made of bipolar transistors B7 to B15.
and resistors R100 to R103, and receives the output of the emitter follower transistors B5 and B6 when the clock signal CLK is at a high level, and holds the outputs of the emitter follower transistors B5 and B6 when the clock signal CLK is at a high level. Transistors B7 and B8 are input transistors, and when transistor Bll is turned on by clock signal CLK, emitter follower transistors B14 . B15
provides an output signal to the pace of.

Transistor B14. The emitter output of B15 is fed back to the transistors BIO and B9, respectively. Thereafter, the transistor B11 is turned off by the low level of the clock CLK, and the transistor B12 is turned on by the high level of the clock CLK, thereby holding data. Note that the transistor B13 is used as a current source, and a constant voltage VR is applied to the current source.

The data held in the latch circuit is transferred to the next stage M
ECL-C composed of O8FETM109 to M112
0MO from ECL level by MOS level conversion circuit
It is converted into an 8-level output signal and used as read data DO.

The main amplifier MAI' shown in FIG. 13 includes current source MO8FETs M2O0 to M2O6 that are turned on only when the read signal R is at a high level, and a current source MO8FET M207 that is always turned on. still,
Transistors equivalent to the main amplifier MAL described above are given the same reference numerals and will not be described. The difference from FIG. 12 is that diodes DI and D2 are connected to the emitters of emitter 7 lower transistors B5 and B6, and a 20th differential sense circuit is connected to the outputs of these diodes D1 and D2. The second differential sense circuit includes a differential bipolar transistor B20
．． B21. Said transistor B20. Diode-connected M connected between the collector of B21 and the Vcc terminal
O8FETM208. It is composed of M2O9 and level clamp diodes D3 to D6. The diodes D3-D6 clamp the collector potentials of the differential transistors above their pace potential, so that the differential transistors B20. Prevents B21 saturation.

FIG. 14 shows a generating circuit for the common data line bias potential VCDB applied to the bias circuit BClc of FIG. 8, and FIG. 15 shows a generating circuit for the constant voltage Vcs for the current source.

The VCDB generation circuit, as shown in FIG.
O8FET M3O0, M301, NMO8FETM
302-M305 and bipolar transistor B50-
832.

The Vcs generation circuit, as shown in FIG.
8FETM400, NMO8FETM401゜M4O
2, and bipolar transistors B40 and B41.The operation of the above vcoa and Vcs generation circuit will not be explained as it is believed to be easily understood by those skilled in the art.

FIG. 16 is a simplified version of FIG. 7, and its operation will be briefly explained.

The high-speed side input circuit 6-3 includes a frame buffer memory 6.
-5 etc., address input data (pixel data) is input in synchronization with a high-speed reference clock. Further, write data and addresses are inputted from the microprocessor 6-5' side to the low-speed side input circuit 6-3° in synchronization with a relatively low-speed reference clock. Memory array 6-1 is accessed by these two input systems. The stored data, that is, the digital image signal read out from the memory array 6-1 by this access, is converted into an analog image signal by the analog section 13-2 and the ODA converter 6-7, and is output. A color image can be displayed on a color CRT using the analog image signal V0 output in this manner. Note that 6-2 is a high-speed peripheral circuit, and 6-2' is a low-speed peripheral circuit.

FIG. 17 shows a state in which a simultaneous selection prohibition circuit 11-1 is added to the color palette CPLT.

Although the reference numbers of the address signals are different, it should be understood that they are the same.

In other words, the address signal Ad is simultaneously applied from the high speed side and the low speed side.
and Ad' are input, both addresses Ad and Ad' are input.
It is determined whether both are addresses that select the same memory cell, and when it is determined that the same memory cell is selected, the selection operation of the decoder circuit 6-4, 6-4' of the memory array 6-1 is prohibited. let

This simultaneous selection prohibition circuit 11-1 is configured to control the high-speed side address Ad.
It is composed of a gate 11-2 which performs an exclusive OR for each bit position between and a low-speed address Ad', and a gate 11-3 which performs a general summation of the exclusive OR taken for each bit position. The general logic output of the gate 11-3 is applied to the decoder circuit 6-4.6-4° as the selection inhibit signal In. In the decoder circuit 6-4, 6-4', the number of logic inputs of the logic gate in any decoding stage is increased by one, and the above-mentioned selection prohibition signal In is added to this added logic input.
By introducing 5, the selection operation at the time of simultaneous selection is prohibited.

In this case, the selection prohibition signal In may be applied to both the low-speed side and high-speed side decoder circuits 6-4. Alternatively, it may be given only to the high-speed decoder 6-4 to give priority to the low-speed address Ad'.

The simultaneous selection prohibition circuit 11-1 as described above makes it possible to reliably avoid malfunctions that may occur due to simultaneous selection of the same memory cell by the high-speed side and the low-speed side.

Figure 18 shows test circuit 1 on the color palette CPLT.
2-1.12-1' is built-in. The test circuits 12-1, 12-1' are provided independently in the high-speed peripheral circuit 6-2 and the low-speed peripheral circuit 6-2°. Reference numeral 12-1 is a test circuit for performing a high-speed operation test, and is constructed using a circuit structure compatible with high-speed operation, such as an H4-CMOS logic circuit, for example.

12-i' is a test circuit for performing a low-speed operation test, such as a pure CMOS logic circuit type,
It is constructed using a circuit structure suitable for low power consumption and high integration.

As described above, by arranging the test circuits 12-1 and 12-1° separately for each operating speed, it is possible to appropriately perform an operating test at each speed. In addition, since the operation test of two systems, high-speed side and low-speed side, can be performed simultaneously, the test time can be shortened. Furthermore, since the operation tests of the two systems on the low-speed side and the high-speed side can be performed separately from each other, it is also possible to obtain the advantage that test patterns (turn creation, etc.) are simplified.

FIG. 19 shows the above color palette CPLT provided with test circuits 14-1 and 14-2.

In this case, the test circuits 14-1 and 14-2 include the digital part test circuit 14-1 and the analog part test circuit 1.
4-2.

The digital section test circuit 14-1 tests the high-speed and low-speed side digital sections 13-1 based on test conditions applied from an external input terminal (not shown) via an input circuit. The analog section test circuit section 14-2 tests the analog section 13-2 based on test conditions given from the external input terminal 8 (not shown).

In this way, the digital section 13-1 and the analog section 13-2
By having the tests performed by separate test circuits 14-1 and 14-2, reliability is improved by simplifying test pattern creation and optimizing the test, as in the case of the embodiment shown in FIG. This effect can be obtained.

FIG. 20 shows a schematic configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention.

The semiconductor integrated circuit device IC2 shown in the figure is configured as a so-called multi-board RAM, and includes two peripheral circuits 6-2.6 for one memory array 6-1.
-2' are formed within the same semiconductor substrate. One peripheral circuit is constituted by a high-speed side circuit block 6-2,
External system 6-5 operating with high-speed reference clock φ1
Address A from. -A is received by the input circuit 6-3 and decoded into a selection signal by the decoder circuit 6-4. The other peripheral circuit 6-2'' is constituted by a low-speed side circuit block, and receives addresses B0 to B from an external system 6-5'' that operates with a relatively low-speed reference clock φ2 at an input circuit 6-3'. It is decoded into a selection signal by a decoder circuit 6-4'.In the figure, 6-6 is a sense circuit that reads out stored information from a selected memory cell, and 6-7 is stored data read out by the sense circuit 6-6. 6-8 is a CRT display that displays the analog stored data.

As described above, in the semiconductor integrated circuit device IC2 according to the second embodiment described above, in addition to the high-speed side circuit block and the low-speed side circuit block, a common circuit block (memory array 6-1) accessed by both circuit blocks is provided. It is characterized by having This allows the low-speed system and high-speed system to be linked directly within the semiconductor integrated circuit device without going through an external interface device, making it possible to build an efficient system. .

In addition, in the same figure, the decoder DEC6-4 is FiG,9
(5) and (The circuit shown in the box is the decoder DEC6-
4' is F''iG, 10 (Al and (Bl) are used.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in addition to the high-speed circuit block and the low-speed circuit block, a medium-speed circuit block having a circuit structure that operates at an intermediate speed between the two circuit blocks may be added.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to the multi-board RAM for color palettes, which is the field of application that formed the background of the invention.
The present invention is not limited thereto, and can also be applied to microprocessors or gate arrays, for example.

The image display system shown in FIG. 6 is an example of:
It is not limited to that. For example, the system disclosed on pages 402 to 420 of [Transistor Technology January Issue] published by CQ Publishing on January 1, 1987 can be used.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, high speed is required by forming a plurality of circuit blocks with the same type of function in the same semiconductor integrated circuit device, and by making the circuit structures of the plurality of circuit blocks constituting the same type of function different between the blocks. Operations that require higher speeds can be performed by circuit blocks with circuit structures suitable for higher speeds, while operations that do not necessarily require higher speeds can be performed by circuit blocks with circuit structures suitable for lower power consumption and higher integration. Therefore, it is possible to efficiently configure a system or device having a plurality of speed environments, and to optimize the configuration of a system or device that requires high speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a diagram showing an example of a circuit structure of a circuit unit that is a component of a low-speed side circuit block, and FIG. 4 is a diagram showing an example of the circuit structure of a circuit unit that is a component of the high-speed side circuit block, FIG. 4 is a diagram showing another example of the circuit structure of a circuit unit that is a component of the low-speed side circuit block, and FIG. 6 is a diagram showing another example of the circuit structure of a circuit unit that is a component of a high-speed side circuit block, FIG. 7 shows a block diagram of the color palette CPLT of the present invention, FIG. 8 shows a memory array and its peripheral circuit diagram of the color palette CPLT of the present invention, and the 9th section shows the semiconductor integrated circuit device of FIG. High-speed side decoder circuit 6 formed in
9 (B) is a specific circuit diagram of the BCL circuit, and the section 10 is a low-speed side decoder circuit formed in the semiconductor integrated circuit device of FIG. 8. 6-4"; FIG. 10 (g)) is a specific circuit diagram of the 0M08 circuit; FIG. 11 is a diagram (b) schematic diagram of the memory cell in FIG. 8; 1st
Figure 2 shows a circuit diagram of the high-speed main amplifier MAI in Figure 8, Figure 13 shows a circuit diagram of the low-speed main amplifier MAI in Figure 8, and Figure 14 shows a circuit diagram of the VCDB generation circuit. , 15th
The figure shows the circuit diagram of the C3 generation circuit, and Figure 16 shows the circuit diagram of the C3 generation circuit.
FIG. 17 is a diagram showing a schematic configuration when a simultaneous selection prohibition block 11-1 is provided in the color palette CPLT of the present invention; FIG. 18 is a diagram showing a schematic configuration of the color palette CPLT of the present invention; Palette lc: A diagram showing a schematic configuration when a PLT is provided with test circuits 12-1 and 12-1'. FIG. 19 shows a color palette CPLT of the present invention provided with test circuits 14-2 and 14-2' FIG. 20 is an M2 embodiment of the present invention, and is a block diagram when the present invention is applied to a dual-port LAM. ICI, IC2... semiconductor integrated circuit device, 1-1~
1-n...High-speed side circuit block, 1-1' to 1-n'
low speed side circuit block, 6-1... memory array, 6
-2...High-speed side peripheral circuit, 6-2'...Low-speed side peripheral circuit, 6-3...High-speed side input circuit, 6-3゛...Low-speed side input circuit, 6-4...・High-speed side decoder circuit, 6-
4'...Low speed side decoder circuit, W...High speed side word line, W'...Low speed side word line, D...High speed side data line, D'...Low speed side data line, 11- 1...Simultaneous selection prohibition circuit, 12-1...High speed side test circuit, 12-
1'...Low speed side test circuit, 13-1...Digital section, 13-2...Analog section, 14-1...Test circuit for digital section, 14-2...Test for analog section Circuit, CPLT...color palette LSI. Figure 1 Figure 4 Figure 5 Figure 6 Figure 70 (A) Figure 70 (B) ℃←0 Figure 18 Figure 19

Claims (1)

[Claims] 1. A plurality of circuit blocks having the same type of function are formed within the same semiconductor integrated circuit device, and the plurality of circuit blocks constituting the same type of function have different circuit structures for each block. A semiconductor integrated circuit device comprising: 2. A circuit block having a circuit structure suitable for relatively high-speed operation and a circuit block having a circuit structure suitable for relatively low power consumption and high integration each constitute the same type of function. Claim 1 characterized by
The semiconductor integrated circuit device described in . 3. Within the same semiconductor integrated circuit device, a high-speed side circuit block having a circuit structure suitable for relatively high-speed operation, and a low-speed side circuit block having a circuit structure suitable for low power consumption and high integration; A semiconductor integrated circuit device comprising a common circuit block that is accessed by both a high-speed circuit block and a low-speed circuit block. 4. As a combination of the circuit structure of the high-speed side circuit block and the circuit structure of the low-speed side circuit block, the high-speed side is bipolar.
4. The semiconductor integrated circuit device according to claim 3, wherein the semiconductor integrated circuit device is a CMOS complex logic circuit, and the lower speed side is a pure CMOS logic circuit. 5. The semiconductor integrated circuit device according to claim 4, wherein a memory array is formed as a common circuit block. 6. Within the same semiconductor integrated circuit device, a high-speed side circuit block having a circuit structure suitable for relatively high-speed operation, and a low-speed side circuit block having a circuit structure suitable for low power consumption and high integration; A semiconductor integrated circuit device comprising a high-speed side test circuit and a low-speed side test circuit that independently test the high-speed side circuit block and the low-speed side circuit block, respectively.