JPH02306339A - Bit addressing system - Google Patents

Abstract

PURPOSE:To attain address calculation at a short time by providing a displacement field and a base address field in an addressing operand. CONSTITUTION:An address 501 in byte unit is obtained from the base address field 4021 in the addressing operand 402 of a bit string extraction instruction 400. On the other hand, an address 503 in bit unit obtained from the field 4022 is shifted to a side lower by three bits in a shifter/code expansion unit 504 and high-order bits are supplied to an adder 502. It generates the effective address 505 of bytes, which include target bits, and three bits which are not supplied from the shifter/code expansion device 504 to the adder turn into bit offsets 506. Thus, the effective byte address and the bit offsets can simultaneous ly be obtained and therefore, the address calculation time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an addressing method in an information processing device, and particularly to a bit addressing method that performs bit-by-bit access.

[Conventional technology]

Generally, when a computer is used to process data, it is determined where and in what form the data exists. The method of specifying where something is located is called addressing, and the promise of how it exists is called data reference type.

Data is accessed, and the contents of the data are interpreted, operated on, and transferred in accordance with instructions written according to these conventions.

The minimum unit of addressing for memory is usually one byte (8 bits). That is, memory is defined as simply a string of bytes, and data is accessed by its byte group address.

A byte address is a value that uniquely specifies the location of a byte.

An instruction format generally consists of a sequence of an instruction code indicating an operation and an addressing operand specifying operation data to be manipulated by the instruction. The addressing operand has multiple fields, and various addressing modes are specified by combinations of these fields. One field of the addressing operand is assigned as a base address reference field, in which the base address for specifying operation data is directly written, or information specifying the register storing the same address is written. There is. Other fields are used as displacement fields.
Displacement information for the address is described. An index φ field may be used instead of the displacement field, and this field describes information specifying the index register storing the displacement information. Furthermore, it may include both a displacement field and an index field, or it may include two displacement fields. From the address information obtained from these fields, an effective address for operation data access is generated according to the specified addressing mode, but in any mode, the minimum unit of the effective address is the above-mentioned address. This is a byte address.

On the other hand, some instructions executed by an information processing device (microprocessor) require bit-by-bit addressing. A typical example is a bit field instruction. This instruction creates a bit string (bit field) of arbitrary length, starting with a bit located at an arbitrary location in memory (and therefore not necessarily on a byte boundary).
These are instructions that perform operations such as extraction, insertion, and comparison. For example, a bit string extraction instruction extracts a bit string of a specified length starting from a specified bit in memory and transfers it to a specified register.
The bit string insertion instruction inserts data of a bit string of a specified length in a specified register into a bit string of a corresponding length in memory, with the specified bit as the leading bit. Therefore, when executing a bit field instruction, it is necessary to address an arbitrary bit in memory.

However, as mentioned above, the minimum unit of the effective address generated by the addressing operand is the byte address, so the addressing operand of the bit field instruction is the byte data containing the first bit of the bit string to be manipulated. Only byte addresses can be specified. For this reason, it is necessary to further provide a bitwise offset operand having information for specifying the position of the first bit of the bit string to be manipulated in the bitwise field instruction. For example, as shown in FIG. 4, the format of a bit string extraction instruction 200 includes an instruction code 201 indicating that it is a bit string extraction instruction, an addressing operand 202, and a length operand 204 indicating bit length information to be extracted. , and the destination operand 205 indicating the storage location information of the extracted data, the minimum unit of the effective address generated using the information of the addressing operand 202 is the byte φ containing the first bit of the bit string to be extracted. Since this is a data boundary, it further includes a bit offset operand 203 that indicates offset information from the boundary to the first bit to be extracted. These two operands 2
02.203 is used to generate the effective address of the first bit to be extracted, and bit addressing is performed.

Such addressing on hardware will be explained with reference to FIG. The instruction code 201 of the bit string extraction instruction 200 fetched from memory is decoded by the instruction decoder, while the addressing operand 20
2 is transferred to an effective address generation device (not shown).

The device extracts the byte containing the first bit of the bit string to be extracted based on the information of the base address reference field, displacement field, and/or index conflict field in the addressing operand 202. Generate an effective byte address 301 indicating the data pie7)'tz. this address 3
01 accesses memory and retrieves data into the processor.

The bit offset operand 203 is also sent to the effective address generator to generate the bit conflict offset effective address 302. The effective address 302 indicates the distance from the beginning of the data loaded by the effective address 301 to the target bit. Note that the value specified by the length φ operand 204 represents the length 303 of the data to be extracted.

[Problem to be solved by the invention]

In conventional addressing, bit addressing is performed in a two-addressing mode using two operands (addressing operand 202 and bit offset operand 203), so that address calculation takes time.

That is, an effective byte address 301 is generated by the addressing operand 202, and necessary processing is performed. Then bit offset operand 20
3 generates the effective address 302 of the bit position. Therefore, the bit offset operand 203
The processing cannot be performed until the processing by the addressing urn operand 202 is completed, and it takes a long time to calculate the address as a whole.

In addition, when an addressing mode can be specified for each operand, and byte-address and bit offset are specified by separate operands, the addressing mode for bit offset can be freely selected, but its purpose is Due to their characteristics, only a few types are actually used, and many of them have redundant functions.

Furthermore, if the bit offset is allowed to take a value larger than the data bus width or a negative value, the target data is not in the loaded data and invalid data is accessed. The value of the bit offset must be limited to O or more and less than the value determined by the data bus width.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a bit addressing scheme that allows address calculation to be performed in a short time.

[Means to solve the problem]

In the bit addressing scheme according to the present invention, the effective address of the desired bit is generated using only the addressing operand. In other words, when the instruction to be executed requires bit addressing, such as a bit field instruction, the values specified in the index field and displacement field in the addressing operand are based on the base address 6. The distance from the byte boundary of the base address specified by the field to the target bit is expressed as a value expressed in two's complement. This value is shifted M bits in the direction of its lower bits, and the shifted value is added to the base address specified in the base address field to generate an effective bid pad address and a bit conflict offset for the target bit.

Therefore, one operand can simultaneously generate two effective addresses: an effective byte conflict address of a byte having a target bit, and a bit Φ offset that is the displacement from this base address to the target bit. The specified range of the bit offset is from 2N-1 bits to (+2N-'-1) bits, and a range of 2N4M bits can be specified as the bit address.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings showing one embodiment of the present invention.

Referring to FIG. 1A, the format of a bit string extraction instruction 400 among bit-field instructions is shown as an embodiment of the present invention.

This instruction 400 includes addressing operands 402,
It has a length operand 403 indicating the length of the bit string to be extracted, and a destination operand 404 indicating the transfer destination information of the data of the extracted bit string, and as shown in FIG. It does not have an operand 203. Addressing operand 402 includes base address urn field 4021 and displacement φ field 4 as shown in FIG. 1B.
022. For instructions that do not require bit-addressing, these two fields 4021.4022
The address information determined by is address information in bytes as described above, and the minimum unit of the effective address generated by these is a byte address.

On the other hand, in the case of a bit field instruction, field 4
The value determined by 022 is regarded as a value indicating the distance from the base contention address in bytes determined by the base contention address field 4021 to the target bit in two's complement representation, and is determined by the base contention address field 4021. The effective byte address of the byte containing the bit to be processed and the effective offset from the first bit of that address to the desired bit.
Addresses are generated at the same time. In this example, since the address in bytes is determined by the base address field 4021, the lower three bits of the data shown in the field 4022 are used as the effective offset address, and the information determined by the remaining bits is used as the effective offset address. is combined with the information specified by field 4021 to generate the effective byte address of the byte containing the desired bit.

That is, when a bit string extraction instruction 400 is fetched from memory, its instruction code 401 is decoded by a decoder (not shown) while addressing operand 40
2 is supplied to the effective address generation device shown in FIG.

A 32-bit byte-wise address 501 is derived from the base-address field 4021 in addressing operand 402 and provided to the left input of adder 502. On the other hand, the address information obtained from the field 4022 in the addressing operand 402 is used as a bit-wise address 503 and
04. This shifter/sign extender 504 is
Shift the bit unit address 503 to the lower side by 3 bits, and add the same data as the most significant bit of the address 503, that is, the sign bit, to the upper side for a total of 35 bits.
Generate bit address information. The upper 32 bits (bit numbers 34 to 3) of the address thus generated are supplied to the right input of adder 502. An adder 502 adds the power of both the left and right hands and generates a 32-bit address 505. Therefore, address 505 becomes the effective address of the byte containing the desired bit. The 3 bits (
Bit numbers 2 through O) are the offset 506 to the effective byte-address of the target bit. Thus, the effective address and bit offset can be obtained simultaneously from a single addressing operand 402, and the bit-
Addressing becomes possible. length operand 40
Information 3 specifies the length of the bit string to be extracted with the addressed bit as the leading bit.

FIG. 3 shows the relationship between the above-mentioned addressing method and data on the memory. That is, the byte unit address 501 indicates a base address indicating a predetermined byte on the memory, and the bit unit address 503 indicates the distance (i.e., the number of bits) from the first bit of the base O address to the target bit. It shows. Therefore, the output address 505 of the adder 502 is the effective byte address of the byte containing the target bit, which is 5
06 is the bit offset to the target bit.

Next, as a specific example, consider a bit string extraction instruction that extracts data on the memory (3 bits of bit numbers 5 to 7 of the byte address "OOOOOO13H") and transfers it to the general-purpose register R6. In this example, addressing φ
Base own address field 40 of operand 402
21 is the memory “second byte address” 00000
Use general-purpose register R1 that already stores 010H#. Therefore, field 4021 is based on
This field becomes an address/register designation field, and the designation code "00001, B#" for general-purpose register R1 is written therein.

Of course, you can also specify immediate. Field 4022 is used as a displacement field, so it contains the desired bit data from the base working address ')#m' OOOOOOOL D H
When used as an index field, the designation code of the index register in which the data is stored is written.

The content of the length operand 403 is "#00000003H" if an immediate is specified, but a register may also be specified. Destination fist operand 404
The designation code #0OOOOB" of general-purpose register R8 is written. When the bit string extraction instruction in which such information is written is executed, the address information 501 shown in FIG.
' is read from register R8 and provided to the left input of adder 502. Meanwhile, the contents of displacement Φ field 4022 are provided to shifter/sign extender 504, whose output 504' is as shown in FIG. The upper 32 bits of that output are fed to an adder 502 and
1' is added. The result of the addition is shown at 505' in FIG. 6, and an effective byte address "00000013H" containing the target bit is obtained. And 504
The lower three bits ``101B'' of ``101B'' become an offset address specifying bit number 5. Length information 507'
is "3H". Thus, byte address #00
Data of bit numbers 5 to 7 in "000013H" are extracted and transferred to bit numbers 5 to 7 of general-purpose register R8, respectively.

Since the value obtained from field 4022 is expressed in two's complement, it is possible to address even bits of an address smaller than the base reference byte address. For example, set the base reference byte address as ``0OO'' above.
If the first bit of the target bit string is bit number 4 of the byte address "0OOOOOOEH", then the value obtained from field 4022 is 7.
1 F FF FF FF 4 H# may be used. As a result, the output of adder 502 is #0OOOOOOOE
H”, and the lower 3 bits from chic 504 are “10”.
It becomes 0B#.

Both an index and a displacement may be used as the field 4022, and in this case, the sum of the values obtained from both fields is the distance from the base working address to the target bit. If two displacements are used, the base e-address field and the first displacement
The data in the memory of the byte address obtained from the field is used as a base address, and the distance from the same address to the target bit is determined as the value obtained from the second displacement field.

If the instruction to be executed does not require bit addressing such as a bit-field instruction, fields 4021 and 4022 are both byte-unit addresses, and addressing is performed with the minimum unit being a byte. The addressing modes include:

■Mode with register indirect index: This is an addressing contention mode that specifies data at an effective address calculated from two values: a base contention address and an index value (or bit offset) from the base address.

■Displacement mode: This is an addressing mode that specifies data at an effective address calculated from two values: a base address and a displacement (or bit offset) from the base address.

■Mode with displacement index Specify the data at the effective address calculated from three values: the base address, the displacement from the base address, and the index value (or bit offset) from the base address. This is the addressing e mode.

(2) PC relative displacement mode: Compared to the displacement mode, the only difference is that the base address is the start address of the instruction currently being executed.

(2) Mode with PC relative relative displacement index: Compared to the mode with displacement index, this mode differs only in that the base address is the start address of the instruction currently being executed.

■Displacement indirect mode: Similar to the displacement mode, the effective address is calculated from two values: the base address of the register and the displacement from the base address, but the address pointed to by the calculated address is The difference is that is a pointer in memory. That is, this is the addressing mode used when the pointer to the data is in memory (memory indirection).

■Displacement indirect index mode
: The effective address of the base pointer to the data is calculated from two values: the base address held by the register and the displacement from the base number address. That is, the base pointer to the data is in memory (
This is the addressing mode used when the effective address of the data is obtained by adding an index value (or bit offset) to the base pointer (memory indirection).

(2) PC relative displacement indirect mode: Compared to the displacement indirect mode, the only difference is that the base address is the start address of the instruction currently being executed.

■Mode with indirect PC displacement index: Compared to mode with indirect displacement index, the only difference is that the base address is the start address of the instruction currently being executed.

[Phase] Double displacement mode) A memory indirect mode in which two displacements (or displacement and bit offset) can be specified.
Base fist register, displacement #2, and displacement #1 (or bit conflict offset)
It is specified by three elements. Set the data at the address calculated from the base address and displacement #2 in the base register as the new base address, and set it to the effective address calculated from it and displacement #1 (or bit offset). Specify some data. This addressing contention mode is particularly useful when manipulating complex data structures such as queue structures and tree structures.

(2) PC relative double displacement φ mode Compared to the double displacement mode, this mode differs only in that the base address is the start address of the instruction currently being executed. This addressing mode is also particularly useful when manipulating complex data structures such as queue structures and tree structures.

[Phase] Direct address indexed mode): Located in the effective address calculated from two values: the 32-bit base address in the direct instruction and the index value (or bit offset) from the base address. This is an addressing mode that specifies data.

[Phase] Mode with direct address indirect index: has the 32-bit address of the base pointer in the direct instruction, i.e. the base pointer to the data is in memory (memory indirect), and the index value is also attached to the base pointer. This is the addressing mode used when the effective address of the data is the addition of (or bit offset).

In this embodiment, the addressing designation field of the operand is the same as that of bit addressing and conventional byte-ken addressing, and the distinction is made based on the contents of the instruction code.

Therefore, since there is no need to increase the number of types of addressing modes, an increase in the hardware of the instruction decoder can be suppressed.

In addition, the degree of freedom in program design can be increased because it can be specified without being restricted by the width of the data bus.

〔Effect of the invention〕

According to the present invention, since data that is not on a byte boundary can be specified with one operand, encoding time can be shortened and an effective address can be generated quickly. Therefore, it is possible to increase the execution speed of a program that uses variable-length data extensively (for example, a graphics program that uses pipmaps).

Since the bit offset designation method can be simplified and unnecessary addressing mode designation functions can be removed, the size of the program can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a diagram showing the format of a bit string extraction instruction among bit field instructions in an embodiment of the present invention.
Figure B is a configuration diagram of the addressing operand in Figure 1A,
FIG. 2 is a diagram showing a method of obtaining an effective address from the bit field instruction shown in FIG. 1, FIG. 3 is a diagram showing the relationship between the obtained effective address and data on memory, and FIG. 5 is a diagram showing the format of a bit field instruction according to the conventional addressing method, and FIG. 5 is a diagram showing a method for obtaining an effective address from the operand in the bit field instruction shown in FIG. 4 according to the conventional addressing method. FIG. 6 is a diagram showing a specific addressing method according to this embodiment.

401... Instruction code, 402... Addressing
Operand, 403...Length operand, 40
4...Destination operand, 501...
・Byte unit address, 502...Adder, 503・
... Bit unit address, 504 ... Shifter, 5
05...Base fist address, 506...Lower 3 bits.

Agent Patent Attorney Susumu Uchihara mα & Eight Figure 1

Claims (1)

[Claims] 1. An instruction has an instruction code and an addressing operand, the addressing operand has a first and a second field, and the value determined by the first field is set to two. Regarded as a bit-wise value in complement representation, that value is shifted by M bits in the direction of its lower bits and added to the address determined in the second field to form the effective address and the bits.
A bit addressing method characterized by generating an offset. 2. The bit addressing system according to claim 1, wherein the second field is an index field. 3. The bit addressing system according to claim 1, wherein the second field is a displacement field. 4. The bit unit according to claim 1, wherein when the contents of the instruction code represent predetermined contents, the value determined in the second field is regarded as the value in units of bits. Addressing method. 5. The range of the bit offset is -2^N^-^1
A bit addressing scheme according to claim 1, characterized in that the bits are (+2^N^-^1-1) bits. 6. The bit addressing method according to claim 1, wherein the bit address represented by the base address and the bit address is specified within a range of 2^N^+^M bits.