JPH02305148A - Digital signal recoding circuit - Google Patents

Abstract

PURPOSE:To attain accurate decoding at all times by obtaining a mean value of plural amplitude medians stored in an analog storage circuit, using the mean value as a reference signal level at a succeeding level discriminating point and using the level for level comparison with a received digital signal. CONSTITUTION:The levels '1', '0' of each bit of a received digital signal RD are discriminated based on a reference signal level Vth and an offset voltage -DELTAV or +DELTAV prepared in advance is added to a signal VS of the received digital signal RD to obtain the amplitude median V of the received digital signal RD. The amplitude median V is stored in capacitors 31a-31c of a switched capacitor circuit 30 together with the amplitude median obtained based on 3 past consecutive level discrimination timings and a mean value of the amplitude medians is used as a new reference signal level Vth, which is used for the succeeding level discrimination timing. Thus, the received digital signal RD is decoded at all times according to the optimum reference signal level Vth.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a digital signal decoding method for determining "12."0" of a received digital signal, for example in a digital mobile communication system.

(Prior art) In a digital mobile communication system, a transmitting side replaces "1" and "0" of a digital signal with a change in frequency or a change in voltage value before transmitting it, and a receiving side converts the digital signal sent from the transmitting side. After receiving and demodulating the signal, the received digital signal is compared with a reference signal level to determine whether it is "1" or "0". FIG. 5 shows an example of the decoding operation. As shown in FIG. 5(a), the reference signal level vth is set to an appropriate value in advance, and the received digital signal RD
By comparing the level of Vth with this reference signal level Vth, a decoded digital signal OD as shown in FIG. 3(b) can be obtained.

(Problem to be Solved by the Invention) However, this type of conventional decoding circuit has a reference signal level v
Because th is set fixedly, for example, variations in the modulation/demodulation frequency or voltage value may occur on the transmitting or receiving side.
As a result, if the DC level of the received digital signal RD changes as shown in FIG. 6(a), accurate level judgment cannot be made (as a result, the decoded output OD as shown in FIG. 6(b) There was a problem where an error occurred.

Therefore, the present invention focuses on this point, and the received digital 1=
It is not affected by changes in the DC level of the signal, and even if the signal value of the received digital signal suddenly changes temporarily due to noise, etc., the effect is removed, thereby ensuring accurate decoding at all times. The object of the present invention is to provide a digital signal decoding circuit that obtains the desired results.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides the ability to maintain the "1" level of the received digital signal even if the DC level of the received digital signal changes.

Focusing on the fact that the amplitude value between "0" is approximately constant, an offset value generation circuit that generates a preset offset value based on the amplitude value of this received digital signal and a reception a center value calculation circuit that calculates the amplitude center value of the received digital signal by adding or subtracting the offset value to the signal value of the digital signal;
Each time a new amplitude center value is calculated by this center value calculation means, an analog storage circuit is provided which stores this amplitude center value together with each amplitude center value calculated at a plurality of consecutive past level determination points, and a reference signal level. The reference signal level output circuit calculates the average of the plurality of amplitude center values stored in the analog storage circuit, and uses this average value as the reference signal level at least at the next level determination point for the received digital signal. This is used for level comparison with the signal.

The present invention is also characterized in that a switched capacitor is used as the analog storage circuit.

(Function) As a result, according to the present invention, the reference signal level is always set to the center value of the amplitude of the received digital signal, so even if the DC level of the received digital signal changes for some reason, Following this change in the DC level, the reference signal level also changes. Therefore, the received digital signal always changes between 1'' and 0 according to the optimal reference signal level.
” is determined, thereby enabling error-free and high-quality decoding.Also, when determining the reference signal level, each amplitude center value determined at multiple past consecutive level determination points The average value is determined and this average value is set as the reference signal level at the next level judgment point, so even if the signal value of the received digital signal changes suddenly due to noise etc., the influence of the change can be ignored. This prevents a problem in which the received amplitude center value is directly set as the reference signal level at the next level determination point, and thereby the reference signal level can be set more accurately.

(Embodiment) FIG. 1 shows the configuration of a digital signal decoding circuit in an embodiment of the present invention.

In the same figure, 80 is a level comparator, which compares the signal value of the received digital signal RD with a reference signal level vth in its bit period, and outputs the comparison result as a decoded signal OD via a resistor 90. It is outputting.

By the way, the decoding circuit of this embodiment has the above-mentioned reference signal level V.
This circuit includes an offset voltage generation circuit 1 that generates an offset voltage ΔV.
0 and a voltage comparator 20. The offset voltage generation circuit 10 temporarily stores the offset voltage ΔV output from the power supply 11 in the capacitor 14 via the switch 12, sets the polarity (positive or negative) in the polarity setting circuit 13, and supplies it to the voltage comparator 20. It is configured as follows.

The polarity setting circuit 13 is, for example, as shown in FIG. 2, in which two pairs of switches 131, 132 and 133° 134 are cross-connected. “0” of signal OD,
It operates reciprocally on and off depending on “1”. Note that the value of the offset voltage ΔV is set to approximately 1/2 of the amplitude value of the received digital signal RD.

The voltage comparator 20 adds the offset voltage ΔV output from the offset voltage generation circuit 10 to the signal value of the received digital signal RD, thereby calculating the center value of the amplitude of the received digital signal RD. The amplitude center value is supplied to the switched capacitor circuit 30.

The switched capacitor circuit 30 includes four switched capacitors, each of which has a capacitor 31a to 31d, a charging control switch 32a to 32d provided at its signal input terminal, and an output voltage of the capacitor 31a to 31d. It is composed of discharge control switches 33a to 33d provided on the side. Among these control switches 32 and 33, charging control switches 32a to 32a are
32d are sequentially and selectively turned on in synchronization with the transmission lock CLK by a timing signal generated from a timing signal generation circuit (not shown). Further, the discharge control switches 33a to 33d are operated to control the transmission lock CL by a timing signal generated from the timing signal generation circuit.
They turn on simultaneously in synchronization with K. In addition, these charge control switches 32a to 32d and discharge control switch 33
The ON operation timing of a to 33d is the transmission lock CL.
The phases are set to be shifted from each other by 1/2 of K. Therefore, each switched capacitor stores each amplitude center value output from the voltage comparator 20 at four adjacent level judgment timings in the capacitors 31a to 31d, and stores these four amplitude center values at each level judgment timing. The signals are read from the capacitors 31a to 31d and output.

The four amplitude center values output from each of the switched capacitors are amplified by current amplifiers 40a to 40d, and then introduced into an adder 60 via resistors 50a to 50d. This adder 60 calculates the average value of the four amplitude center values, and this average value of the amplitude center values is supplied to the voltage holding circuit 7'0. This voltage holding circuit 70 is
Switches 72 and 73 are placed on the input side and output side of the capacitor 71, respectively.
．． By the on/off operation of 73, the average value of the center amplitude values outputted from the adder 60 is temporarily held in the capacitor 71, and then this average value is supplied to the level comparator 80 as the reference signal level vth. It should be noted that, like the switch 12 of the offset voltage generation circuit 10 and the control switches 32 and 33 of the switched capacitor circuit 30, the switches 72 and 73 are also turned on and off by timing signals generated from a timing signal generation circuit (not shown). do.

Next, the operation of the digital signal decoding circuit configured as above will be explained. First, prior to the operation of the circuit, the amplitude value between "1" and "0" of the received digital signal RD is separately detected, and the value of 1/2 of this amplitude value is set as the offset voltage ΔV and the voltage of the offset voltage generation circuit 10 is adjusted. Set to 11.

In addition, each capacitor 3 of the switched capacitor circuit 30
1a to 31d each store an initial value of the center amplitude value by an initial value setting circuit (not shown).

In this state, when a digital signal arrives and an operation instruction is input to the decoding circuit, a timing signal generation circuit (not shown) generates a predetermined timing signal in synchronization with the transmission lock CLK of the received digital signal RD. Each switch starts its on/off operation.

For example, the received digital signal R as shown in FIG.
If D is input, switch 12 is activated in synchronization with the first falling edge to' of the transmission lock CLK.
is on, each switch pair of the polarity inversion circuit 13 is off, and the charging control switches 32a to 32a of the switched capacitor circuit 30 are on.
32d is turned off, discharge control switches 33a to 33d are turned on, and switches 72 and 73 are turned on and off, respectively. Therefore, the initial values of the amplitude center values stored in each of the capacitors 31a to 31d of the switched capacitor circuit 30 are outputted, and the average value thereof is determined by the adder 60. Then, this average value is determined by the voltage holding circuit 7.
0 is supplied to a capacitor 71 and held there. In other words, Q6 is performed at the level determination timing tl.

Now, when the first rising edge t1 of the transmission lock CLK is detected in this state, the switches 72 and 73 of the voltage holding circuit 70 are turned off and on, respectively, in synchronization with this edge ti. Therefore, the reference signal level vth held in the capacitor 71 is supplied to the level comparator 80, and the level comparator 80
The sign of the received digital signal RD is determined accordingly.

Further, at this time tl, the switch 12 is turned off, and one of the switch pairs of the polarity inversion circuit 13 is turned on according to the level of the decoded signal OD. Therefore, the offset voltage generation circuit 10 outputs an offset voltage -Δ■, and this offset voltage -ΔV is added to the signal value of the received digital signal RD by the voltage comparator 20. For example, if the signal value of the received digital signal RD is vSl as shown in FIG. Thus, the amplitude center value v1 is output.

Furthermore, at this tl, only the switch 32a of the charging control switches 32a to 32d of the switched capacitor circuit 30 is turned on, and the discharge control switches 33a to 32d are turned on.
33d are all turned off.

Therefore, the amplitude center value v1 outputted from the voltage comparator 20 is stored in the capacitor 31a.

Then the second falling edge tl of transmission lock CLK
' is detected, each switch 72 of the voltage holding circuit 70
．． 73 are turned on and off, respectively. Therefore, the reference signal level vth is not supplied to the level comparator 80, and as a result, the level of the received digital signal QRD is not determined. Also, at this t1', as in the case of tO',
Each switch pair of the polarity inversion circuit 13 is turned off, and each switch 32 and 33 of the switched capacitor circuit 30 is turned off and on, respectively. Therefore, the amplitude center values held in each of the capacitors 31a to 31d of the switched capacitor circuit 30 are supplied to the adder 60, and the adder 60 calculates the average value.

Then, this average value is determined by the capacitor 7 of the voltage holding circuit 70.
1 as a new reference signal level Vih.

Then the second rising edge t2 of transmission lock CLK
is detected, the above edge t1 is detected in synchronization with this edge t2.
As in the case of , each switch 72.7 of the voltage holding circuit 70
3 is off and on, respectively. Therefore, the reference signal level vth held in the capacitor 71 is supplied to the level comparator 80, and the level comparator 80 determines the sign of the received digital signal RD in accordance with this reference signal level vth. Further, at this time, the switch 12 is turned off, and one of the switch pairs of the polarity inversion circuit 13 is turned on according to the level of the decoded signal OD. Therefore, offset voltage +ΔV is output from offset voltage generation circuit 10, and this offset voltage +ΔV is added to the signal value of received digital signal RD by voltage comparator 20. for example,
Assuming that the signal value of the received digital signal RD is VS2 as shown in FIG. 3, this signal 1ii VS
The above +ΔV is added to 2. Therefore, the voltage comparator 20 outputs the amplitude center value v2 as shown in FIG. Furthermore, at this time, the switched capacitor circuit 30
Then, for example, only the switch 32b among the charge control switches 32a to 32d is turned on, and all the discharge control switches 33a to 33d are turned off. Therefore, the amplitude center value V2 output from the voltage comparator 2o is held in the next capacitor 31b.

Then, when the second falling edge t2' of the next transmission lock CLK is detected, each switch 32.3 of the switched capacitor circuit 3°
3 is off and on, respectively. Therefore, the amplitude center values held in each of the capacitors 31a to 31d of the switched capacitor circuit 30 are supplied to the adder 60, and the adder 60 calculates the average value. This average value is then held in the capacitor 71 of the voltage holding circuit 70 as a new reference signal level vLh.

Subsequently, when the third rising edge t3 of the transmission lock CLK is detected, in synchronization with this edge t3, each switch 72, 73t of the voltage holding circuit 70 is activated, as in the case of tl and t2 above. The reference signal level vth, which has been turned off and on and held in the capacitor 71, is supplied to the level comparator 80.
The sign of the received digital signal RD is determined at . At this time, the voltage comparator 20 adds the offset voltage +ΔV output from the offset voltage generation circuit 10 to the signal value VS3 of the received digital signal RD, and thereby outputs the amplitude center value V3 corresponding to this signal value VS3. be done. This amplitude center value v3 is held in the next capacitor 31C of the switched capacitor circuit 30.

Thereafter, similarly, at each falling edge t3', t4', . vth is generated. On the other hand, each rising edge t of transmission lock CLK
4. t5. ..., the sign of the received digital signal RD is determined according to the reference signal level vth, and the amplitude center value is determined according to the signal value of the received digital signal RD. 31c.

In this way, in this embodiment, the levels of 1" and '0" are determined for each bit of the received digital signal RD using the reference signal level vth, and the signal value vS of the received digital signal RD is prepared in advance. Offset voltage −Δ
The amplitude center value V of the received digital signal RD is obtained by adding V or +ΔV, and this amplitude center value V is added to each capacitor of the switched capacitor circuit 30 together with the amplitude center values obtained at three consecutive past level determination timings. 1a to 31d, and the average value of these amplitude center values is used as a new reference signal level vth at the next level determination timing.

Therefore, even if the DC level of the received digital signal RD changes for some reason, the reference signal level vt follows the change in the DC level as shown in FIG.
h will also change. Therefore, the received digital signal RD can always be decoded according to the optimum reference signal level Vth.

Moreover, in this embodiment, when setting the reference signal level vth, the average of the amplitude center values of past consecutive multiple bits is taken, and this average value is set as the new reference signal level Vth. Even if the signal value of the received digital signal RD temporarily changes significantly due to bit noise or the like, a stable reference signal level can be set by alleviating the influence of this temporary signal change. Therefore, the stability of decoding operation can be improved.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the reference signal level for each bit is set to =I
Although nf is changed at fixed bit intervals, nf may be changed at fixed bit intervals. In addition, the present invention also applies to the value of the number of bits referred to when determining the reference signal level, that is, the number of installed switched capacitors, the configuration of the offset voltage generation circuit, the circuit for determining the center amplitude value, and the analog storage circuit. Various modifications can be made without departing from the gist of the invention.

[Effects of the Invention] As detailed above, the present invention includes an offset value generation circuit that generates a preset offset value based on the amplitude value of a received digital signal, and an offset value generation circuit that generates a preset offset value based on the amplitude value of a received digital signal, and a
a center value calculating circuit for calculating the center amplitude value of the received digital signal by adding or subtracting the offset value to the signal value of the received digital signal; and each time a new center value of the amplitude is calculated by the center value calculating means; The reference signal level output circuit is provided with an analog storage circuit for storing each amplitude center value found in the amplitude and a reference signal level output circuit, and the reference signal level output circuit stores the multiple amplitude centers stored in the analog storage circuit. The average value is determined, and this average value is used as a reference signal level at least at the next level determination point for level comparison with the received digital signal 15'.

Therefore, according to the present invention, even if the DC level of the received digital signal changes, it is not affected by this change, and even if the signal value of the received digital signal suddenly changes temporarily due to noise etc., the effect is removed. This makes it possible to provide a digital signal decoding circuit that can always perform accurate decoding.

[Brief explanation of the drawing]

1 to 4 are for explaining a digital signal decoding circuit according to an embodiment of the present invention, FIG. 1 is a circuit diagram of the circuit, FIG. 2 is a circuit diagram of a polarity inversion circuit,
Fig. 3 is a signal waveform diagram for explaining the operation of varying the reference signal level, Fig. 4 is a signal waveform diagram for explaining the level judgment operation, and Figs. 5 and 6 are respectively conventional digital signal decoding circuits. FIG. 3 is a signal waveform diagram showing the operation of FIG. 10... Offset voltage generation circuit, 11... Power supply,
12...Switch, 13...Polarity inversion circuit, 14.
... Capacitor, 20... Voltage comparator, 30... Switched capacitor circuit, 31a to 31d... Capacitor, 32a to 32d... Charging control switch, 33a
~33d...Discharge control switch, 40a~40d.
...Current amplifier, 50a to 50d...Additional resistor,
60... Adder, 70... Voltage holding circuit, 71...
・Capacitor, 72.73... Switch, 80...
Level comparator, RD...received digital signal, OD/
...Decoded signal, -ΔV, +ΔV...Offset voltage,
vth...Reference signal level. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 4

Claims (2)

[Claims] (1) In a digital signal decoding circuit that compares a received digital signal with a reference signal level in its bit period to determine whether it is "1" or "0", an offset value that is set in advance based on the amplitude value of the received digital signal is set. a center value calculation circuit that adds or subtracts the offset value to the signal value of the received digital signal at each point where the level determination is performed to obtain a center value of the amplitude of the received digital signal; an analog storage circuit that stores the new amplitude center value together with each amplitude center value obtained at a plurality of consecutive past level judgment points each time a new amplitude center value is obtained by the center value calculation means; and a reference level output circuit that calculates the average of a plurality of amplitude center values stored in the digital signal and uses this average value as a reference signal level at least at the next level determination point for level comparison with the received digital signal. Digital signal decoding circuit. (2) The digital signal decoding circuit according to claim (1), wherein the analog storage circuit is constituted by a switched capacitor.