JPH02303362A - Input current detecting circuit and overcurrent detecting circuit for power converter - Google Patents

Abstract

PURPOSE:To reduce the cost by providing an output current detecting means and an operating means for simulating the input current. CONSTITUTION:A power converter inverts power fed from a DC power source 1 into AC power through a switching element circuit, i.e. a single-phase inverter circuit 4, and feeds the inverted power to a load 5. A DC current detector 6 as an input current detecting means, an AC current detector 10 as an output current detecting means, an operating circuit 11 for simulating the input current, and a subtractor 12 are provided, and an ON/OFF signal S for each element Q is provided from a control circuit 9. The operating circuit 11 combines the simulation current for each arm and operates simulation input current for the inverter circuit 4.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a power conversion device that converts, for example, DC power into AC power by controlling switching elements such as transistors on and off, and particularly relates to The present invention relates to an input current detection circuit that simulates the input current from the output current, and an overcurrent detection circuit that detects an overcurrent due to an internal abnormality in a switching element or the like.

[Conventional technology]

Figure 8 shows a case in which the conventional overcurrent detection method in a power conversion device described in, for example, Technical Report (■ Part) No. 162, P. 53, published in January 1980, is applied to a single-phase inverter circuit. FIG.

In the figure, (1) is a DC power supply, which is composed of a DC voltage generation source (2) that generates DC voltage, which is the first form of power, and a capacitor (3) that smooths the voltage. (4) is a single-phase inverter circuit as a switching element circuit, and as shown in the figure, it consists of four arms AU, AX, AV, and AY connected in series and parallel to each other to form a bridge. Transistors QU, QX, QV, QY as switching elements and diodes Dυ, DX, DV, DY connected in antiparallel to these, BU, BX, eV, BY are transistors Q [J to QY on/off drive This is a drive circuit that performs

The input terminal (41) of this single-phase inverter circuit 4)
) is connected to the DC power supply (1). (51 is a load connected to the output terminal (42) of the single-phase inverter circuit, and an AC output current (AC), which is the second form of power obtained by converting from DC, flows through it. (6) is a load connected to the output terminal (42) of the single-phase inverter circuit. A DC current detector serves as an input current detection means for detecting the input current IDC flowing from the power supply (1) to the input terminal (41) of the single-phase inverter circuit (A), ■ is a low-pass filter, and (8) is a comparator , (9) transmits transistor on/off signals su, sx, sv, s to each drive circuit 8O-BY at a predetermined timing according to a series of on/off modes to be described later.
This is a control circuit that sends out y.

Next, the operation will be explained with reference to the waveforms shown in FIG.

Now, each arm AU is in the on/off mode shown in the top row of Figure 9.
When the transistors Qυ~QY of ~AY are on/off controlled, the output voltage VAC applied to the load (town) and the load (51
The output current IAC flowing through the circuit has the waveform shown in the figure, and the DC power from the DC power supply (1) is transferred to the single-phase inverter circuit (4).
This means that it is converted into AC power. The current IX shown in FIG. 9 is applied to each arm AX and AY.

IY flows, and the sonosum IX+IY=IDC becomes the input current from the DC power supply (1) to the single-phase inverter circuit (A).

Here, for example, an abnormality occurs in the drive circuit BY, and the drive circuit BY turns on the transistor QY of the arm AY at time T=TI, which is a period in which an off signal is sent in the normal state in the on-off mode. Suppose a signal is generated. By turning on transistor QY, a short circuit is formed in both arms AV and AY, and an overcurrent due to the short circuit flows from the DC power supply (1) to both arms AV and AY (the waveform thereof is shown by the dotted line in FIG. 9). This overcurrent is naturally included in the input current IDC,
It is detected by the DC current detector (6), and when it exceeds the set value IPR, the output signal A of the comparator (81) rises (at time T
= T2), upon receiving the rising edge of the output signal A, the control n[i
il H (9) sends an off signal to all transistors QU-QY to cut off the current at time T=73, thereby providing overcurrent protection as a single-phase inverter circuit (a).

In this case, the setting value IPf input to the comparator (5)
t is the maximum value of the output current IAC to the load (5)
, , , the margin to prevent erroneous detection during normal operation is set as ΔIPR by the following equation.

IPR= IAC,, 10ΔIPR−・・−・−(11
[Problems to be Solved by the Invention] Since the conventional overcurrent detection in the single-phase inverter circuit (4) is performed as described above, as shown in FIG.
The overcurrent flows simultaneously to other arms AV other than the abnormal arm AY, and in this arm AV, this overcurrent is superimposed on the original output current.

Therefore, even if the comparator detects an abnormality in arm 8Y due to the input current IDC exceeding the set value 11'R, the current IV in arm AV will, in the worst case, be the maximum current value 1v, which is expressed by the following formula: ,. will reach.

IV=,,=IPR+IAC,,X=21AC,,,+
AIP11 -=・(21 As a result, each transistor Q
It is necessary to increase the overcurrent withstand capacity of LI to QY by that amount, and there is a problem that the device becomes large and expensive. In addition, when multiple transistors are connected in parallel to form one arm, the maximum value IAC, □Which ratio of the output current increases substantially, and a short circuit in only one element may become undetectable. It could have happened.

In addition, from another point of view, the DC current detector (6) that detects the input current IDC has the following problems. Namely, the DC current detector (6) usually includes a Hall element CT, etc.
A type using an iron core is adopted, but it is the 9th type.

As shown in the figure, the input current IDC to be detected includes a ripple component with high steepness. Therefore, as the switching frequency of the single-phase inverter circuit (4) increases, the above-mentioned high-frequency ripple of the current causes the DC current detector (
6) The loss occurring in the iron core tends to increase, and in order to prevent overheating due to this, special measures such as making the iron core plate thinner or using an amorphous material are required. ) was expensive.

This invention was made to solve the above-mentioned problems, and includes an input current detection circuit for a power conversion device that can determine the input current from the output current, and an overcurrent detection level that can be set low. The purpose is to obtain an overcurrent detection circuit for a power conversion device.

[Means and effects for solving the problem] The input current detection circuit of the power conversion device according to the present invention includes an output current detection means for detecting the current output from the output terminal of the switching element circuit, and an input current detection circuit that detects the current output from the output terminal of the switching element circuit, and The energization period of each arm determined by each on/off mode is determined, the current of each arm is calculated by simulating that the output current from the output current detection means flows between the energization M, and the simulated current of each arm is synthesized. By doing so, the present invention includes simulated current calculation means for calculating a simulated input current to the input terminal of the switching element circuit.

In general, is it possible to measure the input current with a large ripple component without detecting the input current from the output current? Computationally detects the C flow. As long as each arm is operating normally, the input current detected by this calculation will be equal to the actual input current.

Further, the overcurrent detection circuit of the power conversion device according to the present invention includes input current detection means for detecting the input current to the input terminal of the switching element circuit, and the output of the input current detection circuit and the input current detection means are connected to each other. It detects overcurrent due to abnormality in each arm from the difference in output.

The difference component does not include an output current component as a load, but only an overcurrent component associated with an abnormality in the arm, so it is possible to keep the set value for overcurrent detection low accordingly.

〔Example〕

FIG. 1 is a circuit diagram showing a power converter and its input current/overcurrent detection circuit according to an embodiment of the present invention. In FIG. 1, the same reference numerals as in FIG. 8 indicate the same parts and the explanation thereof will be omitted. 0 [ is an alternating current detector as an output current detection means for detecting the output current IAC flowing through the load (51), (1
1) is the simulated arm current IX from the output of the AC current detector and the on/off signals sx and sy from the control circuit (9).
, IY'', the details of which will be described later in conjunction with the subtractor (12) below with reference to FIG. circuit (output from IX),
This is a subtracter that calculates the difference from "IY" and outputs it to the comparator.

Figure 2 is a circuit diagram showing details of the configuration of the arithmetic circuit (11) and subtracter (12). An analog signal open/close switch that opens and closes the circuit according to the on and off signal output of SY, respectively.
For example, it is configured using a MOS (MOS) run lister.
(+61 is an inverting amplifier with a gain of 1, (17) or 2
0) is a resistor, (21) is a capacitor for noise removal, (
22) is an operational amplifier.

Next, the operation will be explained with reference to the waveforms shown in FIG.

The original power conversion operation of the single-phase inverter circuit (4) is the same as the conventional one, but here, the output current IAC flowing through the load (51) is detected by the AC current detector 00, and this is sent to the arithmetic circuit (11). I'm sending it in. Subtractor I? t(Il
+ separately receives on/off signals SX and SY from the control circuit (9) to the two arms AX and ΔY, and connects them via analog signal open/close switches (14) and (!5) that operate with these on/off signals Sx and SY. Create simulated arm currents x5 and IY8 for both arms. That is, for the arm AX, the polarity of the output current IAC is reversed, and the above output current IAC is output only during the period wi when the on-off signal SX is on, thereby creating a simulated arm current IX.
Similarly, arm AY outputs simulated arm current fY* by outputting output current IAC only during the period when on-off signal SY is on.
By the subtractor (12), this 4! ! , a-arm current IX
"and IY" are added together and the DC current detector (6
) is subtracted and the difference current result is sent to the comparator (to) as a signal ΔI.

Here, the sum of the simulated arm current fX'' and IY8, that is, ix''+rpi=rpc'' becomes the simulated input current, and this simulated input current rDc'', as seen from FIG. ) remains equal to the actual input power IDC as long as it continues to operate normally based on the on/off signals SU~sy. Therefore, assuming normal operation, if the sum of this simulated arm current H" and That is why it is done.

Next, as assumed in the conventional figure 9, arm A
An abnormality occurs in the drive circuit BY of arm Y, and at time T=TI, which is a period in which an off signal is sent in the normal state in the on-off mode, the drive circuit BY
- Assume that an abnormal signal is generated that turns on the run lister QY. In this case, since the arithmetic circuit (11) is operated by the regular on/off signals SX and SY sent from the control a1 circuit (9), even if the drive circuit BY
Even if an abnormal signal is generated, the simulated arm continues to operate as before? It outputs I2 current lx8 and (Y". On the other hand, since the DC current detector (6) detects the actual input current IDC, it naturally also detects the overcurrent component caused by arm AY's 5?! do.

Therefore, the output signal ΔI from the subtracter (12) that calculates the difference between this input current IDC and the simulated input current IDC'' is:
As shown in the lower part of FIG. 3, only the overcurrent component that always accompanies the above 5m is present. As a result, for the setting value PC, which is the detection level of the comparator (81) that detects overcurrent, it is sufficient to look at the margin ΔIPC to avoid false detection during normal operation. That is, IPR = ΔIPR...・
...B) is sufficient, and a low setting value can be adopted. Therefore, the maximum current IV flowing through arm AV due to an abnormality in arm AY is expressed by the following equation.

IV,,X=IPR+IAC,,,=IAC,,X+A
IPR - - - - [4] Therefore, the operation of detecting overcurrent at time T = T2 and cutting off all transistors QU to QY at time T = 73 is the same as in the conventional case, but formula (A) When compared with the conventional equation (2), this maximum current IV,...
is smaller by the value of IAC, , , which shortens the time required for overcurrent detection and current cutoff, reducing the overcurrent withstand capacity required for each transistor QU to QY, and reducing the size of the device. This makes it possible to reduce the cost.

Note that in the above embodiment, when looking at the on/off modes of the transistors QU to QY, for example, regarding the transistors QU and QX that are connected in series, when one is on, the other is always off, and conversely, when one is on, the other is always off. When one is off, the other is always on.

However, in a voltage source inverter, it may be possible to consider a transistor as a switching element to be an ideal switch that operates simultaneously with an on/off signal command, but strictly speaking, these operations require a little time. Therefore, especially if the turn-off time is longer than the turn-on time,
For example, at the same time an off command is given to transistor QU of upper arm 8U, transistor Q of lower arm AX is given an off command.
When an on command is given to X, both transistors Q (J, Q
There is a period when X is on at the same time, and both arms AU and AX
becomes short-circuit-kun. Therefore, to avoid this problem,
While giving an OFF command to the transistor QLI of the upper arm AU, before giving an ON command to the transistor QX of the lower arm ΔX, the transistors Q of both arms ALI and AX are
In many cases, a mode is added in which both U and QX are turned off.

Figures 4 (I) to (■) illustrate the on/off mode and energization status of transistors QU and QX in this case.
I ) is when the polarity of energization is the same as the direction of the vector of the output current ■8C, (IV) (V) (VI) is the opposite case 0 In the figure, the transistor signal is circled. Diodes with no circles indicate that they are receiving an on signal; those without a circle indicate that they are receiving an off signal; those with black diode signals indicate that they are in a bad on state, and those without a circle indicate that they are in an off state. show.

And mode (Il and (■) are both transistors QU
, QX are both receiving off signals.

As can be seen from this figure, even during the period when both transistors QU and QX are off, the output current IAC flowing through the load flows through the diode D[I or DX, which is connected anti-parallel to both transistors QU and QX. As a result, if the arithmetic circuit (11) shown in FIG. 2 is used as is, it will not be possible to accurately simulate the currents in both arms AX and ^Y.

FIG. 5 is a circuit diagram showing the internal illumination structure of the arithmetic circuit (It) taking the above points into consideration. In FIG. 0, (13) to 15) are the same as those in FIG.

(23) is a comparator that determines the polarity of the output current IAC, and when the polarity of the output current (AC) is positive, its output becomes H level. su, sx are logic circuits (24
), and the output signal operates the analog signal open/close switch (14). Similarly, on-off signal SV
, SY are processed by a logic circuit (25), and an analog signal open/close switch (15) is operated by the output signal thereof.

And (241) (25+) is a NOR circuit, (24
2) (252) is an AND circuit, (243) (253)
is an OR circuit, and (26) is an N07 circuit.

Next, the operation when using the arithmetic port n(It) shown in FIG. 5 will be described with reference to the waveforms shown in FIG. 6. The explanation will be focused on the arm AU and the arm X for fjJ. Here, periods Pl, P2 . P3 . Since the logical AND is performed with the output signal from the comparator (23) which makes the output H level when it is positive, as a result, only period P2 of the above results in the analog signal opening/closing switch (1
4) is operated. That is, mode (III) and (
M), the mode in which current flows through the diode OX (I
), select only Cono P2 period, IX" = -IAC
and output it.

As described above, even when there is a mode in which off signals are sent to both arms A (J and AX) at the same time, the logic circuit (
24) by providing a simulated current IX of arm AX.
can be created accurately. Arm AV and AY
Although the explanation will be omitted, the same operation as above is performed, and as a result, an accurate simulated input current IDC'' is obtained.

Also, regarding overcurrent detection when there is an abnormality in, for example, the drive circuit BY in the single-phase inverter circuit (4), the first
As in the case of the embodiment shown in the figures through FIG. 3, high-speed detection is possible.

In each of the above embodiments, the input current IDC to the single-phase inverter circuit (4) is detected by a single DC current detector (6), but the input current may flow from several branches. In such a case, a configuration may be adopted in which the currents in each branch are individually detected and the detected outputs are separately added to form the input current IDC to the single-phase inverter circuit (4).

In addition, as shown in Figure 7, a single-phase inverter circuit (A)
may be divided into two blocks A and B, arms Atl, AX and arms AV, AY, and each block may be provided with the above-mentioned comparator, arithmetic circuit, and subtracter.

Furthermore, in each of the above embodiments, a so-called full-bridge single-phase inverter circuit i (41
The present invention is not limited to this, but can be applied to a so-called half-bridge type in-half, a multiphase inverter, a chopper device, a cycloconverter, and the like. In addition, it is not limited to DC to AC power conversion devices, but also various converter devices that convert AC power to DC power, and so-called active filters, which allow instantaneous power exchange and do not handle active power on the average. It can also be applied to devices.

Further, the switching element is not limited to a transistor, but may also be a GTO, FET, BiMO8, thyristor, etc. Furthermore, a plurality of these switching elements can be used in one
An arm may also be configured.

〔Effect of the invention〕

As described above, in the present invention, the input current of the switching element circuit is simulated based on the output current detection means for detecting the output current of the switching element circuit, the on/off signal to the switching element, and the output signal of the output current detection means. Since a predetermined simulated current calculation means is provided, it is possible to calculate and detect the input current from the output current of the switching element circuit without measuring and detecting the input current itself with a large ripple component at -m, and the current The detection means is simple and inexpensive.

Furthermore, an input current detection circuit consisting of both of the above means and an input current detection means for separately detecting the input current of the switching element circuit are provided, and an overcurrent due to an abnormality in the switching element is detected from the output difference between the two. , it becomes possible to detect only the overcurrent component, and the detection setting value can be kept low to improve the detection speed, and the overcurrent withstand capacity required for the switching element can be reduced accordingly, improving the economic efficiency of the device. .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a single-phase inverter circuit and its input current and overcurrent detection circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a detailed MI configuration of the arithmetic circuit and subtracter in FIG. 1. , FIG. 3 is a waveform diagram for explaining the operation of the above circuit, FIG. 4 is a diagram for explaining the on-off mode in another embodiment, and FIG. 5 is a diagram for explaining the on-off mode in FIG. 4. A circuit diagram showing the detailed MJJ configuration, Figure 6 is the 5th
A waveform diagram for explaining the operation of the circuit shown in the figure, FIG. 7 is a circuit diagram showing another embodiment, and FIG. 8 is a circuit diagram showing a conventional single-phase inverter circuit and its overcurrent detection circuit. FIG. 9 is a waveform diagram for explaining the operation of the circuit of FIG. 8. In the figure, (1) is a DC power source as a source power having a first power form, (41 is a single-phase inverter circuit as a switching element circuit, (41) and (42) are its input terminal and output terminal, respectively, (5) is the load as the load power having the second power form, (6) is the DC current detector as the input current detection means, Oal is the AC current detector as the output current detection means, and (11) is the simulated Arithmetic circuit as current computing means, (12) is a subtracter, AU~
AY is an arm, QU-QY is a transistor as a switching element, IDC is an input current, IAC is an output current,
IDC", IX", and IY" are simulated input currents. The same symbols in each figure indicate the same or corresponding parts. Agent: Patent Attorney Masuo Oiwa IX2IY"6 51 < 3 0 Figure 3 Figure 4 (I) (π) (X) (N) (V) (II) Figure 5 Figure 9 procedural amendment (voluntary) ■Drawing 6 Contents (1) In the 4th page, line 0) In the 7th line of page 15 of the same page, the phrase ``connected in antiparallel'' should be changed to ``connected in antiparallel.'' Correct. 41 Correct the words r-arm AV and AYJ from the 5th line to the 6th line of page 17 to read r 7-arm AYj. Correct. 7 List of attached documents (1) Revised drawing Figure 7 1 copy Figure 7

Claims (2)

[Claims] (1) By providing a switching element circuit consisting of a plurality of arms each having a switching element connected in series or in parallel, and controlling the switching element by sending an on/off signal at a predetermined timing to the switching element according to a series of on/off modes, Power that is extracted from the output terminal of the switching element circuit as load power by converting the source power having the first power form flowing into the input terminal of the switching element circuit into a second power form different from the first power form. In the converter, an output current detection means detects the current output from the output terminal of the switching element circuit, and the energization period of each arm determined by each of the on/off modes is determined at the timing of the on/off signal, and the A simulated input current to the input terminal of the switching element circuit is calculated by simulating the flow of the output current from the output current detection means, calculating the current in each of the arms, and then composing the simulated currents in each arm. An input current detection circuit for a power conversion device comprising simulated current calculation means. (2) An input current detection means for detecting the input current to the input terminal of the switching element circuit is provided, and an abnormality in each arm is detected from the difference between the output of the input current detection circuit according to claim 1 and the output of the input current detection means. Overcurrent detection circuit for power conversion equipment that detects overcurrent due to