JPH02301225A - Data error correction method - Google Patents

Abstract

PURPOSE:To efficiently attain error correction processing by setting a smaller error correction reference as an average error bit number is less and applying error correction processing with a set error correction reference or below. CONSTITUTION:An error bit number is detected at every block, n-block of detected error bit number is stored sequentially and a smaller error correction reference is set with a smaller average error bit number in the block and the error correction processing with the error correction reference to be set or below is implemented as to the received block. Thus, even when the state of a transmission line is worse, a large error correction reference is set to correct lots of error bits and when the state of the transmission line is improved, a small error correction reference is set. Thus, efficient error correction is processed.

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention is a system in which blocks of a fixed pit length are continuously transmitted by wire, wireless communication, broadcasting, etc.
The present invention relates to a data error correction method for correcting data errors by receiving data encoded as a code that can correct errors smaller than a bit.

"Prior art" In Europe, RDS (Radio DataS) is used to transmit data by modulating subcarriers of frequency modulated waves.
system) is in operation. In RDS, one block consists of 26 bits, one group consists of four blocks, and the groups are transmitted continuously. When a bit error occurs in this RDS data due to a transmission path failure, conventionally the error is corrected for up to 1 bit error and 2 bit burst error in 1 block, but if the error is larger than that, the error is corrected. data was being thrown away. The number of bit errors in one block may change from moment to moment depending on the transmission path conditions.
If the condition of the transmission path is poor, it will be impossible to receive data at all. For this reason, the number of error-correctable bits is increased, for example, l
It is possible to enable error correction of up to 5 bits per block. However, in this case, performing 5-pit error correction processing on each block when the transmission path condition improves at C: is inefficient and also reduces the reliability of error correction.

"Means for Solving Problems" According to the present invention, the number of error bits is detected for each block, the detected number of error bits is sequentially stored for n blocks, and the storage state of the number of error bits for these n blocks is Based on this, an error correction standard is set such that the average number of error bits in a block is smaller, and error correction processing less than the set error correction standard is performed on the received block.

``Effect'' Therefore, when the transmission path condition is bad, the average number of error bits in a block increases, a large error correction standard is set, and a large number of error bits can be corrected, and the more data can be used without being discarded. can. Moreover, if the transmission path conditions are good, the average number of error bits in a block will be small, and a small error correction standard will be set.
Error correction processing is performed efficiently, and error correction can be performed more reliably than when error correction processing is performed using a large error correction standard for data with few errors.

``Embodiment'' It is assumed that each block has, for example, 26 bits, and is a code capable of correcting, for example, 5-pit errors.

The number of error bits P (0≦P≦5) is detected for each block, and the number of error bits P is transferred to the buffer B for each detection.
Store to 0. Buffer B prior to that memory. ,B1
．． . . . The contents of B, , B, are sequentially transferred to the adjacent buffers B1* B2# . . . B91A (on the right side in the figure). Also buffer B. Each time the number of error bits P is stored, the block number counter BC is incremented by one. The initial value of the block number counter BC is set to 0.

If the value of block number counter BC is below IOB, buffer B. Look at the number of error bits P each time you memorize,
The corresponding counter Cp in the counter C8-05 is incremented by 1. In other words, if the number of error bits P is 0, counter C6 is incremented by 1, if P is 1, counter C1 is incremented by 1, and P is 2.
In the case of , the counter C2 is incremented by 1, and the same goes for the rest.

If the value of block number counter BC is 11 or more, buffer B is used. Each time the data is stored in buffer B, the number of error bits P is checked and the corresponding counter Cp in counters C6-C5 is incremented by 1. The corresponding counter C9 in ~C5 is incremented by -l.

When the block number counter BC becomes 10 or more, the error bit number P is sent to the buffer B. Each time it is stored, counter C3
- Add each count value of C5 in order from the one with the smallest number of error bits, and each added value C3lco+C11CO"CI"C2
+... becomes a predetermined number, for example 8 or more, the counter Ci is determined. For example, C3=2°C1=3, C2=
2, C3=1 tc4=l IC5=1(7),
2+3+2+1=8, and when C3 is added, it becomes 8 or more, so C3 can be found as the counter Ci. The i of this counter Ci, ie, 37a in the above example, is set to the error correction standard.

Error correction processing for the set error correction standard i bits or less is performed for the next received block.

According to this configuration, when the transmission path condition is bad and the average number of error bits per block is large, the counter C3-C
For example, the count value of C4 and C5 in 5 increases, col,
The count value such as t cle C2 becomes 0 or small, and i of the counter Ci becomes larger than the predetermined number 8 by addition, and the set error correction standard i becomes large, making it possible to correct many errors, and the data You can use it effectively without throwing it away.

Furthermore, as the transmission path condition improves and the average number of error bits per block decreases, the count values of C8 and C1 in counters C6-C5 increase, and the count value of counter Ci increases to a predetermined number of 8 or more by addition. As i becomes smaller, the error correction standard i that is set becomes smaller, and error correction processing is performed more efficiently, and moreover, error correction can be performed more reliably than when the error correction standard i is large.

In the above, the error correction standard was determined from the number of error bits before 10 blocks, but this number of blocks can be arbitrarily selected.

``Effects of the Invention'' As described above, according to the present invention, the smaller the average number of erroneous rebits, the smaller the error correction standard is set, and the error correction processing is performed below the set error correction standard. If the condition of the transmission path is poor, the error correction standard becomes larger, and more error corrections are performed, and data is effectively used. If the transmission path condition improves, the error correction standard becomes smaller, and error correction processing is performed more efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a buffer and counter used in the present invention.

Claims (1)

[Claims] (1) In a data error correction method in which blocks of a fixed bit length are transmitted consecutively and each block receives data with a code that can correct errors of P bits or less and corrects data errors, for each block. Detect the number of error bits in the block, sequentially store the detected number of error bits for n blocks, and from the storage state of the number of error bits for these n blocks, the smaller the average number of error bits in the block, the smaller the error correction standard. A data error correction method in which the received block is subjected to error correction processing that is less than or equal to the set error correction standard.