JPH02300841A - Microprocessor and data processor using the same - Google Patents

Abstract

PURPOSE:To eliminate the need for a memory cycle for the transfer of the PC value of a coprocessor instruction by providing a program counted value holding means (PC queue) where the PC value of the coprocessor instruction is held in preparation for the occurrence of an exception at the time of executing the coprocessor instruction. CONSTITUTION:Coprocessors 11 and 12 execute arithmetic operations in accordance with the commands transferred from a microprocessor 10. When an exception occurs at the time of executing operations, an exception processing handler is started. In this handler, exception information is read out from coprocessors 11 and 12 and its contents are checked, and the PC value of the coprocessor where the exception occurs is read out from the main processor 10 as necessary or the entry number of the PC queue corresponding to the command which causes the exception is read out from the coprocessor and the PV value of the coprocessor instruction which causes the exception is read out from the PC queue of the main processor 10 based on this number, and the coprocessor instruction which causes the exception is specified. Thus, the operation can be instructed to the coprocessor instruction with one memory cycle.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention has a high-speed coprocessor interface,
The present invention relates to a microprocessor capable of transferring commands to a coprocessor in fewer bus cycles and executing coprocessor instructions at high speed, and a data processing device using the microprocessor. Furthermore, the present invention relates to a microprocessor and a data processing apparatus using the microprocessor that can specify the program counter (1'C) value of the coprocessor instruction that generated the exception when an exception occurs during execution of the coprocessor instruction. [Conventional technology] The conventional microbroseno 9 has one processor (Main1
In the data processing device used as 'processing 1Jnit (hereinafter referred to as MPIJ), MP[l performs integer operations and floating point operations are performed by a dedicated coprocessor, which is similar to -IIIQ. For example, a data processing device using a microprocessor as a main processor and various floating point processors as co-processors is described in [Another Interface, Numerical Processor-1 Publishing, 1987. In this data processing device, various measures have been taken to share instructions between a main processor and a coprocessor. Fig. 40 shows a conventional data processing device using a microprocessor and a coprocessor. An example of a configuration is shown below: MPLI 201 that controls the entire device and FPU (Floating-poir+tProc) that is a coprocessor.
essing unit) 202, a memory system 203 for storing instructions and data, and a clock generator 204 for supplying a clock CL to the entire device.
5.216 etc. In addition, the signal line 21
0 is for clock CL, 1δ line 211 is for signal BSI
, A.S.W. DS insult, l? /-Mackerel, Route 13 212 is signal CPST
O:2, line 13 213 transfers the signal cpoc fence, signal line 214 transfers the (δ DCI), and the signal &!
215 is address bus AO:3L! =, the signal vA2
16 u: Thetahas DO: 31 to be used respectively. The value diagram shows MPI+201 when executing a coprocessor instruction in the data processing device shown in FIG.
Command, operand and Cobb 1 from to PPIJ202
This is a timing chart when transferring one setter instruction to the PC (!). In the data processing ViT1 using this conventional microbroseno 4] as the ?1PU 201, the ?1PU 201 fetches and decodes the coprocessor instruction, and this decoding According to the result, the command, operan]' and the PC value of the coprocessor instruction are all transferred via the data bus 216. In the example shown in the timing chart of Figure 1, it takes one memory cycle to transfer the command and one memory cycle to transfer the operan 1'. 2 memory cycles (1 memory cycle each for upper and lower data)
, it takes one memory cycle to transfer the pc value, which is a total of 4 memory cycles and 9 cycles. Cobb C with commands and operands like this
Regarding the method of transferring the PC value of l processor instruction, refer to 68881/MC688B2Floating-Po
int Co-p “ocsssor 1layer’s
Manual'. n0TOROLA, rNc,, PRENTI(j!
HALL, 1987.5ecNon7, or [
It is described in detail in the separate volume Interface, "Numerical Processor," CQ Publishing, 1987, pp. 194-210. Also, rather than the FPII fetching and decoding coprocessor instructions and forwarding coprocessor commands,
Conventional data processing devices employ a method in which a coprocessor directly fetches, decodes, and executes coprocessor instructions! Two proposals have been proposed. For example, in a data processing device that uses Intel's microprocessor 1808G as Mr'll, Cobb

[]
The sesona 18087 constantly monitors the bus, and when a coprocessor instruction is output to the Hass, the Cobb IJ processor fetches it, decodes it, and executes it. This method is described in, for example, [Separate Volume Interface, "Numerical Processor", C-Kuchi Publishing, 1987, pp. 1]. 60-74. [Problem to be Solved by the Invention 1] In a data processing device using a conventional microb 11 setter as Mllt+, as shown in the timing chart in the value diagram, when MPtl instructs the coprocessor to perform an operation for a coprocessor instruction, Cobb Cl processor instruction P
Because the C value is also transferred, many memory cycles are required to instruct the operation, which degrades the performance of the entire device.The PC value of the coprocessor instruction is not directly necessary for the execution of the coprocessor instruction. This is transferred in case an exception occurs during the execution of a coprocessor instruction, and in most cases it is not used and is wasted. [Decoding]
The data processing device used as
Instruction prefetch kiff similar to. - It is necessary to provide an instruction decoder and an instruction decoder, which increases the hardware complexity of the coprocessor. Also, the same Kobrose,
When multiple processors are connected and operated in parallel, arbitration between coprocessors is required to control which MPII executes which coprocessor instruction. Regarding the problems with data processing devices that employ this method, see Miyuki Hanakaku, ``At the dawn of the 32-bit era, the full scale of floating-point arithmetic has arrived'', Nikkei Electronics 425, 1987. July 13th issue p.
p, 123-138 J. [Means for Solving the Problems] A microprocessor used as a main processor of a data processing device of the present invention has a coprocessor instruction pc(a
It has a PC queue (program counter value holding means) that holds . In addition, this PC key ], - can hold the PC value of multiple coprocessor instructions, and when fetching and decoding a coprocessor instruction and instructing the coprocessor to perform an operation, the coprocessor Calculate the entry number of the queue that stores the PC value instead of the PC value of the instruction Jfi
It has means for transferring the command concatenated with the indicator to the coprocessor. Furthermore, when multiple coprocessors are connected, the PC of the coprocessor command is used to identify the coprocessor to which the command is transferred.
(Cobroceso →) identifier (CPID) which is a criterion for determining whether or not to transfer the direct data to the coprocessor is held in the processor status word (PSW). [Operation] In the data processing device of the present invention, the main processor fetches and decodes a coprocessor instruction, and generates an operation indicator to be transferred to the coprocessor according to the result. If the value of the coprocessor identifier (CI'1Il) in the processor status word (1"; W) is "001", the PC value of the coprocessor instruction is
is retained. The entry number of the PC queue holding the PC value, the operation indicator, and the coprocessor identifier in the processor status word are concatenated and transferred as a command to the coprocessor in a single memory cycle. If the value of the coprocessor identifier (CPID) is other than "001", the PC value of the coprocessor instruction is also transferred to the coprocessor after the command is transferred. The coprocessor executes operations according to commands transferred from the microprocessor of the present invention. When an exception occurs during the execution of an operation, the exception handler is activated.The exception handler is read from the coprocessor, its contents are examined, and if necessary, the exception information of the coprocessor that generated the exception is The PC value is read from the main processor or the PCC key-entry number corresponding to the command that caused the exception is read from the coprocessor and the PC of the coprocessor instruction that caused the exception.
(A is read from the PC queue of the main processor based on the number, and the coprocessor instruction that caused the exception is identified. [Embodiments of the Invention] The present invention will be described in detail below based on the drawings showing the embodiments. (1) "Data processing device using the microprocessor of the present invention" Fig. 1 is a block diagram showing an example of the configuration of a data processing device using the microprocessor of the present invention. Main processor (Mill) 1
0, two coprocessors (first F
12, a memory system 13 that stores instructions and data, an interrupt control circuit 15 that controls interrupts to MPU10, a clock generator 14 that supplies a clock that determines the timing of the entire device, etc. The MPU 10, the first FPU II, the second FPU 12, and the memory system 13 are connected to a 64-bit data bus DO;
It is connected by a signal line 1) and a 32-bit address bus AO:31 (signal vA2). MPtllO and memory system 13 use a 32-bit instruction bus 10:31
(FF line 3) is also connected. Furthermore, the entire device is coupled by a control signal vA4. 1 old 0 operates as a bus mask for the entire device, and a signal is always output from -puto to the address bus AO:31[21. 11puto is the memory system 13^
・Address bus A O: 31 (outputs the address through 21, memory system 13 instruction bus IO: 3H3
1 to 1ffi to fetch and execute the instruction. M
When PulO executes an instruction, it uses the data bus D if necessary.
Operands are input and output to and from the memory system 13 through Ox63 (xi). Also, when a coprocessor instruction is decoded, a command is sent from npuio to the first PPLIII or second FPU12 through the address bus AO:3021, and the operation is performed using pputt or 12. When performing calculations on FPU II or 12, if necessary?
1PUIO inputs and outputs operands through data bus DO: 63 (11).
Whether to execute on II or second FP [I12 is determined based on the coprocessor identifier (CPIO) held in hPulO at that time. CPID is software j
・B can be changed by software, and by rewriting CPl[l, MPIIIO changes the coprocessor instruction to the 1st F.
It is also possible to execute by either the PUII or the second FPU 12. Also, FPU II. If an exception occurs during the execution of an operation in 12, the program counter (PC) of the coprocessor instruction that generated the exception.
To specify the value, a register is provided in Ml'υ10 and FPυ12 to hold the PC value of the coprocessor instruction. MPIJIO has a PC queue (first FPc) that holds multiple pc values of coprocessor instructions to be executed in the first FII
21), and the second FPU 12 has a second FPU 12 that holds the coprocessor instruction pc(a) to be executed by the second FPtl12.
There is a PC22. The PC value held in the second FPC 22 is transferred from npuio. The first of these. The second Fl)C21 and 22 are the above-mentioned registers. The PC value held in the first FI)C21 or the second FPC22 is used when the corresponding coprocessor instruction causes an exception. When a coprocessor instruction causes an exception in FPUII (12), first the FPUII (12)
Therefore, the υ1 inclusion control circuit t5 is requested to include the υ1 inclusion.
J! The I interrupt control circuit 15 requests the MPU10 to perform interrupt processing in accordance with the interrupt request from the FPU II (12). This starts the interrupt handler. In the interrupt processing handler, the exception information is read from ppull (12), and according to the contents, the exception information is
11c(it!) held in 22 is read out and exception handling is performed.Hereinafter, the instruction system 9 processing mechanism and processing power method G of the microprocessor of the present invention will be described in more detail. 1. The instructions of the microprocessor of the present invention have a variable length in units of 16 bits, and there are no odd-byte length instructions.The microprocessor of the present invention shortens frequently used instructions. For example, for a 2-operand instruction, it basically has a configuration of "4 bytes" + "extension part", and all at-1 non-singing There are two formats: a general format in which 1. modes can be used, and a shortened format in which only the frequently used command addressing modes 1 to 1 can be used. A schematic diagram of the instruction format of the processor is shown.
-The meanings of the symbols appearing in the mat are as follows. 12 The part where the operand code is entered [ia: The part where the operand is specified in the 8-bit addressing mode of the 8-bi-y (-ship type) Sh: The part where the operand is specified in the 6-bit abbreviated addressing mode Rn = On the register file As shown in Figure 11, the partial formant that specifies the operand of by register number is LS on the right side.
It is on the B side and has a high address. The instruction 1-mat cannot be determined without looking at the two bytes of address N and address N+1, but this is because it is assumed that instructions are always fetched and decoded in units of 16 bits (2 bytes). In the microprocessor instructions of the present invention, in any formant, the h or Sb extension of each operand always immediately follows the halfword containing its Ea or sh base. This overrides any immediate data or extensions of the instruction implicitly specified by the instruction. Therefore, for 4 or more hides (in the D instruction, the operation code of the instruction may be divided by the extended part of Ea. Also, as shown in V below, in the multi-stage indirect mode), an extended part is added to the extended part of Ha. Even if the instruction operation code is specified, it has priority over the next instruction operation code. For example, 1 for the first half word! Consider the case of a 6-byte instruction that includes al, the second halfword includes [Ha2, and goes up to the third halfword. Since the multi-stage indirect mode is used for Eal, it is assumed that the multi-stage indirect mode extension part is also provided in addition to the traditional extended part. In this case, the actual instruction bit pattern is
Halfword (including the base part of Eat), extension part of Eal', l! The multi-stage indirect mode extension of al, the second halfword of the instruction (including the basic part of Ea2), the extension of Ea2, and the third half-1' of the instruction. (2,1) r Shortened 2-operand instruction-1 FIG. 12 is a schematic diagram of a shortened 2-operand instruction. This format includes an L-format in which the source operand side is a memory, and an S-format in which a destination operand side is a memory. In L-format, sh represents a source operand designation field, Rri represents a destination operand register designation field, and RR designates the sh operand size. The size of the destination operand placed on the register is fixed at 32 bits. The size of the register side and the memory side becomes different,
Sign extension is performed when the size on the source side is small. 5-forsaL, sh is the destination operand specification field, Rn is the source operand register specification field 1', and l is the sh operand F'9.
Represents the size specification. The size of the source operand placed in the register is fixed at 32 bits. If the sizes on the register side and memory side are different and the size on the source side is large, overflow portions are truncated and an overflow check is performed. (2, 2) r-ship type 1-operand instruction" Figure 13 shows the general format of the 1-operan 1" instruction) (Gl-f
FIG. Open is a field specifying the operand size. Note that in some G l -f orwaa instructions,
There are extensions other than the extension of Ea. There are also instructions that do not use questions. (2, 3) r-General form 2-operand instruction" FIG. 14 is a schematic diagram of the general form format of the 2-operand instruction. This format includes instructions that have a maximum of two operands in general addressing mode specified by 8 bits. The total number of operands itself may be three or more. EaM is a destination operand specification field, iIM is a destination operand size specification field, EaR is a source operand specification field, and RR is a source operand size specification field. Some G4orsat instructions have extensions in addition to the EaM and EaR extensions. FIG. 15 is a schematic diagram of the formant of a short branch instruction. cccc is a branch condition specification field, and disp:8 is a displacement specification field from the jump destination. In the microprocessor of the present invention, when specifying displacement using 8 bits, the specified value in the bit pattern is doubled to obtain the displacement value. (2, 4) "r Addressing Mode" The method for specifying the addressing mode of the microprocessor instructions of the present invention includes a shortened form in which registers are specified in 6 bits/1, and
There is a 1m type specified by 8 pits 1. If an undefined addressing mode is specified, or if a combination of adreno song modes that is semantically unreasonable is specified, a reserved instruction exception will occur in the same way as when an undefined instruction is executed. occurs and exception handling is triggered. This applies when the destination is in immediate mode, or when immediate mode is used in the addressing mode specification field that should involve address calculation. The meanings of the symbols used in the formats shown in FIGS. 16 to 26 are as follows. Rn=Register specification (Sh): Specification method in the 6-bit abbreviated addressing mode (Ea): Specification method in the 8-bit general addressing mode. Showing 8 (2, 4
, 1) r1 Addressing Modes The microprocessor instructions of the present invention support various addressing modes. Among these, the basic addressing modes supported by the microprocessor of the present invention include register direct mode, register indirect mode, register relative indirect mode, immediate value mode, absolute mode, PC relative indirect mode, stack pop mode, and stack pop mode. There is. In register direct mode, the contents of the register are used as operands. The formant is shown in Figure 16.
Rn indicates the number of a general-purpose register or FPυ register. In the register indirect mode, the operand is the contents of the memory whose address is the contents of the general-purpose register. The format is shown in FIG. In the figure, Rn indicates the number of a general-purpose register. The register relative indirect mode is divided into two types depending on whether the displacement value is 16 bits or 32 bits. The operands are the contents of the memory whose address is the sum of the contents of the general-purpose register plus 16 pins or 32 bits of displacement. The format is shown in FIG. In the figure, 1lri indicates the number of a general-purpose register. disp:16 and disp:32 indicate a 16-bit displacement value and a 32-bit displacement value, respectively.The displacement values are treated as signed. In the immediate mode, the bindpakun specified in the instruction code is treated as a binary number and used as an operand. The format is shown in FIG. 19, where 1m5data indicates an immediate value, and the size of i-1-data is specified in the instruction as the operand size. Absolute mode indicates whether the address value is represented by 16 bits or 3
It is divided into two types depending on whether it is indicated by 2 bits. Each operand is the contents of a memory whose address is a 16-bit or 32-bit focus pattern affirmed in the instruction code. Formatsu 1 is shown in FIG. In the figure, abs:16 and abs:32 indicate 16-bit and 32-bit address values, respectively.
If the address is indicated by , set the specified address value to 3
Sign extend to 2 bits. PC relative indirect mode has a displacement value of 16.
It is divided into two types depending on whether it is Binoto or 32 bit. In each case, the contents of the memory whose address is the value obtained by adding a 16-bit or 32-bit displacement value to the contents of the program counter are used as operands. The format is shown in FIG. In the figure, disp:
16 and disp:32 indicate a 16-bit displacement value and a 32-bit displacement value, respectively.The displacement values are treated as signed. The value of the program counter referenced in PC relative indirect mode is the start address of the instruction that includes the operand. When the value of the program counter (PC) is referenced in the multi-stage indirect addressing mode, the address at the beginning of the instruction is similarly used as the PC-relative reference value. The stack pop mode uses the contents of the memory whose address is the contents of the stack pointer (SP) as the operand. After accessing the operand, SP is incremented by the operand size. For example, when handling 32-bit data, SP is updated by +4 after operand access. It is also possible to specify stack pop mode for operands of size B, H, and D, each with Sll +
1. +2. Updated by +8. The format is shown in FIG. 22. If the stack pop mode has no meaning for the operand, a reserved instruction exception is generated. Specifically, the reserved instruction exceptions are the write operand, read-◎dify-wr
This is the stack pop mode specification for the ite operand. In stack bush mode, the operand is the contents of the memory whose address is the contents obtained by decrementing the contents of SP by the operand size. In star mode, SP is decremented before operand access. For example, when handling 32-bit data, SP is updated by -4 before operand access. 8°16.6
It is also possible to specify stacked bush mode for operands with a size of 4 pints, and each SP is -L-2.
, -8 is updated. If the format is shown in FIG. 23, and the stacked bush mode has no meaning for the operand, a reserved instruction exception is generated. Specifically, the reserved instruction exception is the read operand, read-modify-w
This is the stack bush mode specification for the rHe operand. (2, 4, 2) r multi-stage indirect addressing mode”
Even complex addressing is broken down into combinations of addition and indirect references in W-line fishing. Therefore, if addition and indirect reference operations are given as addressing primitives and they can be combined arbitrarily, any complex addressing mode can be realized. The multistage indirect addressing mode of instructions of the microprocessor of the present invention is based on this idea. Complex addressing modes require data references between modules or Artificial Intel.
When specifying the multi-stage indirect addressing mode, there are three types in the basic addressing mode specification field: register-based multi-stage indirect mode, pc<-space multi-stage indirect mode, and absolute-based multi-stage indirect mode. Specify one of the specification methods. The register-based multi-stage indirect mode is an addressing mode in which the value of a general-purpose register is used as a base value for multi-stage indirect addressing to be expanded. The format is shown in FIG. In the figure, Rn indicates the number of a general-purpose register. The PC-based multi-stage indirect mode is an addressing mode in which the value of the program counter is used as the base value for multi-stage indirect addressing to be extended. The format is shown in FIG. The absolute base multi-stage indirect mode is an addressing mode that uses zero as the base for multi-stage indirect addressing. The format is shown in FIG. The extended multi-stage indirect mode specification field has 16 bits as a unit, and this is repeated an arbitrary number of times. Addition of displacement,
Index register scaling (Xll
X4. X8) and performs addition and memory indirect reference. The format of the multi-stage indirect mode is not shown in FIG. Each field has the meaning shown below. 0: Continuation of multi-stage indirect mode E=1 8 Address calculation end tap -=> address of opera
ndI・0: No memory indirect reference tap+disp+Rx*5cale==>tap■・
l: Men with memory indirect reference [tmp + disp + Rx reference 5ca
le] ==> tsp M=0: Use <RX> as index-1: Special index <RX>・0 Do not add index value (Rx・0) <RX>-1 Use program counter as index value Use (Rx=PC) <Rx>-2+ reserved 11=(]: Multiply the value of 4-bit field d4 in multi-stage indirect mode by 4 to obtain a displacement value, and add this. d4 is treated as signed. , regardless of the size of the operand, it is always multiplied by 4 and used.=i: di specified in the extension part of multi-stage indirect mode
spx (16/32 bits) is used as a displacement value, and the size of the extension section to which this is added is specified in the d4 field. d4=0001 dispx is 16 bits d4・0
010 dtsp has 32 bits, txx; index scale (scale = 1/2/4/8). Intermediate 1a after completion of processing (
An undefined value is entered as tap). Although the effective address obtained by this multi-stage indirect mode is an unpredictable value, no exceptions occur. To specify scaling for the program counter, line
<(Do not do this. Figures 28 and 29 show variations in instruction formats in multi-stage indirect mode. Figure 28 shows variations in whether multi-stage indirect mode continues or ends. Figure 29 indicates the variation in size of dis- brace men]. If a multi-stage indirect mode with an arbitrary number of stages can be used, there is no need for the compiler to differentiate between cases according to the number of stages, which has the advantage of reducing the burden on the compiler. This is because even if the frequency of indirect references is very low, the compiler must be able to generate correct code without fail.For this reason, an arbitrary number of stages is possible in terms of format. The microprocessor commands of the present invention include coprocessor instructions that are executed on the FPU II. After the coprocessor instructions are decoded by the MPIIIO,
The command is forwarded to FPtll (12) and the FP
Executed in UII (12). The command has the format shown in FIG. 30, and is transferred using the lower 20 bits of address bus 2, as shown in FIG. The command is composed of an FPυ command field, a PCID field, and a CP[D field. FPI
The J instruction field is an operation specifier indicating the content of the instruction for FPUII (12). The PCIO field of the coprocessor instruction held in the UlO
FPIIIm (12
), the PC value of the coprocessor instruction that caused the exception is stored in multiple PCs held in MPU10.
This is a number to choose from. CPIO is MPtllO
This is a number to distinguish each FPu when multiple FPtl are connected to MPLIIO. The FPU instruction has formants shown in FIGS. 32 to 34. Memory/FPυ register instruction (H-FR
instruction), IIPυ register/FPu register instruction (
Gl? The instruction consists of an operation code field 1' and an FPLI register number field (PR), and has a former /1 shown in FIG. FPII Regisc・FP
The IJ register instruction (P1?-, PR instruction) consists of an operation code field and two FP[I register number fields (Fill and FI12).
It has the format shown in FIG. The zero operand field has the format shown in FIG. (4) [Functional block configuration] Figure 2 shows the microprocessor of the present invention (MPU in Figure 1).
10) is a block diagram showing an example of the configuration. Functionally, the inside of the microprocessor of the present invention can be roughly divided into an instruction fetch section 51, an instruction decoding section 52, and a P
It is divided into a C calculation section 53, an operand address calculation section 54, a micro ROM section 55, a data calculation section 56, and an external bus interface section 57. In FIG. 2, there is also an address output circuit 58 that outputs addresses to the outside, a data input/output circuit 59 that outputs data to the outside, a control signal input/output circuit 60, and a command input circuit 61 that inputs instruction codes. It is shown separately from each of the above-mentioned functional blocks. (4, 1) r Instruction Fetch Unit” The instruction fetch unit 51 includes an instruction cache, an instruction queue, a control unit thereof, and the like. They determine the address of the next instruction to be fetched and fetch the instruction from the instruction cache or external memory system I3. It also registers instructions in the instruction cache. The address of the next instruction to be found is calculated by a dedicated counter as the address of the instruction to be input into the instruction queue. When a jump occurs, the address of a new instruction of the jump target is transferred from the PC calculation unit 53 or the data calculation unit 56. When an instruction is fetched from an external memory, the address of the instruction to be processed is output from the address output circuit 58 to the outside through the external bus interface section 57, and the instruction code is fetched from the instruction input circuit 61. Among the buffered instruction codes, instruction decoding section 5
In step 2, the next instruction code to be decoded is sent to the instruction decoder 5.
Output to 2. (4, 2) r Instruction Decode Unit” The instruction decode unit 52 basically decodes instruction codes in units of 16 bits (halfwords). This instruction decoding section 52 includes an FHW decoder that decodes the operation 3 code included in the first halfword, and a second . Third
It includes an NFIIN decoder that decodes the operation code included in the halfword, and an addressing mode decoder that decodes the addressing mode. A second decoder that further decodes the outputs of the FHW decoder and NFH-decoder to calculate the micro Roli entry address, a branch prediction mechanism that performs the branch Y-side of a conditional branch instruction, and a vibe line conflict when the operand address totals 11. Address calculation function checking machine (1) 1 to check address calculation including t1. Le. The instruction code input from the instruction fetch unit 51 is decoded by 0 to 6 bytes per 1 block. Among the decoding results, information related to the calculation in the data calculation unit 56 is output to the 7420120M unit 55, information related to operand address calculation is output to the operand address calculation unit 54, and information related to pc calculation is output to the IIc calculation unit 53. Ru. The instruction decoding section 52 decodes both main processor instructions executed in the microprocessor of the present invention and coprocessor instructions executed in the coprocessor. (4, 3) Micro Decoder 7420120 The M section 55 stores a micro decoder in which various micro program routines for controlling the data calculation section 56 are stored. ON, micro sequencer,
Includes microinstruction decoder, etc. The microinstruction is −
? It is read out from the micro OM once per clock. In addition to the sequence processing indicated by the microprogram, the microsequencer accepts exception 1 interrupts, trap (all together referred to as EXT) processing, and test interrupts using hardware. The micro ROM 55 also manages the store buffer. The micro ROM 55 contains flag information based on interrupts and operation results that do not depend on instruction codes, and a decoder 2.
The output of the instruction decoding unit 52 such as the output of is inputted. The output of the microdecoder is mainly output to the data calculation unit 56, but some information, such as information on canceling previous processing due to execution of a jump instruction, is also output to other functional blocks. (4, 4) r Operand Address Calculation Unit The operand address calculation unit 54 is hard-wired controlled by information related to operand address calculation output from the address decoder of the instruction decoding unit 52, etc. The operand address calculation unit 54 performs most of the processing related to operand address calculation. A check is also made to see if the address of the memory access for indirect memory addressing and the operand address fall into the memory mapped IlotJi area. Also, Kobrose
The operand address calculation for the second instruction is also performed. The address calculation result is sent to the external bus interface unit 57. The general-purpose registers and program counter information necessary for address calculation are input from the data calculation unit 56. Memory When performing indirect addressing, the address output circuit 58 outputs the memory address to be referenced externally through the external bus interface section 57, and the indirect address value input from the data input/output section 59 is used for instruction decoding.
By passing through the do part 52 as it is, the hum-notch is performed. (4, 5) rPC calculation unit” The PC calculation unit 53 receives the p output from the instruction decoding unit 52.
It is hardwired and controlled by information related to c calculation,
PC of the instruction (0 to calculate i) The instructions of the microprocessor of the present invention are variable length instructions, and the length of the instruction cannot be determined until after the instruction is decoded.PC calculation unit 5
3 generates the pc value of the next instruction by adding the instruction length output from the instruction decoding unit 52 to the pc value of the instruction being decoded. The calculation result of the PC calculation unit 53 is output as the pc value of each instruction together with the decoding result of the instruction. (4, 6) r Data calculation unit The data calculation unit 56 is controlled by a microprogram, and in order to realize the function of each instruction according to the microinstruction that is the output of the microROM, 1. The necessary calculations are performed using the register file and the calculation unit Execute with . When the operand to be operated on by the instruction is an address or an immediate value, the address or immediate value calculated by the operand address and if arithmetic section 54 is inputted to the data operation section 56 through the external hash interface section 57 . Furthermore, if the operand to be operated on by the instruction is data stored in the memory, the bus interface unit 57 outputs the address calculated by the address calculation unit 54 from the “?” address output circuit 58, thereby fetching the address from the memory system 13. The resulting operands are input from the data input/output circuit 59 to the data calculation unit 56. For coprocessor instructions, the data IF4 calculation unit 56 transfers necessary commands and operands according to the coprocessor protocol determined according to the microprogram. External hash I/F unit 57, address output circuit 58, data input/output circuit 59, control signal input/output circuit 60, etc. When it is necessary to access the memory system 13, the microprogram By outputting the address from the address output circuit 5B to the outside via the column bus interface section 57 according to the instruction of
One piece of data is fetched through the data input/output circuit B59. When loading data into the memory system 13, an address is output from the address output circuit 58 through the external bus interface section 57, and at the same time the data input Data is output from the output circuit 59 to the MPUl0(unit).In order to efficiently perform operand store, the data calculation unit 5
6 has a 4-byte store buffer. When the data calculation unit 56 obtains a new instruction address by executing jump instruction processing, exception handling, etc., the data calculation unit 56 outputs this to the instruction fetch unit 51 and the PC calculation unit 53. FIG. 5 shows the data calculation section 5 of the microprocessor of the present invention.
6. 5 is a block diagram of a detailed configuration of a portion of a micro ROM section 55 and a portion of a bus interface section 57. FIG. Inside the data calculation unit 56, there is a register file 103 consisting of general-purpose registers and working registers. Processor status word (PSW) consisting of processor status bins and flags 104. ^Data operation circuit consisting of LU, barrel shifter, etc. 8105. Alignment circuit rotates data in bytes and aligns it in words when exchanging data with memory 106.8 4-byte - 8-byte converts data between Hyde's external bus and 4-byte internal bus Conversion circuit 107. S1, the internal data bus
A bus, an S2 bus, and a PC queue 21 that holds up to four PC values of a coprocessor instruction when a command is transferred to a coprocessor according to a DO bus coprocessor instruction is provided. The main arithmetic units are connected to each other by the ST bus, S2 bus, and DO bus.
Processes microinstructions in one clock cycle. The PC value of the coprocessor instruction held in the PCC key 21 indicates that the coprocessor instruction overflows. It is read and used by the exception handler when an exception such as underflow or division by zero occurs. Also PC
Values are cyclically written into the four entries of the queue 21, and the fifth write directly overrides PO2 of the first written entry. This allows the PC
The latest four lJC values are always held in the queue 21. The configuration of the PS1 value 94 is shown in the schematic diagram of FIG. The PSW 104 includes an operation mode field indicating the processor operation mode and an IM field indicating the external interrupt mask level.
It consists of a field As, a CPID field used to specify the destination coprocessor when transferring a command to a coprocessor, and a flag field that changes depending on the result of calculations such as carry and zero flags. (4, 7) r External bus interface section, 1 The external bus interface section 57 controls communication at the input/output pins of the microprocessor of the present invention. All memory accesses are performed in clock synchronization and can be performed in a minimum of two clock cycles. The external bus interface section 57 has a data cache, and if successive operands hit the data cache, no memory access is performed. Writing operands is done to both the data cache and memory. When the coprocessor writes an operand to memory, the operand is read through the data input/output circuit 58 and the contents of the data cache at the same address are changed. A request for access to memory is made with a command fair of 1,000 copies 51.
It is generated independently from the Aviles calculation unit 54 and the data calculation unit 56. External bus interface unit 57 arbitrates these memory access requests. Furthermore, the size of the data bus connecting the memory and the microprocessor of the present invention is 64
When accessing data located at a memory address that straddles a bit (double word) aligned boundary, the crossing of the boundary within this block is automatically detected and the memory access is divided into two memory accesses. The corner bus interface section 57 also performs conflict prevention processing when an operand to be fetched and an operand to be stored overlap, and bypass processing from the store operand to the fetch operand. (Margins below) (5) [Pipeline processing J The microprocessor of the present invention exhibits high performance by pipeline processing of instructions. First, a pipeline processing method for a microprocessor according to the present invention will be described. (5,1) Pipeline Processing Mechanism The pipeline processing of the microprocessor of the present invention is schematically shown in FIG. An instruction fetch stage (IF stage) 31 for pre-fetching instructions, a decode stage (D stage) 32 for decoding instructions, an operand address calculation stage (A stage) 33 for calculating addresses of operands,
Micro l? ON access (especially referred to as R stage 36) and operand briefetch (especially called OF stage 37)
an operand fetch stage (F stage) 34 that performs instructions (referred to as
The five-stage configuration of No. 35 is the basis of pipeline processing. In addition to the E stage 35 having a store buffer, the execution of some of the high-performance instructions is pipelined, so that the effect of pipeline processing of five or more stages is actually exhibited. Each stage operates independently of the other stages, and in theory five stages operate completely independently. Each stage can perform one process in a minimum of l clocks. Therefore, ideally, pipeline processing progresses one after another every l clocks. Although the microprocessor of the present invention has instructions that cannot be processed in one basic pipeline process, such as memory-to-memory operations and memory indirect addressing, the microprocessor of the present invention has a pipeline that is as balanced as possible for these processes. It has been devised to allow line processing. For instructions with multiple memory operands, the instruction is decomposed into multiple pipeline processing units (step codes) at the decoding stage based on the number of memory operands, and pipeline processing is performed. The decomposition method is described in detail in Japanese Patent Application No. 61-236456. The information passed from the IF stage 31 to the D stage 32 is the instruction code itself. There are two pieces of information passed from the D stage 32 to the A stage: information In (referred to as D code value) regarding the operation specified by the instruction, and information In related to address calculation of the operand (referred to as A code 42). The information passed from the A stage 33 to the F stage is an R code 43 that includes the entry address of the microprogram routine and parameters to the microprogram, and an F code 43 that includes the operand address and access method instruction information.
There are two, code 44. The information passed from the F stage 34 to the E stage 35 is an E code 45 containing arithmetic control information and literals, and an S code 46 containing operands, operand addresses, etc. BIT detected at stage E stage 35 and above is
BIT processing is not started until the code reaches the E stage 35. Only the instructions being processed in the E stage 35 are instructions in the execution stage, and the instructions from the IF stage 31 to the F
The instructions processed up to stage 34 have not yet reached the execution stage. Therefore, when an EIT is detected at a stage other than the E stage 35, the fact that it has been detected is recorded in the step code and only transmitted to the next stage. (5, 2) ``Processing of Each Pipeline Stage'' The human output stage of each pipeline stage, Buko=1, is given a name as shown in FIG. 4 for convenience. Further, the step code performs processing related to an operation code, and may become an entry address of the micro ROM and a parameter for the E stage 35, or may become an operand for a microinstruction of the E stage 35. (5, 2, 1) r Instruction Fetch Stage The instruction fetch stage (IF stage) 31 fetches instructions from the instruction cache or memory system 13, inputs them into the instruction queue, and outputs the D stage 32-1 instruction code. Input to the instruction queue is performed in aligned 4-byte units. Fetching instructions from memory system 13 requires a minimum of two clocks per four aligned bytes. If the instruction cache is hit, the aligned 4
It can be fetched in l clocks per bit. The output unit of the instruction queue is variable approximately every 2 bytes, and a maximum of 6 bytes can be output during one clock. Immediately after the jump, it is also possible to bypass the instruction key 1- and directly transfer the 2 bytes of the instruction basic part to the instruction decoder. Controls registration and clearing of instructions in the instruction cache, management of prefetch destination instruction addresses, and control of instruction queues.
+B is also performed at the IF stage 31. (5, 2, 2) r instruction decode stage'' instruction decode stage (D stage) 32 is II + stage 31
Decodes the instruction code input from . Decoding is performed using the F1-rei decoder, NFH-decoder, and addressing mode 1' decoder of the instruction decoding section 52.
It is performed once per clock, and in one decoding process, θ ~ 6
A byte of instruction code is consumed (instruction code is not consumed in the output processing of the stem code including the return destination address of the return subroutine instruction, etc.), and in one decoding, it is sent to the A stage 33 as address durability information. A
, a control code of about 35 pints, which is the 1-code 42, and a maximum of 32 bits of address modification information, an intermediate decoding of the opcode, and a control code of about 50 bits, which is the resulting D code value, and literal information of 8 bits. Output. I] At the stage 32, the control j1 of the PC calculation unit 53 for each instruction is
, instruction code output processing from the instruction queue is also performed. <5.2.3) "r operand address calculation stage" operand address calculation stage (to stage) 3
The processing in step 3 is broadly divided into two parts. One is a process in which the second decoder of the instruction decoding unit 52 is used to decode the operation code at a later stage, and the other is a process in which the operand address calculation unit 54 calculates an operand address. The subsequent decoding process of the operation code uses the D code value manually, and performs write reservation of registers and memory, and output of the R code 43 including the entry address of the microprogram routine and parameters for the microprogram. Note that register and memory write reservations can be used to prevent incorrect addresses from being rewritten by instructions that precede them on the pipeline.
``This is to avoid performing a response calculation. The operand address calculation process takes the Δ code 42 as input, and according to this, the operand address value calculation unit 54 performs addition and memory indirect reference. The calculation is performed and the calculation result is output as the F code 44.At this time, a conflict check is performed when registers and memory are read in conjunction with address calculation.In other words, if the writing process of the preceding instruction to the register or memory has been completed. To avoid: If 1 conflict is specified, E stage 35
The preceding instruction is iHt! until the write process is completed. I am made to do so. (5, 2, 4) r Micro RO? +Access Stage" The processing at the operand fetch stage (F stage) 34 is also broadly divided into two. One is micro ROM
This is particularly called the R stage 36. The other is operand brief L Sochi processing, which is particularly referred to as OF stage 37. R stage 36 and Kano stage 37 do not necessarily operate at the same time, but depend on whether memory access rights can be acquired or not. , operate independently. The micro ROM access process, which is the process in the R stage 36, is performed on the R code 43 by performing the following [micro ROM access and micro This is instruction decoding processing. When processing for one 17 code 43 is decomposed into two or more microprogram steps, the micro ROM is used in the E stage 35, and the next R code 43 waits for micro ROM access. The micro ROM access to the R code 43 is performed at the time of execution of the last micro instruction in the previous E stage 35. In the microprocessor of the present invention, most of the basic instructions are executed by the microprogram step 21, so in reality, the microprocessor for the R code 43
? OM accesses are often performed one after another. (5, 2, 5) r Operand Fetch Stage The operand fetch stage (OF stage) 37 performs operand brifetch processing of the above two processes performed in the F stage 34. Presetting of operands is performed from the data cache or memory system 13. Operand briefetch takes F code 44 as input, and sends the fetched operand and its address to S:1J-F
Output as 46. Although one F code 44 may straddle a double word boundary, an operand fetch of 8 bytes or less is specified. The F code 44 also includes a designation as to whether or not to access the operand, and when the operand address itself and the immediate value calculated in the A stage 33 are transferred to the E stage 35, the operan 1 brief is not performed. , the contents of F code 44 are S code 46
will be transferred as If the operand to be read coincides with the operand to be written by the E stage 35, the operand briefetch is not performed from the data cache or memory and is bypassed. (5, 2, 6) r Execution Stage J The execution stage (E stage) 35 operates with the E code 45° S code 46 as input. This E stage 35 is a stage for executing instructions, and all processing performed in stages before the F stage 34 is preprocessing for processing in the E stage 35. A jump command is executed at E stage 35 or F! When IT processing is started, all processing from IF stage 31 to F stage 34 is invalidated. The E stage 35 is controlled by the microprogram and executes instructions by executing a series of microinstructions starting from the entry address of the microprogram routine indicated by the R code 45. The successive output of micro1iOrl and the execution of microinstructions are pipelined. Therefore, when a branch occurs in a microprogram, a blank space of 1 microstep occurs. Further, the E stage 35 can perform pipeline processing of operand store within 4 bytes and execution of the next microinstruction by using the store buffer in the data calculation unit 56. In the E stage 35, the write reservation for registers and memory made in the A stage 33 is canceled after the operand is written. Various interrupts are directly accepted by the E stage 35 at the timing of instruction breaks, and necessary processing is executed by the microprogram. Other various BIT processes are also executed by microprograms. (5, 3) r State control of each pipeline stage”
Each stage of the pipeline has an input launch and an output launch, and other stages basically operate independently. Each stage completes the previous processing, transfers the processing result from the output latch to the input lunch of the next stage, and receives all the human input signals necessary for the next processing at the input lunch of its own stage. Once all is completed, the next process begins. In other words, at each stage, all the human signals necessary for the next processing output from the previous stage are valid.
The current processing result is transferred to the input lunch of the subsequent stage, and when the output lunch is empty, the next processing is started. In other words, all input signals need to be available at the timing immediately before each stage starts its operation. If there are no human signals, the stage is in a waiting state (
input). When transferring from the output latch to the input latch of the next stage, the input lunch of the next stage must be empty, and even if the input latch of the next stage is not empty, the vibe line stage will wait. state (waiting for output), the necessary memory access rights cannot be obtained, or a wait state (standby state) is inserted in the memory access being processed.
If other pipeline conflicts occur, the processing of each stage itself will be delayed. (6) [Detailed circuit connection diagram of a data processing device using the microprocessor of the present invention] In Fig. 3, the microprocessor of the present invention is shown as υ]0,
1st FPU II, memory system 13. Clock generator single value interrupt system? 11 shows a connection relationship of a data processing device using a circuit 15. The first FPU II of the device of the present invention can accumulate and accept up to three coprocessor instructions, but MPt
Since llO has a PC queue of 4 entries, even if an exception occurs during execution of a coprocessor instruction, the PC value of that instruction is retained in the PCC 1021 and is destroyed by writing the PC value of the subsequent coprocessor instruction. It never happens. Also, the CPI old “00” of MPllo’s PSW104
1', the first FPU II has coprocessor number 0.
Assume that 01 is tilted. The system clock CLK is generated by the clock generator 14 and is passed through the IS line 70 to the MPIIIO, the first FPt 111. The data is input to the memory system 13. BATO:1 of signal vi171 is a signal indicating the type of bus cycle, CDEI of line 13 72 is a data output control signal to the first FPU II, which is a coprocessor, signal line 73
BSI, ASW, 051. R/en is another bus cycle control signal output by MPulO, C on signal line 74.
PSTO:2 is the control iT148 that transfers the internal state of the first FP old 1 to MPulo, CP of the signal line 75 [lCI is the bus cycle completion signal rB outputted by the first FPUII, and DCl of the signal line 76 is outputted by the memory system. This is the pass cycle complete 'M control signal. Further, the signal Ml is used as the data bus DO; 63, and the fi signal vA2 is used as the address bus AO: 31. Regarding interrupts, a signal line 79 for requesting an interrupt from the memory system 13 to the interrupt control circuit 15, and the first FPI 11
A signal line 80 that requests an interrupt to the interrupt control circuit 15 when an exception occurs in 1, and a signal that requests an interrupt to the liver υ10 as a result of those interrupt requests being sorted by the interrupt control circuit 15 *78 signal IRLO: 2 There is. (IO: 31 on δ line 3 is an instruction bus that transfers instruction codes from the memory system 13 to MPIIIQ. Each signal operates in clock synchronization with the system clock. Signal BATO on signal line 71: The meanings are as shown in the table in Figure 9. Each value "00", "01", 10", 11
″Address bus A 0 2 31 f 2 for each
+ and data bus DO: 63 (the contents of 11 are defined. For undefined parts, MPU10.11'
Pt1ll and memory system 13 ignore its contents. The meaning of the signal CPSTO:1 on the signal line 74 is as shown in the table of FIG. , the value "001" is the first FPIII
Indicates that data is being prepared for output. Value “OI
O” indicates that the command was accepted normally. The value “
Old 1° indicates that the first FPU II has completed preparations for data output. The value "io1" indicates that the first FPIII requests retransmission of the command. The value "110' indicates that an error occurred during command transfer. The value "I
II" indicates that the first FPII 11 is not connected. Values "000" and 0100" are undefined. The signal I RLO:2 on the signal line 80 requests the MPU10 to perform interrupt processing depending on its value. MPllo is I
It is determined whether to accept or mask the interrupt according to the value of the field in group ^S in RLO:2 and ll5W (104). (6,1) ``Memory Access Operation'' FIG. 6 is a timing chart of the memory access operation of the data processing apparatus whose configuration is shown in FIG. 3. Memory access is performed once every two clocks of clock BCLK for a sufficiently fast memory. In Figure 6, the first zero-wait data read cycle,
Next, a data write cycle with zero wait, then an instruction read cycle with one clock wait, and then a data write cycle with one clock wait are shown. In the diagram, CL and B
CLK is a system clock supplied via the signal line 70. RCLK is a bus clock with twice the cycle of CL,
Odd-numbered pulses and even-numbered pulses of C1 and K are determined. , CL, and the BCIJ of the present invention are synchronized at the time of system reset. In the data read cycle, the address is output as BATO:1-“00’, and the data bus DO:63111 is The value is fetched and the bus cycle ends. In the data write cycle, BATO:1 is set to ``OO'', and the address is first output, and then, after a delay of 1 clock, the data is output to the data bus DO:63 (11), and is output to Dsi and BCL.
I)(
When J (76) is asserted, the bus cycle ends. In the instruction read cycle, the address is output as BATO:1 = "01", and the instruction bus IO when C1l (76) is asserted at the fall of CL while S1 and BCL are at low level. :31 Loads the value of t31 and ends the bus cycle. As described above, in the processor mode, the microphone CI processor of the present invention activates a bus cycle synchronized with the clock CLK to perform input/output operations with the outside. (6, 2) r F P U access operation 1 FIG. 7 shows the MPII
This figure shows an example of a timing chart when a command is transferred from IO to the first FPIII. Command transfer is performed as a type of 9-cycle bus cycle. In Fig. 7, first the memory/FPU register (gate-F
R) 0-wait transfer cycle of command and operand for FPU instruction, then 0-wait data read cycle from memory, then FPLI register F
Between PII registers (PR-Fit) 1-wait transfer cycle of command l for FPυ instruction, then between MPU registers and FPU registers (GIN-Fil) Fl
The transfer cycle of command and operand and FPU instruction command value C value wait for U instruction is shown. In the transfer cycle of command and operand for FPU instruction between memory and FPU register, BATO: 1 = "
If a command is output from bit 16 to bit 31 of address bus A Q H31 (21) as 10', and CPDCI (75) is asserted at the falling edge of CL while DS# and BCLK,' are at low level. The bus U10 ends the bus cycle.The first FPU II receives commands from the address bus 2 and operands from the data bus DO:63 (11).
According to the value of (74), the state of the first FI"till is MP
tlIQ is notified. The command transfer cycle for the FPU instruction between the FPU register and the FPU register is the same as the command and operand transfer cycle for the FPU instruction between the memory and the FPtl register, except that there is no operand transfer. 1'1Fll between Ptl register and I'PII register
The transfer cycle of commands, operands, and PC values for the ll instruction is also similar to the transfer cycle of commands and operands for the Fl'tl register between the memory and Fl'tl registers. That is, the difference is that the operand is transferred only by the lower 4 bytes of data bus l. FIG. 8 is a timing chart when a command and operand for an FPU instruction are transferred between the FPU register and the memory in the data processing device whose configuration is shown in FIG. 3. In this case, first? 1st FP from 1llIIIO
The command is transferred to υ11, and then the 1st FPU II
from? Operands are transferred to IPIIIO and memory system 13. In the command transfer cycle, the address bus A O: 31 f3+ bit lO is set as BATO:1-“lO’.
A command is output from bit 31 to mouth S1 and BCL.
CPD at the falling edge of CLK while K is at low level.
When CI (75) is asserted, MPU10 ends the bus cycle. The first FPIII receives commands from the address bus 2. At this time, the first FPU
The state of II is notified to Ml'[IlO. In this example, the command is for an FPU instruction between FPU registers and memory, and the tppuii receives the command 7 in Tokyo, and CPSTO:2 (74) is "010", "001", "
O11'. gate! ) υ10 looks at the value of CPST (12) after transferring the command and asserts CPI El after reaching °O11'', and starts the operand transfer bus cycle one clock later. In this cycle, BATO: 1 -00'', the memory address at which the operand should be stored is output from the MPLllo to the address bus AO:31f21, and the data bus DO:
The operand is output from the first FPU II to 63 (11). The operand is taken in by both MPU10 and the memory system 13. The reason why MPIIIO takes in the operand is to rewrite the built-in data cache. The protocol and timing when .0 accesses the second Fl 1112 is that 11 Puio accesses the first Fl 1112.
This is basically the same as when accessing FPIII. The difference is that immediately after the memory cycle that transferred the command, BATO:1-“111 is sent to the coprocessor PC.
The only point is that there is a memory cycle that transfers the value from the liver ulO to the second PPυ12. (7) r:lBD Seno 4 “Instruction Processing Example” No. 36
38 are flowcharts illustrating an example of a processing procedure when the first FPU II executes the command 7. 1st FpHll cPID4i″001″? In these examples, C11 in l'5W104 of MllUlo
Since the ID value is also 001", the PC of the coprocessor instruction
(The command is not directly transferred to the first FP tll.) FIG. 36 is a flowchart of the processing procedure from when a coprocessor instruction, which is an FPU instruction between memory/FPI+registers, is fetched by MPIIIO until it is executed by the first FPU II. The figure is a flowchart of the processing procedure from when a coprocessor instruction, which is an FPU instruction between FPII registers and memory, is fetched at -PUIO until it is executed on the first FPUII. Figure 38 is an FPII instruction between memory and FPU registers. A coprocessor instruction is fetched in 5puio, executed in the first FPυ11, causes an exception, and is executed in the first FPυ1.
1 is interrupt system? 1 is a flowchart of a processing procedure when an interrupt is requested to MPIIIO through 1 circuit 15 and 1'1PI 110 performs exception handling. Exception handling is handled by an interrupt handler. In the microprocessor of the present invention, based on the instruction to read the PCID from the first FPU II and the PCID? IPII
There is a privileged instruction that reads the PC value of a coprocessor instruction from the corresponding entry in the PC queue 21 of IO. The interrupt processing handler uses these instructions to sequentially output the PCID and coprocessor. FIG. 39 is a flowchart 1 of the processing procedure from when a coprocessor instruction, which is an inter-register FPI instruction, is fetched at -PUIO until it is executed by the second FPU 12. 2nd FPu12 (7) CPIO is 010"?', and this is l'1Pul. CPID in PSW 104 of In the above-mentioned embodiment, the command transmission from MPU10 to Kobroset (J) and the operand transfer are performed in the same memory cycle, but it is not necessarily necessary to perform the same in one memory cycle. If the number of bits is larger than the number of bits of data bus l, operand transfer may be performed in multiple memory cycles.Furthermore, in the present invention, exceptions during execution of coprocessor instructions are handled by interrupts, and The instruction in the handler performs the operation of deleting the PC value of the coprocessor instruction stored in the entry of the PC queue 21 without reading it to the old O of h1. Notify the exception to MPU10 with a dedicated signal,
The MPU 10 reads the PCID and the contents of the entry in the PC queue 21 as a hardware operation,
The PC value of the coprocessor instruction that caused the exception may be placed on the stack as information to be passed to the exception handler. In this case, since the exception handler obtains the PC value of the coprocessor instruction that caused the exception from the stack, there is no need for the handler to read the Pc1 port or read the contents of the PC queue 21. [Effects of the Invention] As detailed above, the microprocessor of the present invention includes program counter value holding means (PC queue) for holding the pc value of a coprocessor instruction in preparation for the occurrence of an exception during execution of a coprocessor instruction. Therefore, when transferring a command corresponding to a coprocessor instruction, no memory cycle is required to transfer the pc value of the coprocessor instruction. Therefore, it is possible to instruct the coprocessor to operate in response to a coprocessor instruction in one memory cycle, and it becomes possible to obtain a high-performance data processing device. Also, program counter value holding means (1) C queue)
has multiple entries, and in order to concatenate the entry number with a command and transfer it to Kobro Seso'J, the PC of the program counter value holding device means corresponding to the coprocessor (keying multiple commands while distinguishing The entry number is 2 bits, which is a very small number of bits compared to the 32-bit PC value of the coprocessor instruction, and even if the command and entry number are concatenated, they can be transferred in one bus cycle. The entire data can be transferred via the 32-bit address bus 2. Therefore, it is possible to instruct the coprocessor to operate in response to a coprocessor instruction in one memory cycle, so the microprocessor of the present invention can be used to perform high-performance data processing. In addition, since it is determined whether or not to transfer the pc value of the coprocessor instruction to the coprocessor based on the value of the coprocessor identifier (CPIO), it is possible to connect multiple coprocessors. do,
Even when a plurality of coprocessors are operated in parallel while changing the coprocessor identifier, it is possible to hold the pc value of a coprocessor instruction for a specific coprocessor using one program counter value holding mechanism. Therefore, it is possible to configure a data processing device in which a plurality of coprocessors are connected without sacrificing the effect of the program counter value holding means.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a data processing device using the microprocessor of the invention, FIG. 2 is a block diagram showing an example of the configuration of the microprocessor of the invention, and FIG. FIG. 4 is a schematic diagram showing an overview of the pipeline processing of the microprocessor of the present invention. FIG. 5 is a block diagram showing the connection state of the processor and coprocessor. FIG. 6 is a timing chart of the microprocessor of the present invention during memory access; FIG. 7 is a timing chart of the microprocessor of the present invention, and a timing chart of JJ coprocessor access; FIG. 8 9 is a timing chart of a memory cycle when the microprocessor of the present invention executes an FPU instruction between FPU registers and memories. FIG. Figure 10 shows the value of the signal CPSTO:2 that conveys the internal state of the Cobb 11 setter to the microprocessor of the present invention and the meaning of θ. The figure is a schematic diagram showing how instructions are arranged on the memory of the microprocessor of the present invention. Figures 12 to 15 are schematic diagrams showing the format of instructions of the microprocessor of the present invention. 29
30 is a schematic diagram for explaining the instruction addressing mode of the microprocessor of the present invention; FIG. 30 is a schematic diagram, not showing the format of the command I transferred from the microprocessor of the present invention to the coprocessor; The figure is a schematic diagram showing the number of bits to be transferred when commands are transferred from the microprocessor of the present invention to the coprocessor via the address bus, and Figures 32 to 34 are commands transferred from the microprocessor of the present invention to the coprocessor. FIG. 35 is a schematic diagram showing the contents of the PSW of the microphone 1 coprocessor of the present invention, and FIGS. 36 to 39 are data processing devices using the microprocessor of the present invention. Flowchart 1 for executing various coprocessor instructions in 1. FIG. 40 is a block diagram showing the configuration of a data processing device using a conventional microprocessor and coprocessor. 2 is a timing chart when an MPU accesses a coprocessor in the data processing device using the conventional microprocessor shown in FIG. 10... Main processor (MPU) 11.12...
・Coprocessor (FPU) 2l-pc queue (11th PC) 22...2nd FPC52...Instruction decoding section 58...Address output circuit Note that the same reference numerals in each figure indicate the same or equivalent parts. .

Claims (8)

[Claims] (1) In a microprocessor that causes a coprocessor to perform a coprocessor operation, a decoding means that decodes a main processor instruction that is an instruction for itself and a coprocessor instruction that causes the coprocessor to perform a coprocessor operation; program counter value holding means for holding a program counter value; means for transferring a command corresponding to the coprocessor instruction to the coprocessor to execute a coprocessor operation according to the decoding result of the decoding means; A microprocessor comprising means for causing the program counter value holding means to hold the program counter value of the coprocessor instruction until a predetermined point in time during execution. (2) In a microprocessor that causes a coprocessor to perform a coprocessor operation, a decoding means that decodes a main processor instruction that is an instruction for itself and a coprocessor instruction that causes the coprocessor to perform a coprocessor operation; a first program counter value holding means for holding a program counter value of a processor instruction; a second program counter value holding means for holding a program counter value of a second coprocessor instruction; and according to the decoding result of the decoding means, Transferring to the coprocessor a command including a field in which operation specifiers corresponding to the first and second coprocessor instructions and identifiers for identifying the first and second program counter value holding means are concatenated. A microprocessor comprising: means for executing a coprocessor operation using a coprocessor. (3) In a microprocessor that causes first and second coprocessors to perform coprocessor operations, decoding that decodes a main processor instruction that is an instruction for itself and a coprocessor instruction that causes both coprocessors to perform coprocessor operations. means, a register for holding identification numbers of the first and second coprocessors, program counter value holding means for holding a program counter value of the coprocessor instruction, and according to the decoding result of the decoding means, the coprocessor instruction. means for transferring to the coprocessor a command including a field concatenated with an operation specifier corresponding to the first coprocessor and the identification number; and if the identification number indicates the first coprocessor, a program of the coprocessor instruction; means for causing the program counter value holding means to hold the counter value without transferring it to the first coprocessor; and when the identification number indicates the second coprocessor, the program counter of the coprocessor instruction; and means for transferring a value to the first coprocessor. (4) Claim (3) wherein the second coprocessor is plural.
). (5) In a data processing device comprising a coprocessor and a microprocessor that causes the coprocessor to perform a coprocessor operation, the microprocessor includes a main processor instruction that is an instruction for itself, and a main processor instruction that causes the coprocessor to perform a coprocessor operation. a decoding means for decoding a coprocessor instruction to be sent to the coprocessor, a program counter value holding means for holding a program counter value of the coprocessor instruction, and a command corresponding to the coprocessor instruction to the coprocessor according to the decoding result of the decoding means and means for causing the program counter value holding means to hold the program counter value of the coprocessor instruction until a predetermined point in time when the coprocessor executes the calculation. means for notifying the microprocessor from the coprocessor of the occurrence of an exception when an exception is detected as a result of an operation in the coprocessor; and reading a program counter value of the coprocessor instruction from the program counter value holding means. 1. A data processing device, comprising: means for executing exception handling. (6) In a data processing device comprising a coprocessor and a microprocessor that causes the coprocessor to perform a coprocessor operation, the microprocessor includes a main processor instruction that is an instruction for itself, and a main processor instruction that causes the coprocessor to perform a coprocessor operation. a first program counter value holding means for holding a program counter value of the first coprocessor instruction; and a second program counter value holding means for holding a program counter value of the second coprocessor instruction. and a field in which an operation specifier corresponding to the coprocessor instruction and an identifier for identifying the first and second program counter value holding means are concatenated according to the decoding result of the decoding means. A data processing device comprising: means for transferring a command including a command to the coprocessor to execute a coprocessor operation. (7) In a data processing device comprising first and second coprocessors and a microprocessor that causes the coprocessors to perform coprocessor operations, the microprocessor is configured to: a decoding means for decoding a coprocessor instruction that causes a processor to perform a coprocessor operation; a register for holding a coprocessor identification number; a program counter value holding means for holding a program counter value of the coprocessor instruction; and the decoding means. means for transmitting a command including a field in which an operation specifier corresponding to the coprocessor instruction and the coprocessor identification number are concatenated to the coprocessor according to a decoding result of the first coprocessor; means for holding the program counter value of the coprocessor instruction in the program counter value holding means without transferring it to the first coprocessor; and the identification number indicates the second coprocessor; and means for transferring a program counter value of the coprocessor instruction to the second coprocessor when the coprocessor instruction is executed. (8) Claim (7) wherein the second coprocessor is plural.
).