JPH02299313A - Automatic equalizer - Google Patents

Abstract

PURPOSE:To attain equalization with high accuracy with a simple circuit by quantizing n-value of an n-bit input signal to apply coarse equalization, using a discrimination feedback equalizer so as to equalize the residual difference with accuracy, and using the output for extracting the clock. CONSTITUTION:An A/D converter 1 samples an input signal to quantize the signal into n-bit. An absolute value takes the absolute value of the output of the converter 1 and an n-value quantization circuit 4 converts an output of the circuit 3 into n-value. The 1st shift register 5 stores the output of the circuit 4, a coding circuit 6 encodes the output of the converter 1 and the 2nd shift register 7 stores an output of the circuit 6. A coarse equalizing circuit 8 shifts a coefficient stored therein by a value stored in the shift register 5 and outputs the added or subtracted value according to the code stored in the register 7 and uses a difference with a training signal to revise the coefficient. A discrimination feedback equalizer 10 uses the output of a discriminator 9 to estimate the inter-code interference quantity and a clock extraction circuit 11 uses the output of the discriminator 9 to adjust the sampling phase of the converter 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic equalizer that adaptively performs waveform equalization in a metallic transmission line.

[Conventional technology]

In a metallic transmission system, when complex waveform distortion occurs due to the frequency characteristics of the transmission line and reflections from open-ended branch lines installed in the middle of the transmission line, there are systems that automatically correct this waveform distortion. It is a transformer. Figure 2 shows, for example, M
, Ishikawa et.

al,, “An adaptive 1ine eq
ualizer VLSI using digital
signal processing”, IE
EE J, 5oljd-5tata C1rcits
, Vol. 23 No. 3. pp830-835.
June.

This is an example of the configuration of an automatic equalizer using a digital filter shown in 1988. In the figure, (1) is an A/D converter that samples and quantizes the input signal, and (2) is an A/D converter that samples and quantizes the input signal. (9) is a determiner that performs binary determination of the amplitude level of the transmitted signal; (10) is an open-end branch; A decision feedback equalizer (11) that corrects waveform distortion due to reflection on the line adjusts the sampling phase of the A/[1 converter (1) using the output of the fT equalization circuit (2). This is a clock extraction circuit.

Next, the operation will be explained. The constant amplified input signal is sampled and quantized by an A/D converter (1). This A
The output signal xk of the /D converter (1) is sent to the 5-equalization circuit (2), where it is inner-producted with an appropriate coefficient C0,..., CN-□ among the several sets of coefficients stored therein. The calculation is performed and outputs yk. On the other hand, a decision feedback equalizer (10
) is the output ak of the determiner (9) and the coefficient set λ8. ....

An inner product operation is performed with λ4 and ik is output. and fT equalization circuit (2)
The difference 2 between the output yk of the output equalizer (lO) and the output Zk of the decision feedback type equalizer (lO): yk+zk is determined by the determiner (9) as a binary signal ak and output.

On the other hand, the coefficient λ1 of the decision feedback equalizer. ..., λuhaΔ〉
As O, λmu=λ1−Δsign(zl)ak−1, i=1.
2. -, M and stored in the decision feedback equalizer (10).

Finally, the clock extraction circuit (11) is a /7 equalization circuit (2
) is used as input to adjust the sampling phase of the A/D converter (1).

(Problem to be solved by the invention) Since the conventional automatic equalizer is configured as described above,
When a 5-equalization circuit is realized using a digital filter,
As is well known, digital filters require multipliers, which increases the circuit scale, and if the fT equalization circuit is removed, it takes a long time for the sampling phase and decision feedback equalizer to converge. There was a point.

This invention was made to solve the above-mentioned problems, and it completely eliminates the multiplier from the circuit and constructs an automatic equalizer that allows the sampling phase and the equalizer to converge quickly. The purpose is to

(Means for Solving the Problems) An automatic equalizer according to the present invention has a frequency of a transmission path -
In an automatic equalizer that corrects loss characteristics and provides flat frequency-loss characteristics, an A/D converter that quantizes an input signal and an absolute value circuit that takes the absolute value of the output of the A/[1 converter. , an n-value quantization circuit that converts the output of the absolute value circuit into an n-value, a first shift register that stores the output of the n-value quantization circuit, and a sign of the output of the A/D converter. a code circuit, a second shift register storing the output of the code circuit, and shifting a set of stored coefficient values by the value stored in the first shift register, and storing the set in the second shift register. A coarse equalization circuit adds the shifted components when the sign is positive, and subtracts the shifted components when the sign is negative and outputs the result. a decision feedback equalizer that estimates the amount of intersymbol interference shown and subtracts this estimated amount from the output of the coarse equalization circuit; and a code estimated by the decision feedback equalizer from the output of the coarse equalization circuit. The system is equipped with a determiner that performs a binary decision after removing the interfering amount, and a clock extraction circuit that uses the output of the determiner to adjust the sampling phase of the A/[1 converter. be.

[Effect]

The automatic equalizer in this invention first takes the absolute value and sign of n-bit data, converts the absolute value into n-value in an n-value quantization circuit, and then converts the stored coefficients into a coarse equalization circuit. After coarse equalization is performed by shifting n values and adding or subtracting them according to the sign, fine equalization is performed by a decision feedback equalizer.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to the figures (1
) is an A/D converter that samples the input signal amplified to a constant amplitude and quantizes it into n bits, (3) is an absolute value circuit that takes the absolute value of the output of the A/D converter (1), ( 4) is an n-value quantization circuit that converts the output of the absolute value circuit into n-values, (
5) is a first shift register that stores the output of the n-value quantization circuit; (6) is a code circuit that takes the sign of the output of the A/D converter (1); and (7) is the code circuit (6). A second shift register (8) that stores the output of the above shifts the stored coefficient by the value stored in the first shift register (5), and shifts the coefficient stored in the second shift register (7) by the value stored in the first shift register (5). (9) is a coarse equalization circuit that outputs the added or subtracted signal according to the sign and updates the coefficients using the difference from the training signal; (9) is a judger that performs binary judgment; (10)
is a decision feedback equalizer that estimates the amount of intersymbol interference using the output of the decider (9), and (11) is the A/D converter (1) that uses the output of the decider (9). This is a clock extraction circuit that adjusts the sampling phase of

Next, the operation of this embodiment will be explained based on the above configuration. A/
The absolute value 1xkl of the output Xk of the D converter (1) is taken by the absolute value circuit (3), and its sign sign (xk) is taken by the sign circuit (6). Absolute value circuit (
3) Output 1Xkl is 21≦1xkl< 2″+I □≦sk<
n is converted into Sk by the n-value quantization circuit (4) and
Stored in shift register (5). On the other hand, the code circuit (
The output sign(xk) of 6) is stored in the second shift register.

Now, the coarse equalization circuit (8) has coefficients Co,...+CN
-+ is stored, each coefficient G,, o≦l≦N−1
is shifted by -1, the value s stored in the first shift register (5).

Here, u, = C, ·2'', and when 0≦i≦N-1, this data is summed according to the sign Sign (Xk-+) stored in the second shift register (7), and yk During the training period, the difference between this signal 'Ik and the training signal d, ek=dh-yi+, is used to calculate the coefficient Co for Δ=2-' (1 is an integer).
, ... + CN-1 to C, = C, + Δek2 'sign (xb-t)
+ Coarse equalization circuit (8) updated by O≦i≦N-1
Store in.

Coefficients are not updated during data transmission.

On the other hand, with the output ak of the decider (9) as input, the decision feedback equalizer (lO) uses the stored coefficients λ1. ....

The amount of intersymbol interference is estimated and output for λ2. This output Z
The sum Zk of k and the output yk of the coarse equalization circuit (8) = zk+
'/h is input to the determiner (9), determined to be a binary signal ak, and output. During the training period, the coefficient λ1 of the decision feedback equalizer (lO). ..., λi is a positive number Δ, λmu=λ1−ΔSign(Zi+)am−1, i=l,
2. neo, M is updated and stored in the decision feedback equalizer (10) again. Coefficients are not updated during data transmission.

Finally, the output ak of the determiner (9) is determined by the clock extraction circuit (
1O) and adjusts the sampling phase of the A/D converter (1).

(Effects of the Invention) As described above, according to the present invention, an n-bit input signal is
After quantizing and coarsely equalizing the values, the residuals are precisely equalized by a decision feedback equalizer, and this output is used for clock extraction. Since all equalization is adaptive, the multiplier High-precision equalization, high-speed sampling phase, and convergence of a decision feedback equalizer can be obtained with a simple circuit without any noise.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an automatic equalizer according to an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of a conventional automatic equalizer. (1)...A/D converter, (2)...1 equalization circuit, (3)...absolute value circuit, (4)...n-value quantization circuit, (5)... First shift register, (6)... Code circuit, (7)... Second shift register, (8)... Coarse equalization circuit, (9)... Determiner, (10)...・Decision feedback equalizer, (11)...Clock extraction circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] An automatic equalizer that corrects the frequency-loss characteristic of a transmission path and provides a flat frequency-loss characteristic includes an A/D converter that quantizes an input signal and an absolute value of the output of the A/D converter. an n-value quantization circuit that converts the output of the absolute value circuit into an n-value, a first shift register that stores the output of the n-value quantization circuit, and the A/D converter. a code circuit that takes the sign of the output; a second shift register that stores the output of the code circuit; and a code circuit that shifts the set of stored coefficient values by the value stored in the first shift register; 2. A coarse equalization circuit that adds the shifted components when the sign stored in the shift register is positive, and subtracts and outputs the shifted components when the sign is negative, and the determined binary data. a decision feedback equalizer that estimates the amount of intersymbol interference indicated by the transmission path as an input and subtracts this estimated amount from the output of the coarse equalization circuit; and the decision feedback equalizer that uses the output of the coarse equalization circuit. a determiner that performs a binary determination on the estimated intersymbol interference amount removed; and a clock extraction circuit that adjusts the sampling phase of the A/D converter using the output of the determiner. An automatic equalizer characterized by: