JPH02298879A - Flaw inspecting apparatus - Google Patents

Abstract

PURPOSE:To accurately detect a flaw, in such a case that non-flaw signal levels of a definite length or less is intermittently generated between flaw signal levels in a flaw inspecting apparatus of a reproduction signal, by interpolating said non-flaw signal levels as a series of flaw signals. CONSTITUTION:A flaw detecting part 102 detects the abnormal part of a reproduction signal to output a flaw judging signal which is, in turn, inputted to the inverter 104 and shift register 105 constituting a flaw judging signal interpolating part 3. The clock of the shift register 105 is supplied from a clock generating circuit 106 and each of the register outputs of the shift register 105 is inputted to a multi-input AND gate 107. The output of the gate 107 and that of the final stage of the register 105 control an RSFF 108. In this constitution, when the length between non-flaw signal levels appearing between flaw signal levels is within the number of the stages of the register 105, the output of the RSFF 108 is held to a high level state showing a flaw. That is, the output of the RSFF 108 is outputted to a terminal 109 as an interpolated flaw judging signal.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a defect inspection device for information recording media, etc.

[Prior Art] When manufacturing magnetic or optical information recording media,
Defects occur on the media due to scratches, dirt, non-uniformity of the media, etc. The presence of such defects on the medium causes errors in the data when information is reproduced from the medium. Such errors may be tolerated to some extent in the case of analog signals, but in the case of digital information, even a single error may not be tolerated. Alternatively, if the information reproducing apparatus is equipped with a device for detecting and correcting errors using an error correction code, errors that do not exceed the correction capability may be tolerated. In any case, when manufacturing information recording media, it is necessary to maintain the number of errors, maximum length, etc. below standards, and therefore defect inspection is essential.

In particular, since defects occur frequently in optical information recording media, it has been important to inspect and manage them. Relatively large dirt or scratches on the media can cause burst errors of up to several dozen bytes. A reproducing device for an optical information recording medium is usually equipped with an error correction device, and is capable of correcting errors of up to a fixed 7XI bytes, for example, up to 80 bytes per sector. However, 3. The occurrence of a long burst error may exceed this correction range, which is the most worrying point in defect inspection. In other words, defect inspection requires accurate measurement of the length of defects and their frequency of occurrence.

[Problems to be Solved by the Invention] However, the conventional defect inspection apparatus has a problem in that the measured defect length and occurrence frequency are different from the actual state of defects on the medium. This problem will be explained using FIG. 2. Assume that a defect 201 exists on a recording track 202. A reproduced signal 203 is obtained by reproducing the recording track using a reproducing means. Here, nothing is recorded on the recording track. When the reproducing means passes over the defect, an abnormal portion 204 appears in the reproduced signal 203. In order to detect this abnormal part, the judgment voltage level is 20.
5 is provided, and a method is adopted in which when a voltage lower than the determination voltage level occurs in the reproduced signal, this is detected as an abnormal part. The type of waveform that appears in the abnormal area depends on the type of defect,
Since it depends on the shape and cannot be predicted, abnormal part 2
04, there is a location 206 where a voltage exceeding the determination voltage level is generated. Therefore, a defect signal level 208 and a non-defect signal level 209 appear alternately in the defect determination signal 207. For the purpose of defect detection, the defect signal level should be output continuously during the abnormal portion, but this is not actually the case.

[Means for Solving the Problems] The defect inspection device of the present invention includes a reproducing unit that reproduces a reproduced signal from an inspection object, a defect signal level that detects an abnormality in the reproduced signal and indicates the presence of a defect, and a defect signal level that indicates the presence of a defect. A defect detection unit outputs a defect determination signal consisting of a binary signal level of a defect-free signal level shown in FIG. If the finite time at which the defect-free signal level was output is within a predetermined judgment time, the defect-free signal level is corrected to the defect signal level and output before and after the defect-free signal level. The present invention is characterized by comprising a defect determination signal interpolation section that interpolates the defect signal level determined by the defect signal level to a continuous defect signal level.

[Example] Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the defect inspection apparatus of the present invention.

The information recording medium is reproduced by the reproduction section 101 and outputs a reproduction signal as shown in FIG. 2 203. The reproduced signal is input to a defect detection section, which detects an abnormal part of the reproduced signal and outputs a defect determination signal.

When the reproduction signal is reproduced from a state in which nothing is recorded on the medium, as shown at 203, a defect determination signal can be obtained by using a voltage comparator. Further, when reproducing a certain pattern after writing it on a medium, the reproduced pattern and the original pattern may be compared and if there is a difference between the two, a defect signal level may be output. In any case, a defect determination signal is output from the defect detection section 102 and input to the defect determination signal interpolation section. The defect determination signal first passes through an inverter and its logic is inverted. Subsequently, the signal is input to the shift register 105.

The embodiment shown in FIG. 1 uses an 8-bit shift register. A signal output from the clock generation circuit 106 is used as a clock for the shift register. In other words, the defect determination signal is sampled by this clock. The output of each register of the shift register is input to a multi-input AND gate 107. The output of the multi-input AND gate is RS together with the output of the final stage Q8 of the shift register.
The configuration is such that the flip-flop 108 is controlled.

The operation of the defect determination signal interpolation section 103 will be explained using the timing chart of FIG. 301 is shift register 1
05 is a clock (CLK) input to the defect determination signal interpolation section 302, a defect determination signal (ERR) is input to the defect determination signal interpolation section;
03 is the SET input (SE
T), 304 is the RESET input (RESET) of the flip-flop 108, 305 is the flip-flop 10
8 represents the timing of each signal of Q output (Q). When the defect determination signal continues to have a non-defective signal level (here, low), a high level continues to be input to the shift register 105. At that time, since the outputs of each register of the shift register are all high, the output of the multi-input AND gate 107 is low. In this state, SET is high, RESET
Since is low, low is output to Q. This indicates that the defect determination signal after interpolation is at the non-defect signal level.

Here, it is assumed that an abnormal portion occurs in the reproduced signal and a defect determination signal as shown in 302 is output.

Three intermittent defect signal levels are output, but as mentioned above, this is not due to three defects but one continuous defect. 302
Since the signal whose logic is inverted by the inverter 104 is input to the shift register, the outputs of each stage of the shift register transition from a high state to a state in which some (or all) of the outputs are low. Therefore, if the net length of the defect is Lθ, the defect signal level must be input to 8+
When the 7 clock is idle, the output of the multi-input AND gate goes high. 305 indicates this. Furthermore, the output QGI of the final stage of the shift register becomes low for the first time after the 8th clock, that is, after the elapse of 7 clocks after the beginning of the defective signal level is input. At that moment, RS flip-flop 108 is set and its output goes high. Counting from that point, the time when the RS flip-flop 108 is reset and returns to low is (Le+7)
7=After the time corresponding to Le clocks has elapsed. That is, the output Q of RS flip-flop 108 goes high during Lti clocks, as shown at 306. Although signal 306 has a delay corresponding to the number of stages of the shift register, it can be used as an interpolated defect determination signal.

When the defect determination signal is input to the defect determination signal interpolation section through the above operation, the defect determination signal with the defect signal level interpolated appears at the output terminal 109.

In this embodiment, the interpolation operation is performed when the non-defective signal level that appears between the defective signal levels that appear before and after is within seven clocks. Interpolation is not performed when a non-defective signal level continues for 8 or more clocks between two defective signal levels. This reference value is determined by the number of stages of the shift register 105 and the number of inputs of the multi-input AND gate. Longer interpolation becomes possible by increasing the number of stages of the eight-stage shift register used here and inputting the output of each stage to a multi-input AND gate having inputs for the number of stages. The number of stages can be selected according to the defect inspection method and purpose.

Accurate measurement is possible by using the defect determination signal after interpolation. FIG. 4 shows an embodiment in which a defect counting section 401 is provided following the defect determination signal interpolation section to measure the length distribution of defects. This defect counting section counts the defect signal level of the input defect determination signal, and can measure the number of defect occurrences for each defect length, the total number of defect occurrences, and the total number of defect occurrence bits. When the defect 201 shown in FIG. 2 is measured, the defect determination signal 207 is interpolated by the defect determination signal interpolation unit 103 and becomes the interpolated defect determination signal 210. 210
is input to the defect counting unit, the defect counting unit recognizes that L@ bit or length defects have occurred once, and adds 1 to the number of Lo bit length defects and adds 1 to the total number of defects.
, the total number of defective bits is plus L. On the other hand, in a conventional defect inspection apparatus without a defect determination signal interpolation section, the defect determination signal 207 is directly input to the defect counting section. In that case, the defect counting unit recognizes that defects with a length of L+, L2, and L3 bits have occurred once each, and
The number of defect occurrences for the l, L2, and L3 pit lengths is each plus 11, the total number of defect occurrences is plus 3, and the total number of defect occurrence bits is plus (LI+L2+L3). The measurement results of the latter conventional defect inspection apparatus do not represent the actual state of defects on the medium. The occurrence of defects with long lengths of t and s bits is overlooked, and short defects with lengths of L1, L2, and L3 bits occur instead. As mentioned earlier, it is a long burst error that causes a defect on an information recording medium to become uncorrectable and makes it impossible to read information, so overlooking this is a serious defect for defect inspection equipment. I can say that.

The result of the defect inspection apparatus of the present invention that assumes that a long defect of 1 Li bit has occurred once is correct.

[Effects of the Invention] As explained above, according to the present invention, a defect determination signal interpolation unit is provided to interpolate intermittent occurrence of non-defective signal levels of a certain length or less between defective signal levels. By doing so, it is possible to perform a defect inspection that well represents the reality of defects on the medium, and in particular, it is possible to obtain accurate results in detecting long defects that are a problem for information recording media. Note that the circuit configuration of the defect determination signal interpolation unit 103 shown in FIG. 1 is an example, and other circuits can be used.

The main focus of this patent is to emphasize the importance of interpolation and that a defect inspection device should be equipped with interpolation means.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of a defect inspection apparatus of the present invention. FIG. 2 is a schematic diagram showing the relationship among defect 1, a reproduced signal, a defect determination signal, and a defect determination signal after interpolation. FIG. 3 is a timing chart showing the operation of the defect determination signal interpolation section used in the defect inspection apparatus of the present invention. FIG. 4 is a block diagram of the defect inspection apparatus of the present invention including a defect counting section. Applicant: Seiko Epson Co., Ltd. Representative Patent Attorney Kizobe Suzuki and 1 other person Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Scope of Claims] A reproducing unit that reproduces a reproduced signal from an inspection object, a defect signal level that detects an abnormality in the reproduced signal and indicates the presence of a defect;
a defect detection unit that outputs a defect determination signal consisting of a binary signal level of a defect-free signal level indicating that no defect exists; following the defect determination signal outputting the defect signal level, the defect-free signal level is maintained for a limited period of time; If the defect-free signal level is output again after the defect-free signal level is output, and the finite time when the defect-free signal level is output is within a predetermined judgment time, the defect-free signal level is corrected to the defect signal level and the defect-free signal level is output again. A defect inspection device comprising: a defect determination signal interpolation unit that interpolates the defect signal level outputted before and after the defect signal level to a continuous defect signal level.