JPH02295259A - Phase demodulator - Google Patents

Abstract

PURPOSE:To prevent a communication device from entering a different alarm generation state in the same fault mode by adding a function which stops the output of a demodulated data signal or clock by a carrier synchronism alarm. CONSTITUTION:A clock enable part 10 is added. The clock enable part 10 stops the clock which is outputted by a VCO 8 from being sent out by the carrier synchronism alarm, so when modulated wave input is ceased, the carrier synchronism alarm is generated to stop the clock input. Consequently, no clock is inputted to a received signal processing part which is connected as a trailing stage, so an input pulse break alarm is generated without fail. Further, the same effect is obtained by providing an output data enable part instead of the clock enable part 10. Consequently, such trouble that alarms generated when the input of the phase demodulator is ceased are in individually different combinations is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase demodulator used for demodulating PSK modulated waves. [Prior Art] A block diagram of an example of a conventional phase demodulator is shown in FIG.

The input modulated wave is outputted by the phase detector 1 from the VCO 5 (
The output is synchronously detected with the reference carrier signal) and the output is sent to the wave section 2.
After removing harmonics and unnecessary wave components, the signal is input to the determining section 3. Here, the input signal is the output of vcos (
clock), ゛0゛′. "゜1'゜" is determined and output as data. On the other hand, the output of the ?toba section 2 is simultaneously transmitted to the control section 4 (carrier regeneration control circuit based on Costas type phase comparison) and the control section 9 (clock regeneration control circuit). circuit).

The control section 4 controls the VCO 5 according to its output, and outputs a reference carrier signal synchronized with the carrier component of the input modulated wave. A search oscillator 6 consisting of a low-frequency oscillator is connected to the VCO 5, but the output of this search oscillator 6 is compressed by the loop gain of the Costas Lube, and when the loop is closed, it affects the oscillation frequency of the VCO 5. not give. However, when the Costas loop is no longer closed, such as when the modulated wave input disappears, the VCO 5 is controlled by the output of the search oscillator 6, and its oscillation frequency is successively changed. When the above state occurs, the alarm detection section 7 outputs a carrier synchronization alarm by utilizing the fact that the output component of the search oscillator 6 is no longer compressed by the loop and is generated at the input terminal.

On the other hand, the output of the waveform unit 2 inputted to the control unit 9 is subjected to full-wave rectification, and then compared in phase with the output of vcos (for clock oscillation), and the error signal is outputted as the output of the control unit 9.
A clock synchronized with the clock component of the modulated wave input to the OS and input to the phase detection section 1 is reproduced. VC○8
The output is input to the determination section 3 and the control section 9, and is also output to the next stage as a clock.

[Problem to be solved by the invention]

Since the conventional phase demodulator described above uses a double-balanced mixer in its phase detection section 1, when there is no input modulated wave, its output is near the center of the amplitude of the eye pattern.

The situation is shown in FIG. 3(b) as an input waveform of the determination unit 3. Note that FIG. 3(,a) shows the input waveform (eye pattern) of the determination section 3 when the phase detection section 1 has an input modulated wave.

Here, since the ideal threshold value of the judgment unit 3 is also at the center of the amplitude of the eye pattern, the threshold value of the judgment unit 3 should be adjusted to around this point, but many phase demodulators have been manufactured. In this case, the threshold value will vary around the center of the amplitude of the eye pattern. As a result, when the threshold value is set low or high, the output of the determination unit 3 when there is no manually modulated wave in the phase detection unit 1 is “1゛′ or ゛′” 0”, but those set almost to the center are
Due to the influence of noise, '゛1゜゜, "0'" will be repeated irregularly. However, the output of this type of phase demodulator is usually delivered in the form of an NRZ waveform, so the output will be "" It is fixed at 1゜゛ or "0", and "1''. If 0° is repeated irregularly, it will cause the input pulse disconnection alarm detection circuit in the received signal processing unit (not shown) connected to the next stage to malfunction, and when viewed as a communication device, the phase demodulator A problem arises in that the combinations of alarms that are generated when the input is turned off are individually different.

[Means to solve the problem]

The phase demodulator of the present invention demodulates the input signal using a reference carrier signal regenerated by a phase-locked loop synchronized with the carrier component of the input signal, and outputs a demodulated data signal and a clock of the demodulated data signal. In,
a first means for detecting out-of-synchronization of the phase-locked loop; and a second means for stopping output of at least one of the demodulated data signal or the clock under the control of a detection signal of the first means. I'm here.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment is constructed by adding a clock enable section 10 to the conventional example shown in FIG. The clock enable unit 10 stops outputting the clock output from the vcos to the outside in response to the general transmission synchronization alarm output by the alarm detection unit 7.

As a result, when the modulated wave input disappears, a carrier synchronization alarm is generated and the clock output is stopped. Therefore, the received signal processing section (not shown) connected to the next stage of this embodiment loses the input clock, so an input pulse cutoff alarm is sure to occur. Furthermore, the same effect can be obtained by providing an output data enable section that stops the data output of the determining section 3 from being outputted to the outside in response to a carrier synchronization alarm, instead of providing the clock enable section 10.

〔Effect of the invention〕

As explained above, the present invention adds a function to stop the output of the demodulated data signal or clock in response to a carrier synchronization alarm, so that the communication device can have different alarm occurrence conditions in the same failure mode. It has the effect of preventing

Moreover, since this additional function can be constructed with a simple gate circuit, it can be realized with almost no change in price.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an example of a conventional phase demodulator, and FIGS. 3(a) and (b).
) are diagrams showing input waveforms of the determination unit 3 in FIGS. 1 and 2. DESCRIPTION OF SYMBOLS 1... Phase detection part, 2... Wave wave part, 3... Judgment part, 4... Control part, 5...■C○, 6... Search oscillator, 7... Alarm Detection unit, 8...VCO,
9... Control section, 10... Clock enable section.

Claims (1)

[Claims] In a phase demodulator that demodulates the input signal using a reference carrier signal reproduced by a phase-locked loop synchronized with a carrier component of the input signal and outputs a demodulated data signal and a clock of the demodulated data signal, the phase-locked loop is synchronized. A phase shifter characterized in that it includes a first means for detecting deviation, and a second means for stopping output of at least one of the demodulated data signal or the clock under the control of the detection signal of the first means. Demodulator.