JPH02294031A - Formation of trench - Google Patents
Formation of trenchInfo
- Publication number
- JPH02294031A JPH02294031A JP11427689A JP11427689A JPH02294031A JP H02294031 A JPH02294031 A JP H02294031A JP 11427689 A JP11427689 A JP 11427689A JP 11427689 A JP11427689 A JP 11427689A JP H02294031 A JPH02294031 A JP H02294031A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- etching
- upper edge
- insulating film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title claims description 5
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims 2
- 239000007789 gas Substances 0.000 claims 1
- 239000012495 reaction gas Substances 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 4
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、半導体記憶装置のトレンヂキャバシタ用のト
レンチ形成方法に関し、特に、半導体ダイナミックラン
ダムアクセスメモリのトレンチキャパシタ用のトレンチ
形成方法に関するものである.
(従来の技術)
近年、半導体記憶装置は、高密度化が進み、特に,ダイ
ナミックランダムアクセスメモリ(以下DRAMと称す
)の高集積化,高密度化は目覚ましいものがある.この
ようなDRAMの発展は,そのチップサイズの半分以上
の面積を占めるメモリセルの高密度形成技術の発展に負
う所が大きい.高密度化の,ための技術のひとつに、ト
レンチキャパシタ構造があげられる.
従来のDRAMに用いられるトレンチキャパシタの形成
方法について,第2図により説明する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming a trench for a trench capacitor in a semiconductor memory device, and particularly to a method for forming a trench for a trench capacitor in a semiconductor dynamic random access memory. It is. (Prior Art) In recent years, the density of semiconductor memory devices has been increasing, and in particular, the density and integration of dynamic random access memories (hereinafter referred to as DRAMs) have been remarkable. The development of DRAM is largely due to the development of high-density formation technology for memory cells, which occupy more than half of the chip size. One of the technologies for increasing density is the trench capacitor structure. A method of forming a trench capacitor used in a conventional DRAM will be explained with reference to FIG.
第2図(a)ないし(C)は、従来のトレンチキャパシ
タの形成工程を示す要部拡大断面図である。第2図(a
)において,まず、シリコン基板1の表面にマスクとな
る酸化III2を形成した後、エッチングによりトレン
チ3を形成する.
次にマスクとなった酸化膜2を除去した後、トレンチ3
上部のエッジを丸めるために、加熱炉に入れ偽製酸化処
理を行うと、第2図(b)に示すように、全面に酸化膜
4が形成される。FIGS. 2(a) to 2(C) are enlarged cross-sectional views of essential parts showing the process of forming a conventional trench capacitor. Figure 2 (a
), first, a III oxide 2 serving as a mask is formed on the surface of a silicon substrate 1, and then a trench 3 is formed by etching. Next, after removing the oxide film 2 that served as a mask, the trench 3
In order to round off the upper edge, when it is placed in a heating furnace and subjected to fake oxidation treatment, an oxide film 4 is formed over the entire surface as shown in FIG. 2(b).
次に、上記の酸化膜4を除去した後に、トレンチ3の内
壁面およびこれに沿う縁表面に絶縁膜5およびT字状の
電極6を形成すると、第2図(c)に示すトレンチキャ
パシタが得られる(トレンチキャパシタの信頼性向上,
Se++iconductor World,198
7. 8 篠崎,渡辺).
(発明が解決しようとする問題点)
しかしながら、上記の形成方法では、偽製酸化処理によ
って形成されるトレンチ3上部のエッジの丸みは,小さ
いため、エッジの電界集中によって絶縁膜5の耐圧性が
劣るという問題があった。Next, after removing the oxide film 4, an insulating film 5 and a T-shaped electrode 6 are formed on the inner wall surface of the trench 3 and the edge surface along the inner wall surface of the trench 3, and the trench capacitor shown in FIG. 2(c) is formed. (Improved reliability of trench capacitors,
Se++iconductor World, 198
7. 8 Shinozaki, Watanabe). (Problem to be Solved by the Invention) However, in the above formation method, the roundness of the upper edge of the trench 3 formed by the fake oxidation treatment is small, so the voltage resistance of the insulating film 5 is reduced due to electric field concentration at the edge. The problem was that it was inferior.
本発明は,上記の問題を解決するもので,優れた耐圧性
を有するトレンチキャパシタが得られるトレンチ形成方
法を提供するものである。The present invention solves the above-mentioned problems and provides a method for forming a trench that allows a trench capacitor with excellent voltage resistance to be obtained.
(課題を解決するための手段)
上記の課題を解決するため、本発明はシリコン基板をエ
ッチングする際に、等方性エッチングと、異方性エッチ
ングを行うものである。(Means for Solving the Problems) In order to solve the above problems, the present invention performs isotropic etching and anisotropic etching when etching a silicon substrate.
(作 用)
上記の横成により、等方性エッチングの工程でトレンチ
上部のエッジが大きく面取りされるため、電界の集中を
緩和し絶縁膜の耐圧性を大幅に向上する。(Function) Due to the above-mentioned horizontal formation, the upper edge of the trench is largely chamfered in the isotropic etching process, which alleviates the concentration of electric field and greatly improves the voltage resistance of the insulating film.
(実施例) 本発明の一実施例を第1図により説明する。(Example) An embodiment of the present invention will be explained with reference to FIG.
第1図(a)ないし(c)は,本発明によるトレンチキ
ャパシタ形成の工程順を示す要部拡大断面図である。FIGS. 1(a) to 1(c) are enlarged cross-sectional views of essential parts showing the order of steps for forming a trench capacitor according to the present invention.
第1図(a)において,まず、シリコン基板1の表面に
マスクとなる酸化膜2を形成した後、リアクティブイオ
ンエッチング(以下、RIEと称す)を用い, 300
W, 70mTorr, S F./ CCIl.=1
30/10 3CCHの条件で等方性エッチングを施し
た後、続いて、真空度を15mTorrに下げて異方性
エッチングを行うと、上部のエッジに角面取りが施され
たトレンチ3が形成される。In FIG. 1(a), first, an oxide film 2 serving as a mask is formed on the surface of a silicon substrate 1, and then reactive ion etching (hereinafter referred to as RIE) is used to perform etching at 300 nm.
W, 70mTorr, SF. /CCIl. =1
After isotropic etching is performed under the conditions of 30/10 3CCH, the vacuum level is lowered to 15 mTorr and anisotropic etching is performed to form a trench 3 with a chamfered upper edge. .
次に,上記のマスクとなった酸化膜2を除去した後,ト
レンチ3の内壁面およびこれに沿った縁表面に絶縁膜5
と電極6を形成する。Next, after removing the oxide film 2 that served as the mask, an insulating film 5 is formed on the inner wall surface of the trench 3 and the edge surface along this.
and form the electrode 6.
以上のように本実施例によれば,トレンチ3上部のエッ
ジに形成された角面取りの角は鈍角となるため、電界の
集中が緩和され、従って、絶縁膜の耐圧性が大幅に向上
する.
なお、本実施例では、従来用いられた偽装酸化処理を省
略したが、絶縁膜5の形成前に偽製酸化処理を行なえば
,さらに,安定した高耐圧性のキャパシタが得られる.
また、トレンチキャパシタだけでなくトレンチゲートに
も応用できることは言うまでもない。As described above, according to this embodiment, the chamfered corners formed at the upper edges of the trenches 3 have obtuse angles, which alleviates the concentration of the electric field, and therefore greatly improves the voltage resistance of the insulating film. In this embodiment, the conventionally used fake oxidation process is omitted, but if the fake oxidation process is performed before forming the insulating film 5, a capacitor with a more stable high voltage resistance can be obtained.
Furthermore, it goes without saying that the present invention can be applied not only to trench capacitors but also to trench gates.
(発明の効果)
以上説明したように本発明によれば、トレンチの上部エ
ッジに、大きな角面取りが形成されるので絶縁膜の耐圧
性を大幅に向上することができる。(Effects of the Invention) As described above, according to the present invention, a large corner chamfer is formed on the upper edge of the trench, so that the voltage resistance of the insulating film can be greatly improved.
第1図(a)ないし(C)は本発明のトレンチキャパシ
タの形成工程順を示す要部拡大断面図、第2図(a)な
いし(C)は従来例のトレンチキャパシタの形成工程順
を示す要部拡大断面図である。
1 ・・・シリコン基板、 2,4 ・・・酸化膜,3
・・・ トレンチ, 5 ・・・絶縁膜、 6 ・・
・電極。
特許出願人 松下電子工業株式会社
第
図
第
図FIGS. 1(a) to (C) are enlarged cross-sectional views of essential parts showing the order of forming steps for a trench capacitor of the present invention, and FIGS. 2(a) to (C) show steps for forming a conventional trench capacitor. FIG. 3 is an enlarged cross-sectional view of main parts. 1... Silicon substrate, 2, 4... Oxide film, 3
... trench, 5 ... insulating film, 6 ...
·electrode. Patent applicant Matsushita Electronics Co., Ltd.
Claims (3)
成するエッチングによるトレンチ形成方法において、等
方性エッチングおよび異方性エッチングで形成すること
を特徴とするトレンチ形成方法。(1) A method for forming a trench by etching for forming a trench capacitor or the like on the surface of a silicon substrate, which method is characterized in that the trench is formed by isotropic etching and anisotropic etching.
わせたことを特徴とする請求項(1)に記載のトレンチ
形成方法。(2) The trench forming method according to claim (1), characterized in that wet etching and dry etching are combined.
スの種類、ガス流量の条件のうち、いずれかの条件が異
なった2つ以上を組み合わせて用いたことを特徴とする
請求項(1)に記載のトレンチ形成方法。(3) Claim (1) characterized in that two or more of the conditions for dry etching, such as applied power, pressure, type of reaction gas, and gas flow rate, are used in combination. Trench formation method described.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11427689A JPH02294031A (en) | 1989-05-09 | 1989-05-09 | Formation of trench |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11427689A JPH02294031A (en) | 1989-05-09 | 1989-05-09 | Formation of trench |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02294031A true JPH02294031A (en) | 1990-12-05 |
Family
ID=14633776
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11427689A Pending JPH02294031A (en) | 1989-05-09 | 1989-05-09 | Formation of trench |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02294031A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5741738A (en) * | 1994-12-02 | 1998-04-21 | International Business Machines Corporation | Method of making corner protected shallow trench field effect transistor |
JP2007013085A (en) * | 2005-06-30 | 2007-01-18 | Hynix Semiconductor Inc | Method for manufacturing semiconductor device |
JP2017117963A (en) * | 2015-12-24 | 2017-06-29 | トヨタ自動車株式会社 | Semiconductor device manufacturing method |
-
1989
- 1989-05-09 JP JP11427689A patent/JPH02294031A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5741738A (en) * | 1994-12-02 | 1998-04-21 | International Business Machines Corporation | Method of making corner protected shallow trench field effect transistor |
JP2007013085A (en) * | 2005-06-30 | 2007-01-18 | Hynix Semiconductor Inc | Method for manufacturing semiconductor device |
JP2017117963A (en) * | 2015-12-24 | 2017-06-29 | トヨタ自動車株式会社 | Semiconductor device manufacturing method |
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