JPH0229357A - Interface for printer - Google Patents

Abstract

PURPOSE:To enable image data to be transferred at extremely high speed through only hardware and not through software by providing a parallel I/O IC and a buffer RAM for storing printing data with an address counter and a switching circuit for switching between a strobe signal and a busy signal, in a parallel interface. CONSTITUTION:When a received instruction is an instruction for printing image data, a CPU 5 sets a switching circuit 2 through an I/O 6. When switching is finished, a busy signal is canceled, and a host computer starts transferring data. A strobe signal from the host computer increments an address counter 7, and causes the data to be written into a buffer RAM 8. When an output from the counter 7 becomes equal to a predetermined value, a detecting circuit 9 sets the switching circuit 2. The data from the buffer RAM 8 is transferred to a head data-transferring circuit 11 by high-speed DMA transfer, through changing over a switch 10 and in synchronism with a clock signal from the circuit 11. Thus, a data bus 4 for the CPU 5 is not occupied exclusively, so that the CPU can continue a required processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to increasing the speed of an interface circuit for an image printer capable of expressing gradations.

[Summary of the invention]

In a parallel interface such as Centronics, the CPU switches the interface signal to the data receiving circuit using hardware in response to a command to transfer image data, and after receiving data for a specific number of pixels using the address counter, normal software and CPU This allows the command to return to the receiving state. In this way, image data can be received at high speed.

[Conventional technology]

Centronics is the most common printer interface, and most computers have this parallel interface, and printers also use the bidirectional GPIB interface used in measuring instruments. However, a 12 dot/l111 image printer, which requires 1 byte of data for 1 dot, requires 40 megabytes of data to be transferred to an A3.1 screen.

[Problem to be solved by the invention]

However, with interfaces such as Centronics and CPNB, the CPU receives the received data according to software instructions, and determines whether it is data or instructions to control the printer (
If it is data, it is stored in memory. Therefore, it depends on the speed of the CPU, which is much slower than the hardware. FIG. 2 shows the timing when the CPU of the printer receives data by software, and an interrupt (P) is generated in the CPU by data and a stroke signal from the host computer side, and processing is performed. Furthermore, the printer also controls the head and motor, and for this purpose, timer interrupts (H) and (M> are generated and processed. During these processes, the CPU communicates with the host computer. During this time, the host computer cannot send data. Due to the waiting time and CPU processing time, data transfer is slow, and each dot has 1 pixel + 1 byte. There is a problem that it takes a lot of time to send data.Furthermore, when printing while receiving data, there is a problem that the data transfer cannot keep up with the printing operation, resulting in intermittent printing operation and uneven feeding. Ta.

[Means to solve the problem]

A parallel interface with a parallel I/O IC and a buffer RAM that stores print data. Equipped with an address counter that outputs addresses to the buffers R and A M of ``, and a switching circuit that switches between strobe signals and busy signals.When the host computer is outputting control commands, the control commands are input commands to the CPU.

When the CPU receives a command to print an image, the CPU activates the switching circuit. After receiving a specific number of image data, the switching circuit automatically resets and enters a state for inputting commands to the CPU. While the switching circuit is in operation, pixel data is read only by hardware using the host computer's strobe signal as a clock.

[Effect]

In this way, the pixel data transfer speed can be up to 50 Mbytes/sec, which is the operating speed of logic ICs such as TTL.[Embodiment] FIG. 1 is a block diagram showing the principle of the present invention.

A host computer signal inputted from the switching circuit 2 through the connector 1 of the Centronics interface is inputted to the CPU 5 via the parallel I/O IC 3 and the data bus 4 in the control command receiving state. When the received command is to print image data, the CPU 5 outputs l/O6.
The switching circuit 2 is set via. The switching circuit 2 connects the state of the switch to the lower side opposite to that shown. During this switching, a busy signal is output to the host computer.

When the switching is completed, the busy state is canceled and the host computer starts data transfer. The strobe signal from the host computer causes the ANDRES counter 7 to count up while writing the data input from the connector 1 into the buffer RAM 8.

When the output of the address cardant, that is, the number of data written to the buffer RAM, becomes equal to a predetermined specific value, for example, the number of data for one line, the detection circuit 9 detects 1. Reset switching circuit 2. Then switching circuit 2
The switch returns to the state shown in the figure, but until it returns, it outputs a busy signal to the host computer to suspend the transmission of data, etc. Data transfer from the buffer RAM 8 is performed by switching the switch /O in the opposite direction to that shown in the figure, and performing high-speed DMA transfer to the memory of the head data transfer circuit 11 in synchronization with the clock of the head data transfer circuit.

Since this transfer does not monopolize the data bus 4 of the CPU 5, the CP tJ can continue necessary processing even during the transfer. still,
The head data transfer circuit 11 creates serial data according to the number of gradations according to the data in the internal memory, transfers it to the thermal head, and prints it.

FIG. 3 shows how data is transferred from the connector 1 to the buffer RAM 8 while the switching circuit 2 is in operation. This figure shows how data can be transferred at high speed, unlike the software-based data transfer shown in FIG. Here, data can be transferred at an operating frequency of 50 megabytes/second using TTL, etc., while the host computer uses high-speed C
Even when using a PU, when transmitting using software, it takes several megabytes and 7 seconds, so even if the busy signal is fixed in the canceled state, data can be transferred reliably.

By connecting the address and data of the buffer RAM 8 to the address and data bus of the CPU via a 3-state buffer, data can be directly written to and read from the buffer RAM 8 from the CPU 5. Such cases are also included in the present invention. In addition, the data input/output section of the buffer RAM 8 includes a connector 1 and a head data transfer circuit 1.
A bus switching means such as a 3-state buffer is built in for each bus, and bus switching is performed in accordance with the read/write control of the buffer RAM 8.

〔Effect of the invention〕

According to the present invention, the following effects are achieved.

0 When transferring image data, the bar/
Data can be transferred at ultra-high speed using only software.

■A printer that prints while transferring data eliminates instantaneous printing stops that occur during printing due to insufficient data transfer, and eliminates image quality deterioration such as uneven feeding.

01975 Time can be made faster.

■Centronics is included with most computers,
When the present invention is applied to Centronics, it becomes extremely versatile and can be used regardless of the model of the host computer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a timing diagram when the CPU of the printer is receiving data by software, and FIG. 3 is a timing diagram of data transfer according to the present invention. It is. Connector switching circuit Parallel I/O IC Data bus CPU Address counter buffer RAM Detection circuit Switch head Data transfer circuit Applicant: Seiko Electronics Industries, Ltd.

Claims (1)

[Claims] In an image printer that receives and prints gradation data pixel by pixel from a host computer via an interface that handles parallel data, a central processing unit (hereinafter referred to as CPU) and a parallel I/O that can be accessed from the CPU are used. an IC, a buffer RAM for storing print data, a signal for inputting a data read request of the interface (hereinafter referred to as a strobe signal), a switching means for switching the flow of a signal for outputting a busy state on the printer side, and the strobe. It includes an address counter that counts signals and a detection circuit that detects a specific value of the address counter, the switching means is controlled by the CPU and the detection circuit, and the parallel data of the interface is connected to the parallel I/O. A printer interface characterized in that an IC and the buffer RAM are connected directly or via a circuit such as a buffer.