JPH02292684A - Picture recognizing system - Google Patents

Abstract

PURPOSE:To realize the processing of various kinds of feature quantities, and to improve a recognition rate by providing the neural layer of layer construction to meet the degree of abstractness of extracted data obtained from a picture processing part, and recognizing a picture according to the extracted data. CONSTITUTION:The picture inputted from an input part 200 is inputted to the picture processing part 300, and the processing part 300 processes the inputted picture, and extracts a number of groups, a number of holes, an Eulerian number, and texture feature quantity, and sends them to a recognizing part 100. The recognizing part 100 is constituted of a neural network to recognize a graphic according to the extracted data, and is provided with a data group 10 and the neural layers 20, 90. The data of low order among the extracted data is inputted to the neurons 21 to 23 of the layer 20, and besides, the data of high order is inputted to the neurons 91 to 93 of the layer 90, and they are processed. Thus, because the recognizing part 100 is of the layer construction to meet the degree of abstractness of the data and of data input configuration, various kinds of the feature quantities can be processed, and the recognition rate can be improved.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an image recognition system.

[Conventional technology]

Conventionally, as a method for recognizing image information, for simple symbol recognition, the position and size of black and white areas within a predetermined size area are calculated after preprocessing such as expansion, contraction, and thinning of the figure. There was a method of coding mutual relationships and comparing them with registered data. Regarding character recognition, there is a method of extracting features such as coordinate angle distribution, final point list, and reflected line segments, and comparing these features with the features of registered data.

[Problem to be solved by the invention]

In the former method, it is difficult to recognize complex figures, characters, etc. because the types of input data are enormous. In addition, in the latter case, it is necessary to predetermine the allowable amount for matching between character features and registered data features, which requires statistical processing of a huge amount of sampling data, and It is difficult to recognize handwritten characters. Moreover, in general, handwritten characters have a wide variety of characteristics, and the characteristics of the same character vary greatly among individuals.

The present invention was devised to solve these conventional problems, and an object of the present invention is to provide an image recognition system that is capable of processing a variety of special MLs and that can increase the recognition rate.

[Means to solve the problem]

The image recognition system according to the present invention includes an input unit that inputs an image, an image processing unit that processes the manually generated image and extracts features, and a threshold value and the sum of input data multiplied by a predetermined weight. Neurons are provided in parallel that output data according to the comparison results of It is equipped with a recognition section that performs image recognition, and performs the main recognition processing using a so-called neural network.

[Effect]

Extracted data indicating the characteristics of the input image obtained by the image processing section is input to neurons of the neural layer of the recognition section, thereby performing image recognition. That is, since image recognition is performed by processing image feature data using a neural network, the image recognition rate is increased by the learning function and associative function of this neural network.

〔Example〕

The present invention will be explained below based on illustrated embodiments.

In FIG. 1, the image recognition system includes an image input section 200, an image processing section 300, and a recognition section 100, which are interconnected through a system bus B.
Connected to CPtJ500. The image input unit 200 includes an input device such as an image scanner and an I/O.
/O includes data compression means, memory for data retention, etc. as appropriate. The image processing unit 300 includes a processing unit 310 that performs feature extraction and a frame memory 330 that holds images.
If desired, an image input section 340 is provided inside. As will be described in detail later, the recognition unit 100 performs image recognition based on the extracted data obtained by the image processing unit 300, and a neural layer consisting of multiple neurons is constructed, and the output data of this neural layer is It is equipped with a memory for storing.

FIG. 2 shows a processing section 3lO in the image processing section 300. The processing section 310 transfers data selectively fetched from the frame memory 330 via the multiplexer 311 to the neighboring processing section 312 via the local bus LB. ing. The neighborhood processing unit 312 holds data in units of predetermined neighborhood areas (for example, 3×3), and inputs these data in parallel to the calculation unit 320. The calculation section 320 has a numerical calculation section 321 and a state calculation section 325, and the output of the neighborhood processing section 312 is manually input to the numerical calculation section 321. The numerical calculation unit 321 is formed by sequentially connecting a multiplication unit 322, a selector 323, and an integration unit 324, and performs differentiation and other operator processing and inter-image calculations in the numerical calculation unit 321. In numerical calculations, for example, the density of each pixel is multiplied by a multiplier and then integrated numerically, but based on the inventor's knowledge that the same pixel is never multiplied by a multiplier with a different absolute value, A multiplication section 322 is arranged at the front stage. As a result, the number of kernels in the multiplication section can be set to a minimum value equal to the number of simultaneously processed pixels, and the number of gates in the selector 323 and integration section 324 at the subsequent stage is also reduced accordingly. Therefore, the numerical calculation section 321 can have maximum functionality with a small circuit, and the processing speed can be increased.

The data in the numerical calculation section 321 is led to the state calculation section 325, and the state calculation section 325 performs the following judgment or calculation on pixels within a predetermined neighborhood area.

i) Whether or not the center pixel is the pixel to be processed.

ii) Whether there is a pixel with a density different from that of the central pixel in the 8 neighborhood.

iii) Whether each pixel in the 8 neighborhoods is the same as the central pixel.

iv) Each number of TFDEs for Euler number calculation.

■) Degree of match with a predetermined pattern.

vi) Others.

In this way, by performing state calculations in parallel with numerical calculations and in separate circuits, it is possible to improve the efficiency and speed of each activation. Further, the output of the state calculation unit 325 is itself a valid feature quantity, or is valid data for extracting a feature quantity.

The output of the state calculation unit 325 is input to the conversion unit 313, and feature quantities are further determined by processing such as feature extraction, integration, and comparison.

The converter 313 is constructed by connecting a light arithmetic unit such as a full adder to a branch of the output of a high speed memory such as a static RAM, and feeding back the output of this light arithmetic unit to the data input of the high speed memory.

With such a configuration, it is possible to repeatedly perform the same operation on the same data, and to perform complex operations such as data integration and data successive approximation at high speed in a small-scale circuit.

The outputs of the calculation section 320 and the conversion section 313 are returned to one of the frame memories 330 via the local bus LB on the output side.

The local bus LB on the output side further includes a sequential processing unit 31.
4 is connected, and sequential processing such as labeling and thinning is performed in this sequential processing section. The sequential processing unit 314 includes a line memory, a latch, and a logic unit, and performs sequential processing while referring to the post-processing density of the rask immediately before the pixel to be processed.

Such a processing section can obtain extremely diverse feature amounts at high speed, and can supply valuable feature amounts to the recognition section 100. Note that if a dual port memory is employed as the frame memory 330, data can be read and written at extremely high speed.

Next, the configuration of the recognition unit 100 will be explained based on FIG. 3.

The recognition unit 100 processes data input via the system bus B or from an input system directly connected to the recognition unit 100, that is, the image processing unit 300, and stores the processing results in the data memory 110 as final output data. Output.

A neural network is constructed in the recognition unit 100. To briefly explain neural networks here, a neural network consists of neurons shown in Figure 4 arranged in parallel as shown in Figure 5 in a layered manner, and connected to neurons in other layers or the same layer. It is constructed as follows. Neurons l are interconnected to exchange data, and final output data is obtained from the neurons in the final layer. In data processing in neuron l, data DI. , DIE, Dll, ... DI. are respectively multiplied by weights W,, W2, W3, . . . W, and the sum total thereof is compared with the threshold value θ.

Various methods are possible for this comparison, but for example, when this sum is greater than or equal to the threshold θ, the output data DO is “1”.
and when this sum is smaller than the threshold value θ, the output data DO is set to be “0”. That is, oo=r((Σ(W1×old five)−θ} (1), where f is a normalization function.

The recognition unit 100 has an output data generation unit 120 that performs an association function in a neural network, and the output data generation unit 120 calculates a linear threshold function (ΣW, A.-θ) for each neuron. . Each part of the output data generation section 120 is controlled by the CPU 500.

W. A. The multiplication is executed in the multiplication circuit 121 in the output data generation section 120. W. A. The calculation results of ΣW, A. calculations are performed. The integration circuit 122 has a flip-flop 105 connected to the addition circuit 104 in a feedback manner, and after temporarily holding the addition result in the flip-flop 105, it connects the next input of W, A, and the held addition result. Integration is performed by adding. ΣW,A. The calculation result is input to the threshold processing unit 123, and the calculation of (ΣWiA, -θ) is performed. Furthermore, in the threshold processing unit 123, (ΣW
．． A, one θ) processing such as normalizing the calculation result,
Use as output data. The calculation result of (ΣW.A.-θ) is input to the data memory 110 via the buffer 106.

Since weight data and input or output data are input in parallel to the multiplication circuit 121, it has two input lines, and the buffer 106 is connected to one of the input lines. Used as a bidirectional input/output line. The buffer 106 becomes high impedance when data is transferred from the data memory 110 to the multiplication circuit 121.

Regarding the data of each neural layer, the O-order input data and the weight of the neural layer are input for the first layer, and the primary output data and the weight of the second neural layer are input for the second layer. That is, the output of the nth neural layer (nth output data) becomes the human power of the (n+1)th neural layer. In the data memory IO, weight data is stored in a synapse weight area 111, and input/output data is stored in an input/output data area 112. Further, the threshold value of each neuron to be set in the threshold value processing unit 123 is set in the data memory 110 or the system memory 1.
01, and is transferred to the threshold processing unit 123 before starting calculation for each neuron.

Although the processing content actually executed by a neural network is extremely complex, the first embodiment of the neural network of the present invention will be described on the assumption that extremely simple logical operations will be executed, and the first embodiment of the neural network of the present invention will be described. Explain the basic philosophy of 1.

Figure 6 (a), (b), and (c) are the results of learning, A. (
B+C) This shows the neural network that led to the execution of the logical operation in (2). Figures 6(a) and (b) show comparative examples, and Figure 6(a) and (b) show comparative examples.
C) shows a first embodiment of the neural network.

In FIG. 6(a), the first stage neural layer 2o is provided with neurons 21 to 2, the number of all combinations of the three data A, B, and C in the data group 0, 23=8 neurons 21 to 2.
In the neural layer 3o of the first stage, there is one neuron 3 that calculates the OR (logical sum) of the outputs of the first stage neurons 21 to 2.
1 shows a configuration in which 1 is provided. In the figure, neuron 2
The numbers such as rooOJ attached above I~28 are data A.
, B, C, and these neurons output " when this bit pattern is input.
1" is output. In this neural network, the number of neurons is 9 and the number of synapses is 32, the efficiency of neurons and synapses is extremely low, the required memory capacity is large, and the processing time is also large.

Figure 6(b) expands equation (2) as follows, and A-B
+ A-C (3)
This is an example in which calculations are simplified, and the first neural layer 20 includes neurons 21 for processing the calculations of A-B.
, A-C. The second stage neural layer 30 includes neurons 2l,
It has a neuron 31 that calculates the OR of the outputs of 22.

In the neuron 21, weights W. -W3 is, for example, W1=1, W2=1, W3=
It is set to 0, and outputs "1" when AW, +BW2 +cw, ≧2 (4). Therefore, in this case, the threshold θ=2
It is said that Similarly, in neuron 22, Wa =1
- Ws = O, W6 = 1, θ = 2. On the other hand, in the neuron 31, W,=1, W8=1, and θ=1.

In the neural network of FIG. 6(b), the number of neurons is 3 and the number of synapses is 8, and when compared with the neural network of FIG. 6(a), the neuron efficiency and synaptic efficiency are significantly improved. However, as described below, according to the present invention, these efficiencies are further improved.

FIG. 6(C) shows the first neural network of the present invention.
This shows an example, and this configuration includes a first-stage neural layer 20 and a second-stage neural layer 30. Only data B and C are input to the first-stage neural layer 20, and the second-stage neural layer 30 receives only data B and C. is data A
is input directly. The initial neural layer 20 includes (
One neuron 21 is provided to perform the calculation of B+C), and the second stage/neural layer 30 has a
One neuron 3l is provided for performing the calculation of B+C). For example, the neuron 2I has a weight W1=1, W
g=1, θ=1, BW, +CW2≧1
When (5), an output "l" is output. On the other hand, the neuron 31 has, for example, W3=1, W4=1, θ=
2 and the output of neuron 2l is Yl, then
Y I W 3+ A W < ≧2 (
6), the output rl is output. In this example, the number of neurons is 2 and the number of synapses is 4.
Neuron efficiency and synaptic efficiency are significantly improved compared to the comparative example b).

Here, the first basic idea of the present invention will be explained.

Paying attention to equation (2) again, data B and C are connected by one operator r+(OR)J, and data A is connected by the operator ``×(AND)J'' for the operation result. Therefore, originally, data B, C and data A should not be evaluated in the same dimension, but if you dare to evaluate them in the same dimension, the efficiency will be reduced as shown in the comparative example in Figure 6 (a) and (b). resulting in a decrease in

Here, it is assumed that the processing content of the neuron is only the evaluation of the following equation (7).

ΣW,A. −θ (7) (However,
Wi: weight, Ai: input, θ: threshold) Then, it is assumed that the degree of abstraction can be defined for each data, and this degree of abstraction is called "degree."

This order is defined as the order of output data increasing by one order with respect to input data in one neuron.

Further, it is defined that data connected by one operator have the same degree.

According to this definition, in the case of equation (2), data B,
C is of the same order, and data A is one order higher than that. Here, if rQJ is given as the order of data B and C, the order of data A is "1".

Considering the relationship between the order of this data and the hierarchy of neural layers, in Fig. 6(c), neural layer 2
Only the Oth-order data is manually input to the neural layer 30, and only the first-order data is input to the neural layer 30. Therefore, it is clear that the neural layers 20 and 30 can be associated with the order of input data, and hereinafter the same order as the human data will be defined for the neural layers as well.

Then, by classifying the data group to be input into the neural network according to its order, and inputting the data of each order to the neural layer of the corresponding order, neuron efficiency and synaptic efficiency are optimized.

Furthermore, as explained in relation to FIGS. 6(a) and (b), it is also possible to process high-order data by reducing it to a lower order, and in this case, neuron efficiency and synaptic efficiency decrease. . Therefore, the degree of each data should be based on the highest possible degree of that data.

Note that one data may be used for multiple orders, such as (A0B)/B, and in this case, 1
One piece of data may be input to multiple neural layers.

As an example to more clearly explain the degree of abstraction, which is the original meaning of the degree, FIGS. 7(a) to (C) show neural networks for determining the end points of a figure.

There are various ways to consider the end points of a figure, but here,
In the 3×3 convolution (Figure 7(a)),
When any of the patterns shown in Fig. 7(b) (i) to (viii') occurs, the central pixel (Fig. 7(a)
It is assumed that pixel E) is an end point. This end point is judged as an "end point" when any one of the pixels A-D, F to ■ other than the center pixel has a figure density (for example, "1"), and the center pixel E has a figure density; ``There is no end point'' when .

A neural network for this determination is configured, for example, as shown in FIG. 7(C), and this figure shows a second embodiment of the neural network. This neural network has a first stage neural layer 20 having eight neurons 21 to 28 and a second stage neural layer 30 having one neuron 31, and has pixels A-D, F.
-1 data is input to the first stage neural layer 20, and data of pixel E is input to the second stage neural layer 30.

The neurons 21 to 28 of the first stage neural layer respectively determine that only 8, only B, only C, etc. are figure pixels "1", and the neuron 31 of the second stage neural layer 30 determines that each of the neurons 21 to 28 Either “IJ
is output, and when E is the figure pixel "1", the output is "
1" is output.

Here, if each pixel data A-D, F-1 is considered as O-order data, the output of the neuron 31 becomes secondary data. Therefore, when the data of each pixel and various feature quantities are input data, it can be seen that if the data of each pixel is considered as zero-order data, the end point data can be handled as secondary data. The image processing unit 300 outputs the number of groups, large numbers, Euler numbers, texture characteristics f'll. Various data such as ffi are output, but the order of these data should be taken into account and directly input to the optimal neural layer.

FIG. 8(a) shows a third embodiment of the neural network, and in this embodiment, the neural network:
It has a data group 10 and neural layers 20 and 90,
Layer 90 is an output layer that outputs output data to the outside.

The data group lO is the first group of data l1, l2, l
3... and the second group of data l4, 15, l6.
Consists of... That is, the data of the data group 10 is classified into two types, a first group and a second group, according to their order.

The neural layer 20 includes neurons 21, 22, 23,
..., and the output layer 90 has neurons 91, 9
It has 2,93... Each neuron of neural layer 20 is connected to each neuron of output layer 90. The first group of data l1, 12, l3... is input to each 221ron of the neural layer 20,
The second group of data l4, 15, 16, . . . is input to each neuron of the output layer 90, respectively.

Each neuron of the neural layer 20 is configured, for example, as described above (
1) As shown in Figure 2, the total sum of each manually inputted data multiplied by a weight is compared with a threshold value, and output data ``1'' or ``0'' is output depending on the comparison result. Each neuron in the output layer 90 has the same information as each neuron in the neural layer 20 and the second group of data 14, 15,
Find the sum of 16... multiplied by their respective weights,
Depending on the comparison result between this sum and the threshold value, data of "l" or "0" is outputted similarly to the neurons of the neural layer 20.

The first group of data 1l, 12, 13, etc. are zero-order data indicating whether the pixel is "l" (for example, black) or "0" (for example, white), and the second group of data 14,
15, 16, . . . are high-order data indicating characteristics of pixels.

Thus, in the third embodiment, the first group of data, ie, low-order data, is input to the neurons of the neural layer 20, and the second group of data, ie, high-order data, is input to the neurons of the output layer 90. .

Therefore, the neurons in the neural layer 20 perform lower-order processing, for example, processing on the data of the pixel itself, and the neurons in the output layer 90 perform higher-order processing, such as processing on various properties of pixels, etc. .

In this way, in the third embodiment, high-order data is input directly to the output layer 90 and not to the neural layer 20, so the number of synapses, that is, the number of connections between input elements and neurons or between neurons is reduced. However, the number of neurons also decreases. As the number of synapses decreases, the number of operations required for neurons decreases, so
The calculation speed increases and the number of weight data decreases, so
The memory capacity is also small. Furthermore, when the number of neurons is reduced, the number of threshold values is also reduced, which reduces the memory capacity, reduces the number of calculations, and increases the calculation speed. According to this embodiment, high-speed arithmetic processing is possible with a small memory capacity, and a highly efficient neural network can be obtained with a simple circuit.

FIG. 8(b) shows a fourth embodiment of the neural network, which consists of three groups of input data 1
0, neural layers 20, 30 and output layer 9
has 0.

The input data group 10 includes first group data 11 and 12.
, l3... and the second group of data 14, 15, 1
6... and the third group's De Ichiba 17, l8, 19.
...and is provided. That is, unlike the third embodiment, the input data group is classified into three types. The first neural layer 20 has neurons 2, 22, 23, etc., and the second neural layer 30 has neurons 31,
32, 33... The output layer 90 has neurons 91, 92, 93, . . . . Each neuron of the first neural layer 20 is connected to each neuron of the second neural layer 30, and each neuron of the second neural layer 30 is connected to each neuron of the output layer 90, respectively.

The first group of data 11, 12, 13... are sent to each neuron of the first neural layer 20, and the second group of data l4, l5, l6... is sent to each neuron of the second neural layer 30. Third group data 17
, 18, 19, . . . are connected to each neuron of the output layer 90, respectively.

Each neuron is similar to the third embodiment, for example, the above (1
), output data "1" or "O" is output according to each input data. The first group of data 11, 12, 13... are zero-order data, the second group of data 14, 15, l6... are l-order data, the third group of data 17, l8, engineering 9... is secondary data. That is, high-order data is input to the second neural layer 30, and even higher-order data is input to the output layer 90.

In this fourth embodiment, as in the third embodiment, the number of synapses and neurons also decrease. Therefore, the same effects as in the third embodiment can be obtained.

Figures 9(a) and (b) show the fifth part of the neural network.
Examples are shown together with comparative examples, and this example shows a case where input data is processed according to the logical operation (AeB) 6B (([D). Here, e indicates "exclusive OR". , and A, B, C, and D are digital values of "IJ" or "0", and the result of this logic calculation is also "1".
'' or r■, will be explained as being output as a digital value.

FIG. 9(a) shows a comparative example, and this device has an input data group 10 for passing input data, first and second neural layers 20, 30, and an output layer 90. The input data group IO consists of input data A, B, C, and D. The first neural layer 20 has four neurons 2L22, 23, 24, and the second neural layer 30 has four neurons 3l, 32, 33, 34. Each data A-D is input to each neuron of the first neural layer 20, and each neuron of the first neural layer 20 is connected to each neuron of the second neural layer 30, respectively. On the other hand, the output layer 90 has one neuron 9l, and each neuron of the second neural layer 20 is connected to this neuron 9l.

In the first neural layer 20, each neuron 2
l has a weight and a threshold by which each human data is multiplied, and according to (1) 2 above, when the sum of the products of each input data and the weight is greater than or equal to the threshold, output data "l" is output, and this sum When is smaller than the threshold θ, output data “0” is output.

Similarly, neurons 22, 23, and 24 also output "1" or rQ, depending on each input data. Similarly, in the second neural layer 30, each neuron outputs "1" or "0" depending on the input data.

Similarly, the neurons 91 of the output layer 90 output data of "1" or "0" according to the output data from the neurons of the second neural layer 30.

Now, the logical operation (AeB) 69 (CeD) (7) The operation result is when data A and B do not match and C and D match, and when A and B match and C and D do not match. , becomes "1". In other cases, it is "0". Therefore, in FIG. 9(a), each neuron is configured as follows.

In the first neural layer 20, neurons 21
, 22, 23, and 24 are respectively "01 XXJ, rlOx" when A, B, C, and D are represented by 4-bit patterns.
x", rxx0 1J, rXX10", outputs "1", otherwise outputs "OJ".Here, "xX
j means to ignore the data. On the other hand, the second
In the neural layer 30 of , the neurons 31 are
Only the neurons 21 of the first neural layer 20 are "
1”, outputs rlJ, otherwise outputs rQJ
Output. Further, the neuron 32 outputs "1" when only the neuron 22 of the first neural layer 20 outputs "1", and outputs "0" at other times. Similarly, the neurons 33 are connected to the first neural layer 2
0 outputs "1" when only the neuron 23 outputs "1", and the neuron 34 outputs "1" when only the neuron 24 of the first neural layer 20 outputs "1".
" is output. On the other hand, neurons 91 of the output layer 90
outputs "1" when at least one neuron of the second neural layer 30 outputs "l".

Therefore, if the input data of A, B, C, D is a bit pattern of roooIJ, the first neural layer 2
0, only the neuron 23 outputs "1", and the other neurons 21, 22, and 24 output "0". As a result, the neuron 33 in the second neural layer 30 outputs "1", and the neuron 91 in the output layer 90 outputs "1". Similarly, A and B
,C,D,r0010'',rolooJ,rl000
”, r1110J, rllolJ, “1011”, ro
In the case of 111J, one of the neurons in the second neural layer 30 outputs "1", and the neuron 91 of the output layer 90 outputs "1".

FIG. 9(b) shows a fifth embodiment of the present invention, and this device has a human data group 10, first, second and third neural layers 20, 30, 40 and an output layer 90. The input data group 10 includes input data A. ．． Consists of B, C, and D. The first neural layer 20 has four neurons 2122, 23, 24, the second neural layer 30
has two neurons 3, 32, the third neural layer 40 has two neurons 4L42, and the output layer 90 has one neuron 91. Data A to D of the human data group are input to each neuron of the first neural layer 20, and each neuron of the first neural layer 20 is connected to each neuron of the second neural layer 30, respectively. second neural layer 30
Each neuron of the third neural layer 40 is connected to each neuron of the third neural layer 40 , and each neuron of the third neural layer 40 is connected to a neuron of the output layer 90 .

Each neuron in each neural layer 20, 30, 40 and output layer 90 outputs "1" or "0" depending on input data, as in the case of FIG. 9(a).

In the first neural layer 20, neurons 21
, 22, 23, 24 are A. ．． When B, C, and D are expressed as 4-bit patterns, they are respectively "0IXXJ, N
"1" when "Oxx", rxxoIJ, rXX10"
", otherwise outputs [OJ. on the other hand,
In the second neural layer 30, neurons 31
outputs "1" when the neuron 21 or 22 of the first neural layer 20 outputs "1", and outputs "0" otherwise. Further, the neuron 32 is the same as the neuron 23 or 24 of the first neural layer 20.
When outputting ``1'', output ``1'', otherwise output ``0''
Output. In the third neural layer 40, the neuron 41 outputs r1 when only the neuron 32 of the second neural layer 30 outputs "I", and otherwise outputs "0". Further, the neuron 42 is
Only the neurons 31 of the second neural layer 30 are "
1”, outputs r1, otherwise “O”
Output. On the other hand, the neuron 91 of the output layer 90 outputs "1" when at least one neuron of the third neural layer 40 outputs "l".

? Therefore, if the input data of ASB, C, and D has a bit pattern of roOG1, the first neural layer 2
0, only the neuron 23 outputs rl, and the other neurons 2l, 22, and 24 output r■,. As a result, only the neuron 32 in the second neural layer 30 outputs "I J", and the neuron 42 in the third neural layer 40 outputs "1". Therefore, the neuron 91 of the output layer 90 outputs rlJ. Similarly, A, B, C, D are r0
010”, rQloOJ, “1000”, r1110J
, r1101,, rlo11r, “0111,”
In the second neural layer 30, one of the neurons outputs "1", which causes one of the neurons in the third neural layer 40 to output "IJ", and the fourth neural layer 40 outputs "IJ". Either neuron outputs "1". therefore,
Neuron 9l of output layer 90 outputs rlJ.

As can be easily understood from FIG. 9(a), in the comparative example, the number of synabuses is 36 and the number of neurons is 10. On the other hand, in this example, the number of synapses is 30 and the number of neurons is 10, as understood from FIG. 9(b).

Therefore, logical operation (AeB) IEE} (C69D)
It is understood that when input data is processed by , 36 synapses were required in the comparative example, but only 30 synapses are required according to the present embodiment.

That is, according to this embodiment, the number of synapses is reduced by about 20%, and the same effects as described in the above embodiments can be obtained. In other words, by increasing the number of neural layers and setting the number of neurons in the neural layer constructed on the output layer 90 side to be equal to or less than the number of neurons in the preceding neural layer, the number of synapses can be reduced, and the number of synapses can be reduced. The memory capacity of the unit 100 (FIG. 1) can be reduced and the calculation speed can be improved.

FIGS. 10(a) and (b) show the sixth embodiment of the neural network together with a comparative example. In this example, input data is subjected to logical operations + (AfE9B) $ (CeD)) eE (8)
Indicates the case where processing is performed according to the following.

FIG. 10(a) shows a comparative example, where the input data group 10 is 5
The first layer 20 has 15 neurons, and the output layer 90 has 1 neuron. In the comparative example, each term obtained by expanding the above equation (8) is input to each 221-ron of the neural layer 20. Therefore, all data is processed as O-order data.

On the other hand, FIG. 10(b) shows a sixth embodiment, and this configuration includes an input data group 10, first, second, third and fourth neural layers 20, 30, 40, 50, and an output layer 90. The first neural layer 20 and the second neural layer 30 are (AeB) and (CeD)
The third neural layer 40 performs processing according to {(AeB) e(CeD)).

and a fourth neural layer 50 and an output layer 9
0, the final result is determined by { (AeB) e(CeD)) eE.

As can be understood from the comparison between FIG. 10(a) and FIG. 10(b), in the comparative example, the number of synabuses is 80 and the number of neurons is 16, whereas in the present example, the number of synabuses is 80 and the number of neurons is 16. 32, and the number of neurons is 10. According to this embodiment, the number of synapses is reduced by about 40%, and the number of neurons is reduced by about 60%. Therefore, in this embodiment as well, effects similar to those described in each of the above embodiments can be obtained.

As can be understood from the above explanation, in the present invention, the layered structure consisting of the input data group, neural layer, and output layer is optimally configured according to the order required for data processing and the order of the input data. Input data needs to be input to an appropriate layer depending on the layer structure. Note that the degree here means the degree of abstraction of data or processing content, as described above.

Now, in order for a neuron to perform the processing described above, the weights must be determined to appropriate values through learning. Therefore, in this embodiment, the weights are changed exponentially over time, as will be described later. There are three methods for modifying the weights, as disclosed in Japanese Patent Application No. 63-297541, and these will be referred to herein as Mode (2), Mode (2), and Mode (2), respectively.

In mode I, as shown in FIG. 11, the weight of a neuron is modified based on the output of that neuron. This correction method is effective when the target value of the output of each layer is clear. Now, when that neuron produces an output in response to a certain input, when that output matches the target value or is sufficiently close to the target value, the relationship between the human outputs at that time should be strengthened. This corresponds to increasing the weight of synapses given significant input. In mode I, the target value of the output of each neuron is known in advance, so the output of each neuron is compared with the target value, and when the two match or are sufficiently close, for example, 2
In the case of value input, the weight of the synapse to which r1 is input is increased.

As shown in FIG. 12, mode (2) is one in which the weights of the neurons are modified based on the final output evaluation results. This correction method is effective when determining the processing content of the data processing apparatus from a global perspective. As an evaluation method in this mode, evaluation of the Hamming distance or Pythagorean distance between the final output of the output layer and the target value, or perceptual evaluation is possible. As a result of this evaluation, if the output matches or is sufficiently close to the target value, the input/output relationship at that time should be strengthened, and at that time, for example, the weight of each synabus to which "1" is input is increased.

Mode (2) is a weight modification method for a type of learning in which inputs are memorized as they are, and strengthens the relationship between the input and the output that originally occurred for that input. That is, the 11th
In the configuration shown in the figure, the weight of the synapse to which rlJ is input in the neuron that outputs "1" in response to that input is increased.

In modifying the weights in this manner, the inventors first assumed that changes in the weights of neurons were changes in membrane potential in living nerve cells. In other words, if the weights are set similar to the membrane potential of biological nerve cells, it is thought that the efficiency of learning in the data processing device will be extremely high, similar to that of biological brain cells. Furthermore, if the weight shows a change similar to the membrane potential, the change is considered to be expressed by an exponential function like a general RLC circuit.

Therefore, the weight W is, as shown in FIG.
It is expressed as p(t) (9). where t is the learning time in each neuron,
In other words, it represents the number of times of learning.

In equation (9), if the synapse is excitatory type, the sign is 10, and the weight W starts from O and increases rapidly at first, as shown by the solid line I, and changes as time passes from the start of learning. The amount becomes smaller and reaches the maximum value W. Approaching 4. On the other hand, if the synapse is of the inhibitory type, the sign will be one;
As shown by the solid line J, the weight W starts from 0 and decreases rapidly at first, and as time passes from the start of learning, the amount of change decreases and approaches the minimum value W1.

Immediately after the start of learning, there is not much data correlation for that synapse, so the weight W at this time is set small.
Thereafter, as the data correlation increases, the weight W rapidly increases, which speeds up the convergence due to learning. On the other hand, if learning has progressed and the weight W has already become large, that synapse has sufficient data correlation in the learning up to that point. Therefore, if the weight W is changed unnecessarily, it will simply cause oscillation and impede the convergence in learning, but since the weight W is set so that it hardly changes, sufficient convergence can be achieved. can get.

Conventionally, inhibitory and excitatory neurons have been considered as the output characteristics of neurons, and in order to optimally arrange them as a neural network, a detailed study that takes into account the processing content is required. Neuron connections are complex. However, according to this embodiment, by simply selecting the sign of the weight W to be + or 1 as a characteristic of one synabus, it is possible to arbitrarily realize an inhibitory type or an excitatory type, which simplifies the circuit configuration. Increased freedom. It has been well known since Rosenblatt (1958, F. Rose) that the presence of inhibitory neurons improves the separability of data.
nblatt ” The perceptron
: a probabilistic model
for information storage
and organization in
the brain", Psychological
Rev. II+65: 386-408).

According to this embodiment, the efficiency of learning in the neural network is improved, and the final output data can be converged and stabilized quickly.

Furthermore, as described above, suppressive and excitatory characteristics can be obtained by simply changing the sign of the weight W, increasing the degree of freedom of the circuit of the neural network.

Note that the temporal change in the weight W does not necessarily need to be determined exactly as an exponential function, and may be approximated by, for example, a polygonal line.

Next, seventh to ninth embodiments of the neural network will be described, and the second basic idea of the present invention will be explained.

FIG. 14(a) shows a seventh embodiment of the neural network of the present invention, in which the learning result (A+B)
This figure shows the neural network that led to the execution of the logical operations.

This configuration has one neural layer 20, and this neural layer 20 is provided with the same number of neurons 21 and 22 as the number of data, that is, two neurons 21 and 22. Data A and B are input to each neuron 2l, 22, respectively. Each neuron 21, 22 has a weight Wi in a connection part with the input path of each data, that is, a synapse, and a threshold value θ. The weight W, changes due to learning, and the neuron comes to perform a predetermined process. In this embodiment, as a result of learning, only one neuron 21 performs the logical operation (A+
B) is performed, and the other neuron 22 does not substantially act. That is, the neuron 21 has, for example, W+=1,
When W2=1 and θ=1, and AW, +BW2≧1, output data “1” is output. On the other hand, neuron 2
2 is set to, for example, W3=0, W4=0, θ=1, so that always A W 3 + B W a < 1 and the threshold {direction θ is not exceeded, and the output data “0
" is output.

Thus, when at least one of the data A and B is "lJ," the neuron 21 outputs the output data rl, and the neural network of this embodiment executes the logical operation (A+B).

FIG. 14(b) shows an eighth embodiment, and this embodiment shows a neural network that has come to execute the logical operation of the learning result (AeB). This configuration has two neural layers 20 and 30, the first neural layer 20 is provided with neurons 21 and 22, and the subsequent neuron 30 is provided with a neuron 3L32. Neuron 21 of the first neural layer 20
, 22, data A and B are input.

Logical operation (AeB) is expanded as (AB+AH),
In the neural layer 20, neurons 21 (/
The neuron 22 processes (AB). That is, the neuron 21 has, for example, W+ =-
When L Wz =1 and θ=1, and AWI +BW2≧1, output data “1” is output. On the other hand, the neuron 22 is set to, for example, W3=1, W4=1, and θ=1, and outputs output data “1” when AW3 +BW4≧1.

The three neurons of neural layer 30 are (AB+A
E! ), for example, W,=1, W6=1, θ-
1, the output of neuron 21 is Yl, and the output of Euron 22 is Y2, then y, W, +Y2 Wb
When ≧1, output “1”. On the other hand, neuron 32 does not substantially function.

Therefore, the neuron 31 outputs output data "1" when only one of the data A and B is "1", and both of them output "1".
” or “0”, output data “0” is output, and the neural network of this embodiment executes a logical operation (AeB).

FIG. 14(c) shows a ninth embodiment, and this embodiment shows a neural network that has come to execute the logical operation of (A+B)C as a result of learning. This configuration is 2
The first neural layer 20 is provided with neurons 21, 22, and 23, and the subsequent neuron 30 is provided with neurons 31, 31, and 30.
32 and 33 are provided. First stage neural layer 20
Data ASB and C are input manually to the neurons 21, 22, and 23.

In the neural layer 20, the neurons 21 are (A
+B) is performed, the neuron 22 does not substantially act, and the neuron 23 outputs the input data C as is. That is, the neuron 21 has, for example, W,=1, w. =
1, W3=O, θ=1, and when A W + + B W Z + C W z≧1,
Outputs output data "1". On the other hand, in the neuron 22, the weights W4, Ws, and Wb are set to O, and the threshold value θ is set to 1, so that the neuron 22 does not substantially act. Further, the neuron 23 has, for example, a weight W7=0, W,=
0, W,=1, θ=1, and when AW7+I3we+CW,l≧1, output data “1” is output, and at other times, output data “0” is output.

The neuron 31 of the neural layer 30 processes (A+B)C based on the output data of the neuron 2123 of the neural layer 20, for example, Wz=1, W+
2=O, W+3=1, θ=2, neuron 2
The output of neuron 1 is Y, the output of neuron 22 is Y2, and the output of neuron 23 is ? If it is 3, then Y + W + + 10Y z W r ■ 10Y3Wl3
When ≧2, output data “1” is output. On the other hand, neurons 32 and 33 do not substantially act.

Therefore, neuron 3] outputs output data ``1'' when at least one of data A and B is ``1'' and data C is ``1.'' 10B) Execute C.

The second basic idea of the present invention will now be explained.

In the seventh embodiment, data A and B are one operator r+
(OR)J, and this logical operation (A+
B) is performed by one neural layer 20.

In the eighth embodiment, data A and B are r(B(EX-
OR) J, and this logical operation (AeB
) is (AB+A113) and H open h6.

Then, in the first stage neural layer 20, λB and AE
is executed, that is, a logical operation on the operator rx (AND) is executed. Next, in the second neural layer 30, a logical operation is performed on the operator "+(OR)J". executed.

In the ninth embodiment, data A and B are one operator r-
1-(OR)J, and this logical operation is executed by the neural layer 20 at the first stage. The data C is the operator rX (AN
D) are connected by J, and this logical operation (A+B)
C is executed by the second stage neural layer 30. Thus, the logical operations in the ninth embodiment are executed by two neural layers.

In this way, when the processing content of the neural network is expressed by the logical operators rANDJ and rORJ, the number of neural layers increases depending on the number of logical operators or the configuration of the logical operations.

Note that the order of each data is as described above, and according to its definition, for example, in the eighth embodiment that performs a logical operation (/IB), if data A and B are 0th order, each of the first stage neural layer 20 AB and AE processing are executed in the neurons 2 and 22, respectively, and the primary output data is input to the neuron of the second stage neural layer 30. Then, in the second new layer 30,
(XB+AB) processing is executed and secondary output data is output. That is, the final output data is quadratic,
The logical operation (AeB) is considered to be processed by the number obtained by subtracting the order of input data from the order of final output data, that is, two neural layers.

The inventors can determine the number of neural layers by determining how many degrees higher the order of the final output data is with respect to the input data. It is estimated that the number is the order of the data minus the order of the human data. This is the second aspect of the present invention.
This is the basic idea. As mentioned above, the degree is the abstraction level of data and is determined by the properties of the data. For example, in image recognition, pixel data is 0th order,
Endpoint data, large number data, or Euler number data are of higher order. For example, when obtaining end point data from pixel data, it is sufficient to take into account the degree of end point data, that is, the degree of abstraction, and provide a number of neural layers equal to the degree of end point data minus the degree of pixel data. An example in this case will be described later with reference to FIGS. 16 and 17.

FIG. 15 shows a tenth embodiment of the neural network, and this example shows the result of learning, input data A,
A case is shown in which B, C, and D are processed according to the logical operation (AeB) e(CeD). Note that A, B
, C and D are "1" or rOJO:) digital values, and the result of this logical operation will also be explained as being output as rl, or a digital value of "0".

This example has four neural layers 20, 30, 4
0, 90, and the final stage neural layer 90 is an output ray that outputs final output data. It is. The first neural layer 2o has four neurons 21, 22, 23
, 24; similarly, the second neural layer 30 has four neurons 3l, 32, 33, 34, and the third neural layer 40 has four neurons 4142, 43.
, 44, and the output layer 90 has four neurons 91, 9
2, 93, and 94. Each data A to D is input to each neuron of the first neural layer 2o. Note that each neuron is connected to each neuron in the adjacent neural layer, but for the sake of simplicity, lines that are not substantially related to the action are omitted from the diagram.

Each neuron has a weight Wi by which input data is multiplied and a threshold θ, and according to (1) 2 above, when the sum of the products of each input data and the weight is greater than or equal to the threshold, the output data “
1'', and when this sum is smaller than the threshold θ, output data r■, is output.

36 El performance) E (A eB) Ha, (AB+
AB) is opened, and in the neural layer 20, the neuron 21 processes (AB), and the neuron 22? (AU) is processed. Also logical operations (CeD)
is expanded as (CD+CI5), and neuron 23 is (
The neuron 24 processes (CI15).

That is, the neuron 21 has, for example, W21=1, W
2■-1, Wzz=O, W24=O, θ1 is set, A Wz+ + B Wzz + C Wz3+D W
When ta≧1, output data “1” is output. The neuron 22 is, for example, W2,=1, W26=l,W!
? = '0, Wza=O, θ=1, A Wzs+ B WZ&+ C w2? ＋D W2
[When 1≧1, output data “1”. Similarly, the weights WL and threshold values θ of the neurons 23 and 24 are determined.

The neurons 31 of the neural layer 30 are (AB+A
Er) (7) Perform the processing, for example, W:u = 1,
When Wzz=1, Wz3=O, W34=0, θ=1, and the outputs of neurons 21, 22, 23, and 24 are K, L, M, and N, respectively, ? W ff++ LWs■+MW3:I+ NW* 4
When ≧1, output data “1” is output. Similarly, the neuron 33 processes (CD+CD5), and when at least one of the outputs of the neurons 23 and 24 is "1",
Output data r1. Furthermore, neurons 32, 3
Each weight of 4 W. is set to 0, and these neurons have virtually no effect.

Therefore, neuron 31 outputs the result of (AeB), and neuron 33 outputs the result of (CeD).

The outputs of neurons 3l, 32, 33, and 34 are expressed as E
, F, G, H, the neuron 41 of the neural layer 40 processes (EG'), and the neuron 4
3 performs the processing of (EC). That is, neuron 41
For example, W41=1, W4■=0, Wa3=
1, Waa=O, θ=1, E Wa+ + F Wa■+GW41+HW44≧1
When , output data r1, is output. Similarly, the neuron 43 has, for example, W45=1, W46=O, W47""
l − W411=O, θ−l, EW
．． To +F Wab +G W47 + H W4e≧1
When , output data r1, is output. neuron 42,
Each of the 44 weights WI is set to O and these neurons have virtually no effect.

The neuron 91 of the output layer 90 is (EG+EC)
For example, Wq+=I, Wqz=O, Wq3
=j, Wl=0, θ=1, neuron 41,
The outputs of 42, 43, and 44 are respectively P and Q. ．． R.S.S.
Then, P W91 + Q W92 + R Wqy +S
When W94≧1, output data “1” is output. Neurons 92, 93, 94 have virtually no effect. If the purpose of use is thus limited and the number of output data is clear, neurons that do not substantially function can be omitted.

Therefore, the neuron 91 outputs the result of (Eel), that is, the result of (AeB)e(CeD).

The order of output data in logical operations (AeB) and (CeD) is determined by the operator "e(Eχ-OR)" as described above.
" is replaced by two operators rANDJ and "ORJ, so they are each 2. Therefore, the order of the output data in the logical operation (AeB) e(CeD) is 4, and this logical operation has the same number of input data. (4
It is reliably processed by a 4-layer neural layer with 1) neurons.

FIGS. 16 and 17 show a data processing device for determining the end points of a figure.

Here, how to arrange the end points of a figure is as shown in Fig. 7 (
b) It is assumed that when any of the patterns (i) to (viii) occurs, the central pixel (pixel E in FIG. 7(a)) is located at the end point. This end point is determined by pixel A other than the center pixel.
-D, F~■ Any one of figure density (for example, "1")
), and the center pixel E is defined as an "endpoint" when it has a graphic density, and otherwise as "not an endpoint".

A neural network for this determination is configured, for example, as shown in FIG. 16, which shows an eleventh embodiment of the present invention. This neural network consists of a first neural layer 20 with nine neurons 21-29.
, a second neural layer 30 having nine neurons 31-39, and an output layer 90 having nine neurons 91-99. The data of pixels A to ■ are input to the first neural layer 20.

The neuron 21 of the first neural layer 20 outputs output data rlJ when only the pixel A is "1" among the pixels A to ■ excluding the pixel E.

Similarly, neurons 22, 23, 24, 25, 26, 2
7 and 28 are pixels B, C, D, F, G, H, and I, respectively.
When only one of them is "1", output data "1" is output. Therefore, any one of pixels A-D, F-■
”, one of neurons 21 to 2 outputs output data “l”. On the other hand, the neuron 29
Output the data as is.

The neuron 31 of the second neural layer 30 outputs output data "1" when the output of the neuron 2329 is "l", that is, when the pixel and E are each "1". Similarly, neurons 32-38 are connected to pixel B (
! : When E is "1", pixel C and E are "1", pixel D
When and E are "1", when pixels F and E are "1", when pixels G and E are "IJO", when pixels H and E are "l", when pixels I and E
When is "1", output data "engine" is output respectively. Note that the neuron 39 is not actually involved in this end point determination process.

The neuron 91 of the output layer 90 outputs the output data "1" when at least one of the neurons 31 to 3 of the second neural layer 30 outputs the output data "1", that is, as shown in FIG. 7(b).
When any of the patterns (i) to (viii) occurs, output data "1" is output. At this time, it is determined that the central pixel E is at the end point. Furthermore, neurons 92-9
9 is not substantially involved in this end point determination process.

If each pixel data A-1 is considered to be O-order data, the output of the neuron 91 is cubic data, and three-stage logical operations are performed in the end point determination process. That is, in the neural layer 20, a logical product (for example, in the neuron 21, (ABCI5FCRT)) is taken to determine whether only one of A to D, F-1 is "l". In the neural layer 30, A-DSF-1
Only one of them is "1" and E is "1" (for example, neuron 3
In engineering, (A[DFC;F{T − E)) is taken. In the neural layer 90, E is "1" and A
A logical OR is determined that any one of -D, F to ■ is "1".

Regarding this end point determination process, neural layer 3
0, E is "1" and any one of A to D, F-1 is "1", and by this, the end point is determined by two neural layers. It is also possible to make a judgment. However, if the difference in order between the output data and the input data is 3, the endpoint determination process can be performed reliably by providing at most three neural layers.

FIG. 17 shows a twelfth embodiment of the invention. The neural network in this example consists of 9 neurons 2
A first neural layer 20 having neurons 1 to 29, a second neural layer 30 having nine neurons 31 to 39, and an output layer 90 having nine neurons 91 to 99. The data of pixel A-1 is input to the first neural layer 20.

The neuron 2l of the first neural layer 20 outputs output data "1" when eight or more of the pixels A-D and F-I are "1". The neuron 22 has pixels A-D.
, F-1, when 7 or more of them are "1", the output data "
1" is output. Similarly, neurons 23, 24, 25
, 26, 27, 28 are pixels A-D. ．． F~
6 or more, 5 or more, 4 or more, 3 or more of ■,
When two or more and one or more are "1", the output data "
1" is output. Neuron 29 outputs the data of pixel E as is.

The neuron 31 of the second neural layer 30 outputs the output data "1" when only the neuron 28 among the neurons 21 to 2 of the neural layer 20 outputs "1j".
Output. That is, the neuron 31 has pixels A to D.
, F to D is "1", the output data "
1" is output. The neuron 32 outputs the data of the pixel E as is. Note that the neurons 33 to 39 are not substantially involved in this end point determination process.

The neurons 91 of the output layer 90 are neurons 3l,
32 to determine whether they both output "1" or not, and only one of the pixels A to D, F to ■ outputs "1".
1” and E is “l”, the output data is “1”.
" is output. Note that the neurons 92 to 99 are not substantially involved in this end point determination process.

Therefore, in this embodiment, end point data is determined by three neural layers.

In the seventh to twelfth embodiments described above, the order of data is the number of processes performed on the data, and each process is performed by a respective neural layer. Here, as an example of the processing content, the logical operator (17) rAND, .
rORJ, rNANDJ, rNOR, and rEX-
In the case of ORJ and rEX-NORJ, rAND,
Or it must be converted to "OR". This is because "EX-OR, etc. cannot be processed by one neural layer.

Note that the processing content is not limited to what is expressed by logical operators, but is determined by the nature of the output data.

(Effects of the Invention) As described above, the present invention is configured to process feature data of an image extracted by an image processing section using a neural network and perform image recognition. Therefore, the self-learning function of the neural network improves the performance of image recognition, and the associative function expands the scope of image recognition. Therefore, according to the present invention, it is possible to obtain an image recognition system that is capable of performing various image recognition and can increase the recognition rate.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an image recognition system to which an embodiment of the present invention is applied, Fig. 2 is a block diagram showing a feature processing section, Fig. 3 is a block diagram showing a recognition section, and Fig. 4 is a general A conceptual diagram showing a neuron, FIG. 5 is a conceptual diagram showing a general neural layer, FIG. 6(a) is a conceptual diagram showing a comparative example, FIG. 6(b) is a conceptual diagram showing another comparative example, Figure 6 (C)
is a conceptual diagram showing the first embodiment of the neural network of the present invention, FIG. 7(a) is a diagram showing 3x3 convolution in graphic processing, and FIG. 7(b) is a diagram showing the state of graphic density of each pixel. , FIG. 7(C) is a second embodiment of the neural network, and is a conceptual diagram showing an example of a configuration for determining end points in graphic processing. FIG. 8(a) is a third embodiment of the neural network. Conceptual diagram, Figure 8(b) is a conceptual diagram showing the fourth embodiment of the neural network, Figure 9(a) is a conceptual diagram showing a comparative example, Figure 9(b) is the fifth implementation of the neural network. Conceptual diagram showing an example; Figure 10(a) is a conceptual diagram showing a comparative example; Figure 10(b)
is a conceptual diagram showing the sixth embodiment of the neural network; FIG. 11 is a conceptual diagram of a data processing device that performs mode I learning; FIG. 12 is a conceptual diagram of a data processing device that performs mode ■ learning; is a graph showing the temporal change in weight, Figure 14 (
a) is a conceptual diagram showing the seventh embodiment of the neural network; FIG. 14(b) is a conceptual diagram showing the eighth embodiment of the neural network; FIG. 14(C) is a conceptual diagram showing the ninth embodiment of the neural network. Conceptual diagram; Figure 15 is a conceptual diagram showing the tenth embodiment of the neural network; Figure 16 is a conceptual diagram showing the eleventh embodiment of the neural network; Figure 17 is a conceptual diagram showing the twelfth embodiment of the neural network. It is. 20, 30, 40, 50, 90... Neural layer 21-24, 31-34, 41, 42 91-93... Neuron 100... Recognition section 200... Input section 300... Image processing Figure Figure Can T Figure Figure (i) (iV) (ii) (v) Figure (City) (vi) Figure Figure Can j Figure (a) (b) (C) Figure

Claims (1)

[Claims] (1) An input unit that inputs images; an image processing unit that processes the input images and extracts features; A recognition unit that includes neurons that output data in parallel and has a neural layer with a layered structure depending on the level of abstraction of the extracted data obtained from the image processing unit, and performs image recognition based on the extracted data. An image recognition system equipped with