JPH02291980A - Verification of logic circuit - Google Patents

Abstract

PURPOSE:To enable performing of evaluation of verifying work of a logic circuit and a test vector by converting a logic circuit designed into a circuit of a programable logic element to realize as actual circuit for verification. CONSTITUTION:A logic circuit 10 designed is converted to a circuit of a programable logic element (PLD), for example, using a developing tool 20. The circuit thus converted is realized as actual circuit for verification containing the PLD, for example, at least one microprocessor (CPU) chip 34 arranged almost at the center of a system board 32 and a programable one-board computer 30 containing a plurality of PLDs 36 arranged surrounding the perimeter of the CPU chip 34. Then, a function, timing and the like of th logic circuit 10 are verified with a tester 42 into which a test vector is inputted from a trouble simulator 40 using a circuit realized in the circuit 30 for verification.

Description

[Detailed description of the invention] [Industrial application field]

The present invention provides a logic system that allows designed logic circuits and their test vectors to be verified and evaluated in a short time using circuits actually realized using programmable logic elements at each design stage. It is related to circuit verification methods.

[Conventional technology]

The large number of integrated components and their complex relationships in large-scale integrated circuits make it nearly impossible for designers to predict all the outcomes at each design stage. Furthermore, the cost of design errors, even at the prototyping stage, is extremely high. To minimize the possibility of such costly errors, there is a great need for designers or computer tools to analyze and verify their designs before they go to very costly silicon fabrication. There is. When designing a conventional IC, the process moves from the stage of an abstract idea in the designer's head to the stage of architectural specifications (register transfer level (RTL)), which is a combination of black boxes, for example, and then
For example, we move on to the schematic logic design stage (gate level), which is a combination of circuit blocks, then move on to the circuit design stage (transistor level), which is a combination of transistor circuits, and then go through the mask layout stage on silicon. It becomes concrete. Furthermore, there is a stage in which failure tests are designed for the completed product. Therefore, when designing a large-scale system and realizing it by combining actual large-scale integrated circuits, it is important to ensure that the design is correctly reflected at various stages. The above-mentioned verification work to confirm whether or not the situation is true is extremely important. Conventional verification work at each design stage is, for example, at the initial stage in the designer's mind.
The designer himself, for example, thinks about it in his head and performs verification work.
At the next RTL level, the designer similarly performs verification work in his head, or performs functional simulation (RTL simulation) by calculation using a logic simulator using a personal computer level computer. Regarding the next gate level, we will perform a functional simulation by calculation using a logic simulator using a PC-level computer. At the next transistor level, we use a PC-level computer to perform calculation-based timing analysis using a timing simulator. Furthermore, in the mask layout 1 stage, a circuit is extracted from the mask data using an intermediate level computer, and a timing analysis is performed on it by calculation using a timing simulation. In addition, regarding the final product failure test stage 1, a large-scale computer or supercomputer-level computer is used to perform a failure simulation (fault simulation) using a test vector (test pattern) generated by the design name, for example. is done by calculation.

[Problem to be achieved by the invention]

However, in conventional verification work, as shown in FIG. For example, when performing a logic simulation of 10,000 gates on an IMIPS machine,
Verification takes more than an hour, and even more time is required for processes above the transistor level. Also, designer 12
Since the design circuit 10 is modeled and input into the computer 14, verification omissions and misunderstandings are inevitable. Furthermore, there were other problems, such as timing, etc., which did not adequately correspond to reality. In order to evaluate whether the test vectors for performing the Fault detection rate using the test I/vector (for circuits where fault detection is not taken into account, approximately 70% or more for simple faults that are not complex faults, and for circuits that take fault detection into account, 95% for simple faults as well) However, in the method of generating faults in each part of the modeled logic circuit one by one and running test I/vector calculations, simulation calculations are required for each fault part. It is necessary to repeat. Therefore, even for a test vector of about 3 seconds, calculations on a yearly basis are required to accurately evaluate and create a fault coverage rate. Furthermore, the input pattern for device testing (DUT 1D
ev+ce LJnder Testing input pattern) to obtain the output pattern to be used as a comparison standard required calculations on the same machine, which also took a long time. Showa 63-1570
72, especially for the latter, to check the operation of large-scale circuits instead of the software simulators mentioned above,
It is disclosed that a hardware simulator is used, which is created by assuming a necessary integrated circuit module and writing code data corresponding to logic specifications into the PLD of the specified integrated circuit module. However, the hardware simulator includes regular ICs such as PLD, EPROM, RAM, etc.
Since the configuration was such that a wide variety of integrated circuit modules could be optionally added in series, it was necessary to store a large number of integrated circuit modules that were not needed depending on the logic circuit, making the configuration of the hardware simulator complex. It was. The present invention has been made in order to solve the above-mentioned conventional problems, and is a logic circuit that can quickly perform logic circuit verification using an actual verification circuit realized with a simple configuration. The first task is to propose a verification method. The present invention also provides practical verification Ol! The second challenge is to make it possible to quickly evaluate test vectors using A third object of the present invention is to make it possible to quickly create an output pattern when inputting a DUT input pattern using an actual verification circuit.

[Means to solve the problem]

The present invention is a logic circuit verification method that converts a designed logic circuit into a programmable logic element circuit, implements the converted circuit into an actual verification circuit including a programmable logic element, and The first problem is achieved by verifying the logic circuit using a circuit realized as a verification circuit. Further, the verification circuit may include at least one microprocessor chip disposed approximately in the center of a system board, and a plurality of programmable logic elements disposed substantially surrounding the microprocessor chip. It is a programmable one-board computer that includes at least one computer. Furthermore, the second problem has been achieved by evaluating test vectors for fault simulation using the circuit realized as the verification circuit. Also, using the circuit realized as the verification circuit, CUT
The third problem is achieved by creating an output pattern of the logic circuit when an input pattern is input.

[Operation and Effect End] In the present invention, as shown in FIG. 1, a designed logic circuit (design data) 10 is transferred to a development tool 20,
The converted circuit is converted into a circuit of a programmable logic element <PLD) using In this case, a programmable one-board computer 30 including at least two microprocessor (CPU) chips 34 and a plurality of PLDs 36 arranged almost surrounding the CPU chip 34 is realized. Using the circuit implemented in the circuit (30), the logic circuit 1 is tested by a tester 42 to which a test vector is input from, for example, a fault simulation 40.
I am trying to verify the functions and timing of 0. In this way, the logic circuit 10 is constructed as a verification circuit <<3> with a simple configuration.
0》 and perform verification work on the actual circuit, verification can be performed in real time, which is much faster than calculation, and verification work can be performed quickly. In particular, since it uses an actual circuit, there is very little chance of making a mistake. Furthermore,
Since it uses a programmable logic element circuit, it is not only easy to get used to it, but also easy to convert the designed logic circuit into a verification circuit. Further, when the programmable one-board computer 30 is used as a verification circuit, any verification circuit can be easily realized. As the logic circuit 10, that is, the design data that can be verified in the present invention, for example, the above-mentioned R
In the case of TL, Nick T redennick is one of the procedures for designing computer processes.
Data based on the flowchart method proposed by Mr.
UTER81.12 PP87-102) or data using any behavioral description language can be used. Furthermore, at the gate level, for example, a schematic data representing a combination of circuit blocks can be used. Furthermore, if it is at the transistor level (1), for example, data of a transistor circuit diagram can be used. Further, at the mask layout level, for example, circuit data based on a combination of circuit elements extracted from the mask layout can be used. Furthermore, if the product is made according to the design and is at the failure test level to test whether there are any internal failures such as element defects or disconnections, then the design data at any stage can be analyzed using any method, such as a simulation engine, Product test data (Test Vector 44) generated by failure simulators, test vector generators, etc. can be used. That is, as shown in Fig. 2, it is possible to conduct an experiment by assembling a circuit in which a failure has been intentionally caused in an actual 13l (30), so that test vectors in seconds or minutes can be evaluated in real time. Therefore,
It is now possible to quickly evaluate and create test vectors for the final lecture, which previously took more than a year. Furthermore, as shown in FIG. 3, the device test input pattern <
DUT input pattern》46 Output pattern 48 when using human power can also be created extremely quickly in real time. [Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The verification method according to the present invention includes, for example, as shown in FIG.
An input interface device 50 for inputting a logic circuit designed by a designer, for example, a conventional logic circuit and a PLD.
a database 52 in which conversion data of combinations of circuits are stored; and an arithmetic unit that converts a logic circuit input from the input interface device 50 into a PLD circuit using the data stored in the database 52. 54 and
A write control circuit 5 for realizing the circuit converted by the arithmetic unit La 4 into an actual verification circuit including a PLD, for example, the programmable one-board computer 30.
6 and a writing device 58 are used. The database 52 includes, for example, as shown in FIG.
Each design stage [e.g. logical design level including block diagrams, flowcharts, state transition tables, state transition diagrams, etc., hardware including functional descriptions expressed in definition formulas including CS code representing the current state and NS code representing the next state] A combination of the conventional partial (peripheral) circuit design at the software description language (HDL) level and the schematic diagram including schematic diagrams expressed in symbols and the data of the transistor-level PLD circuit that realized it. For example, data such as which microprocessors and how many were used, how many peripheral chips (memory, TTL, PLD) were used, how they were wired, etc., is compiled into a library as design assets and can be handled accordingly. A large number of data are accumulated for each partial circuit. Therefore, as shown in FIG. 6, the calculation section 54, for example,
Partial circuits A, B, and C obtained by dividing the input logic circuit 10
, D, E are selectively retrieved from the database 52, and the actual circuits corresponding to P in the one-board computer 30 are
By attaching each to the LD separately, the layout and wiring of the circuit are determined. When converting to an actual circuit, for example, it may be difficult to directly convert data at the logic design level into an actual circuit, so first, the data is reduced to the HDL level, and then converted to the HDL level.
It is also possible to convert L level data into an actual circuit. In this way, a test signal is input from the tester 42 to the verification circuit implemented on the programmable one-board computer 30, thereby performing real-time verification using the actual circuit. Also, when evaluating the fault coverage rate of test vectors,
As shown in FIG. 2, instead of design data, faulty circuit data in which internal faults such as element failures and disconnections are intentionally generated is used to realize the faulty circuit in the one-board computer 30. By inputting a test vector into a faulty circuit, the fault coverage rate of the test vector can be quickly evaluated in real time. When creating an output pattern for a DUT input pattern, as shown in FIG. You can quickly obtain the desired output pattern in real time. Therefore, combinations of input and output patterns can be easily obtained. In addition, in the above embodiment, as an actual verification circuit,
Although a programmable one-board computer 30 consisting of two CPUs and many PLDs was used, the type of verification circuit is not limited to this. For example, as in the modification shown in FIG. 7, the number of PLDs 36 is further increased, and the C
For example, the PU 34 is surrounded twice, and an external memory element, for example, a FROM 38, for defining the internal circuit of the PLD 36 is placed in a part of the PU 34, for example, at the four corners, as shown in FIG. As in the other modified example shown, the CPU 34 is arranged so as to almost surround it.
A plurality of large-scale programmable logic devices (PLDs) 36A (9 pieces in the figures) and a plurality (28 pieces in the figures) of small-scale gPLDs 36B arranged outside the large-scale PLD 36A.
You can use something composed of . In the example shown in Fig. 8, the large-scale PLI 36A (for example, for Cobrosesa) that normally requires high functionality is placed near the CPU 34, so it can operate efficiently and at high speed, making it suitable for the hierarchical benefit system. It is suitable. Of course, the large-scale PLD36A
Alternatively, it is also possible to replace a part of the small-scale PLD 36B with a FROM38 similar to the example shown in FIG. It is also possible to make a microprocessor chip just the central core, excluding memory and input/output. In this case, the memory and input/output circuits included in a normal microprocessor can be configured with peripheral PLDs, which is particularly effective for the development of CPUs. Further, as the PLD, one including a memory for a computer system can also be used. In this case, since the memory of the computer system is built into P and D, access is quick and high-speed operation is possible. Of course, PLD
Independently from the external DRAM on the system board,
Memory for the computer system, such as ROM, may also be provided.

[Brief explanation of drawings]

1 to 3 are diagrams for explaining the outline of a logic circuit verification method according to the present invention, and FIG. 4 is a block diagram showing the configuration of an apparatus for implementing the present invention. 5 is a diagram showing an example of a database provided in the device; FIG. 6 is a diagram illustrating a method of converting a logic circuit into a PLDu path in the embodiment; FIGS. 8th
The figures are plan views showing the configurations of modified examples of the verification circuit, and FIG. 9 is a diagram for explaining the outline of conventional verification work. 10...Logic circuit (design data), 20...Development tool, 30...Programmable one-board computer, 3
2... System board, 34... Microprocessor (CPU) chip, 36
, 36A, 36B...Programmable logic device (PLD), 42...
Tester, 44... Test vector 46... Device test (DUT) input pattern, 48
...Output pattern.

Claims (4)

[Claims] (1) Convert the designed logic circuit into a programmable logic element circuit, realize the converted circuit into an actual verification circuit including the programmable logic element, and convert the realized circuit into the verification circuit. A method for verifying a logic circuit, characterized in that the logic circuit is verified using the following method. (2) In claim 1, the verification circuit includes at least one microprocessor chip located approximately in the center of the system board, and a plurality of verification circuits located substantially surrounding the microprocessor chip. A method for verifying a logic circuit, comprising: a programmable one-board computer including at least a programmable logic element. (3) A logic circuit verification method according to claim 1 or 2, characterized in that a test vector for fault simulation is evaluated using a circuit realized in the verification circuit. (4) A method for verifying a logic circuit according to claim 1 or 2, characterized in that an output pattern of the logic circuit when an input pattern for device testing is input is created using a circuit realized in the verification circuit. .