JPH02290318A - Digital filter - Google Patents

Abstract

PURPOSE:To prevent production of a limit pattern at the time of inputting non signal by generating a data pattern corresponding to a pattern appearing as a feedback signal at the time of inputting the non signal and adding the signal to a feedback signal. CONSTITUTION:A data pattern Pj from a data pattern generating circuit 1 resulting from sampling a data pattern of a feedback signal from a digital filter when no signal exists in advance is added to an input signal Xi via an adder A1 to obtain a signal Xij. The signal Xij is inputted to the digital filter comprising adders A2-A5, multipliers M1-M4 and delay circuits D1, D2. Thus, the production of a limit pattern at the time of inputting non signal is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter having a feedback loop consisting of an adder, a multiplier and a delay element.

[Prior Art] In general, a digital filter, such as an n-th order cyclic filter, is constructed of a feedback loop consisting of an adder, a multiplier, and a delay element. FIG. 3 shows an example of a conventional second-order recursive digital filter.

That is, the input signal X, is added to the feedback signal in the adder A2. The output W, becomes data w+-+N Wl-2 via delay elements D1 and D2, respectively, and these are sent to the multiplier M. ．． M. are multiplied by β, , β2, respectively, and the adder A3
and is added to the adder A2 as the feedback signal. Furthermore, the output data Wl- of the delay elements DI and D2
1 1 W+-2 is α1, α2 in multipliers M3 and M4, respectively.
After being multiplied, they are added by an adder A5, and the addition result and the data W are further added by an adder A4 to become output data Y.

This digital filter realizes the difference equation shown in equation (1) below.

W + = X r+β1・Wl−1+β2・W1−2
Y l= W ++α1・Wl−1+α2・W,−2・
...(1) (i=... -2, -1.0.1.2....) However, here, X is the input signal NYI, the output signal is α8, α2
, β,, β2 are coefficients, W l. -1 1 Wl-2 are respective output signals of delay elements DI and D2.

[Problems to be solved by the invention However, the above-mentioned conventional digital filter
Since each of the delay elements, adders, and multipliers can only handle a finite word length (number of bits), errors due to rounding, truncation, etc. inevitably occur. Due to this error, the calculation within the feedback loop becomes nonlinear, and even though the input signal is O,
A mint cycle may occur where the output from the feedback loop does not asymptotically approach O but converges to a constant value or approaches a periodic waveform. Particularly in the filtering of audio signals, such a limit cycle results in a noise output when no signal is input, causing a problem that cannot be ignored.

It is also possible to minimize the error when rounding to a finite word length by increasing the operation word length, but if you increase the operation word length to a level that does not cause any practical problems, adders, multipliers, and delay circuits The disadvantage is that the circuit becomes larger and the circuit scale increases.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a digital filter that can prevent limit cycles from occurring even when no signal is input without changing the operation word length.

[Means for Solving the Problems] The digital filter according to the present invention is a digital filter having a feedback loop consisting of an adder, a multiplier, and a delay element, in which a data pattern corresponding to a pattern appearing as a feedback signal when no signal is input is provided. and an adder that adds the output of the data pattern generation circuit and the feedback signal.

[Function] According to the present invention, a data pattern corresponding to a pattern appearing as a feedback signal when no signal is input is outputted from a data pattern generation circuit, and the output of this data pattern generation circuit and the feedback signal are added. Therefore, it is possible to prevent the occurrence of a limit pattern when no signal is input.

? Embodiments Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a second-order cyclic digital filter according to a first embodiment of the present invention.

The circuit of this embodiment is different from the conventional circuit shown in FIG. 3 in that an adder A1 is added before the adder A2, and the input signal The point is that the data pattern P from the newly provided data pattern generation circuit 1 is supplied to the data pattern generation circuit 1. The data pattern P may be determined based on, for example, sampling the feedback signal of the digital filter when no signal is input in advance.

Note that the other configurations are the same as those shown in FIG. 3.

In the digital filter according to this embodiment, input data Xl is input to adder A. It is added to the data pattern PJ in the data pattern PJ to become the data Xll. This data XII becomes input data to the recursive filter.

Therefore, in this circuit, the differential equation of equation (2) below is calculated.

W+=X+++β1・W, -1+β2・W1-2=PJ
+Xl+β1・Wl−1+β2・W1−2Y1=W,
+α1・W, −, +α2・W... (2) ? i=...0. 1, 2, ...) In this way, according to the circuit of this embodiment, even when the input signal XI is 0, the pattern data PJ can prevent the input to the feedback loop from becoming 0. , the occurrence of limit cycles can be effectively prevented.

FIG. 2 is a diagram showing the configuration of a digital filter according to a second embodiment of the present invention. The circuit shown in FIG. 2 consists of the cyclic filter section 21.2■+
23 + 24 connected in cascade, adders AI and A add the data pattern P output from the data pattern generation circuit 1 in consideration of the passband characteristics of the filter.
5 as part of the recursive filter section 2. ．． It is added only to the return section of 24.

Further, this circuit includes a recursive filter section 21+2. This is an example in which a low-pass filter is constructed by the cyclic filter sections 23 and 24, and a Takagi pass filter is realized by the recursive filter sections 23 and 24, and the entire band-pass filter is constructed.

The data pattern generation circuit 1 generates a data pattern PJ of a frequency that passes through a low pass filter and is blocked by a Takagi pass filter.

According to this circuit, the input signal XI to the filter is added to the data pattern P output from the digital pattern generation circuit 1 by the adder A1, and the input signal XI to the filter is added to the data pattern P output from the digital pattern generation circuit 1.
1 input signal X. becomes. When the frequency component of the output P, of the digital pattern generation circuit 1 in this input signal Xll passes through the recursive filter sections 2, 22, and the data pattern P, is added to the input of the recursive filter section 23. shows the same effect as . Since this data pattern P, is blocked by the recursive filter section 23 constituting the Takagi pass filter, the output P, of the digital pattern generation circuit 1 is input to the adder A before the input of the recursive filter section 24.
5 is added.

In this way, even when cascading cyclic filters,
It is not necessary to add the data pattern PJ to all the feedback loops, and even if the input signal X1 of the filter is O, it is possible to have a configuration in which the inputs of all the feedback loops do not become O.

[Effects of the Invention] As explained above, according to the present invention, by adding the data pattern output from the data pattern generation circuit to the feedback signal, it is possible to add the data pattern output from the data pattern generation circuit to the feedback signal, thereby reducing the Limit cycles that occur can be prevented. Therefore, the operation word length can be set to the minimum length necessary to match the characteristics of the filter, and noise output due to rounding of operations can be prevented without increasing the amount of hardware. can do.

[Brief explanation of drawings]

FIG. 1 shows a digital camera according to a first embodiment of the present invention. FIG. 2 is a block diagram showing the structure of a digital filter according to a second embodiment of the present invention, and FIG. 3 is a block diagram showing the structure of a conventional digital filter. 1; data pattern generation circuit, 2l to 24: cyclic filter section, At to A5, A■2 to A15, A4■
to A45; adder, M. ~M41M1I~M1
41 M4■ to M44; Multiplier, D I+ D2 +
D Il+D I2+ D 41+ D 4. ;Delay elements A, ~A5: Rabbit IL gain M1 to M4 ; * * Device DI, D2 r slow rat system 10

Claims (1)

[Claims] (1) In a digital filter having a feedback loop consisting of an adder, a multiplier, and a delay element, there is a data pattern generation circuit that outputs a data pattern corresponding to a pattern that appears as a feedback signal when no signal is input; A digital filter comprising: an adder that adds the output and the feedback signal.