JPH0228722A - Data processor - Google Patents

Abstract

PURPOSE:To detect prohibition addressing mode designation with a small quantity by comparing prohibition and addressing mode information which respectively decode and output the mode designation fields of operation and addressing. CONSTITUTION:A prohibition addressing mode bit pattern 30 is outputted from a programmable logic array for instruction decoding (PLA)20. The present or absent signal for addressing mode designation 34 is inputted from PLA16 and the six bit signal of use addressing mode information from addressing PLA17 to a logic circuit 19 and an addressing mode bit pattern 28 is outputted. When the patterns 28 and 30 are inputted to a prohibition addressing mode detection part 21, prohibition addressing mode designation are compared. The output is inputted to an exception processing part 23, and the designation of a prohibition addressing mode is treated as a contract instruction exception. When the exception is detected, a flag 32 showing the effect and a number 33 showing a type are transmitted to an operand fetch stage as parameter codes R11.

Description

[Detailed description of the invention]

[Field of Industrial Application] The present invention relates to a data processing device that processes an operand instruction, which has an operation specification field that specifies the operation of the instruction, and an operand specification field that allows operand specification using a general-purpose addressing mode. be. [Prior Art] In a data processing device having an orthogonalized instruction set, it is possible to use any addressing mode for each operand of any instruction. However, in reality, there is an inappropriate addressing mode specification for each operand of each instruction. As the instruction set becomes more complex, the number of prohibited combinations tends to increase. Conventionally, this type of data processing device has been published in the literature, for example 8
6th edition of National Sem1 conduct
or c. rp 5eries 32000 Data book
In particular, the series number N532032 has five types of access classes (as shown in Figure 22).
WRITE to RE8:,RMW・,ADDR・,REG
ADDR, etc.) and define each addressing mode (register mote, relative register mote, memory relative mode 1 immediate mode, absolute mote, external mote, top of stack mote, memory space mode, scale) for the operand in each access class. (e.g. index, index, etc.). Of these addressing modes, there are three types of addressing modes (register mode, immediate value mode,
top of stack moto) is affected by the address class of the operand. Below are five types of access classes (READ:, WRIT
ERMW: ADDR+, REGADDR: etc.) and the interpretation of the above three types of addressing mode in each addressing mode will be explained. (READ:) This addressing mode is interpreted as an operand that is either read or not written. When register mode is used, the specified register stores the operand. Also, if immediate value mode is used, it is legal only for operands of this access class. Additionally, if a top-of-stack mote is used, the stack pointer is incremented by a number of bytes corresponding to the length of the operand, or post-incremented, thereby ``popping'' the operand from the stack. (WRITE:) This addressing mode is interpreted as an operand that is written but not read. When register mode is used, the specified register receives and receives the operand. Also, if an immediate value mote is used, it becomes undefined for this access class. In addition, if you use the top stack mode, the stack pointer is decremented by the number of bytes corresponding to the length of the operand, thus pushing the operand onto the stack. The addressing mode is interpreted as an operand that is read, modified, and written to the same location. Also, if a register mote is used, the specified register stores the operand. Immediate motes use this access class. is undefined. Additionally, when using top-of-stack mode, the stack pointer gives the address of its operand, but is unchanged. , or as an effective address calculation that does not correspond to the operand being fetched as data. When using register mode, the operand is in memory and stores the specified register or its address. Immediate mode uses this access class When top-of-stack mode is specified, the stack pointer gives the address of its operand, but is unchanged. If register mode is used, the data item is held in the specified register. Immediate mode is also unspecified for this access class. Additionally, the top of If stack mode is used, the stack pointer gives the address of the operand, but is not changed.If an immediate mote is used for an operand with an access class other than READ, the prohibited mote is specified. However, in this type of data processing device, in order to guarantee more accurate operation, exception detection is not performed even though it returns an undefined value. Exception detection is required.Actually, as a process to detect this prohibited addressing mode, the instruction code, including the operand specification field, is transferred to the PLA for instruction decoding.
, and a prohibited combination was detected. However, both the operation specification field and the operand specification field should be input as information to a programmable logic array (PLA) for instruction decoding to detect whether a valid addressing mode is used for each operand of each instruction. Then, P.A.
Since the number of input bits of L increases and it is necessary to check combinations in detail, the number of product terms of the PAL increases and the size of the PAL used for instruction decoding becomes extremely large. The present invention was made to solve the above-mentioned problems, and includes separately decoding an operation specification field and an addressing mode specification field, and obtaining information about prohibited addressing modes output from a decoder that decodes the operation specification field. To provide an inexpensive data processing device capable of detecting prohibited addressing mode designation with a small capacity by comparing information of a used addressing mode outputted from a decoder that decodes an addressing mode designation field. [Means for Solving the Problems] A data processing device according to the present invention includes a first field information input means for inputting a value of an operation designation field, and an operation designation field input from the first field information input means. a first output means for analyzing the value of and outputting a prohibited address request for the operand specified by the operation specification field; and a second field information input means for inputting the value of the operand specification field. a second output means that analyzes the value of the operand specification field inputted from the second field information input means and outputs designated addressing mode information; and an operand outputted from the first or second output means. Detection means for detecting an abnormality in a designated addressing mode based on the value of the designated field and the value of the operation designation filter is provided. [Operation] In this invention, the value of the operation designation field or the value of the operand designation field input from the first field information input means and the second field information input means is outputted from the first or second output means. When the value of the operand specification field and the value of the operation specification field are output, the detection means detects whether the specified addressing mode is abnormal based on the value of the operand specification field and the value of the operation specification field. [Embodiment] FIG. 1 is a block diagram illustrating a pipeline processing mechanism in a data processing device showing an embodiment of the present invention. Reference numeral 1 denotes an instruction fetch stage (IF stage), which performs prefetching of instructions. Outputs code 8. 2 is a decode stage (D stage), which decodes the first stage instruction, that is, instruction code 8, and decodes D code 9 and A
Output Nido 10. 3 is the operand address calculation stage (A stage),
Second-stage instruction decoding and operand address calculation are performed from the output D code 9 and A code, and R code 11 and F code 12 are output. Reference numeral 4 denotes an operand fetch stage (F stage), which is composed of an R stage 6 that performs micro ROM access, and an operand fetch stage (OF stage) 7 that performs a pre-fetch of operands. 5 is an E stage, which executes a predetermined instruction from the E nid 13 and S code 14 output from the overrant fetch stage 4. Note that in this embodiment, pipeline processing is executed using a five-stage configuration, so the E stage 5 has a one-stage store buffer, and some of the high-performance instructions are configured so that the instruction execution itself is pipelined. , there is actually a pipeline processing effect of five or more stages. Further, the codes output from each stage will be explained below. The information passed from IF stage 1 to D stage 2 is instruction code 8 itself. The information passed from the D stage 2 to the A stage 3 is a D code 9 related to the operation specified by the instruction, and an A code 9 related to address calculation of the operand. Further, the information passed from the A stage 3 to the F stage 4 is an R coat 11 including the entry address of the microprogram routine, parameters to the microprogram, etc.
The F code 12 includes the operand address and access method instruction information. Furthermore, the information passed from the F stage 4 to the E stage 5 includes an E code 13 including arithmetic control information and literals, etc.
S code 14 including operands, operand addresses, etc.
There are two. Note that the value of the operation designation field (instruction code 8
) or the value of the operand specification field output from the first or second output means (D stage 2) according to the value of the operand specification field (consisted of a part of instruction code 8). When the value of the operation designation field (D code 9) is output, the A stage 3 having a detection means described later determines whether the specified addressing mode is abnormal based on the value of the operand designation field and the value of the operation designation field. The system is configured to detect whether the exception occurs and to perform predetermined exception handling. Also, each stage operates independently of the other stages, and in theory the five stages operate completely independently. Each stage can perform one process in a minimum of two clocks. Therefore, ideally, pipeline processing progresses one after another every two clocks. Furthermore, in inter-memory operations, memory indirect addressing, etc., there are instructions that cannot be processed with just one basic pipeline process, but for instructions with multiple memory operands, processing is performed based on the number of memory operands. At the decoding stage, pipeline processing is performed by breaking down into multiple pipeline processing units (step codes). Regarding the decomposition method of pipeline processing units, please refer to Japanese Patent Application No. 612.
Since it is described in detail in No. 36456, the details will be omitted, but the pipeline processing unit will be explained below. The pipeline processing unit in this embodiment is determined using the format characteristics of the instruction set. That is, the instruction is a variable-length instruction in 2-byte units, and is basically configured by repeating (2-byte instruction basic part + 0 to 4-byte addressing extension part) one to three times. The instruction basic part often has an opcode part and an addressing mode specification part, and when index addressing or memory indirect addressing is required, instead of the addressing extension part (a 2-byte multi-stage indirect mode specification part 0 to 4 bytes) Addressing extension part) is added in any number. Also, depending on the instruction, a 2 or 4-byte instruction-specific extension section is added at the end. The basic instruction part includes opcodes, basic addressing modes, literals, etc. Additionally, the addressing extensions include displacement, absolute address, and immediate value 1.
Any displacement of a branch instruction. Instruction-specific extensions include immediate value specification for register map I-format instructions. Note that in D stage 2, (2-byte instruction basic part 0
~4-byte addressing extension). (Multi-stage indirect mote specification part addressing extension part) or an instruction-specific extension part is processed as one decoding unit. The decoding result of each time is called a step code, and from A stage 3 onwards, this step code is used as a unit of vibe line processing. There is one operand for which a general addressing mode can be specified for one step code. The number of step codes is unique for each instruction, and when multi-stage indirect mode is not specified, one instruction is divided into a minimum of 1 step code and a maximum of 3 step codes. If multiple indirect motes are specified, the number of step coats will increase accordingly. Next, the addressing mode in this embodiment will be explained with reference to FIGS. 2 to 15. [Basic Addressing Mode] FIGS. 2 to 15 are schematic format diagrams illustrating addressing mode types and functions applied to the present invention. In these figures, Rn indicates the number of a general-purpose register, (sh) indicates how to specify the 6-bit abbreviated addressing mode, and (Ea) indicates how to specify the 8-bit general addressing mode. Note that the portion surrounded by dotted lines indicates an expanded portion. In the data processing device in this embodiment, the supported addressing modes are register direct mode,
A total of eight modes are defined: register indirect mode, register relative indirect mode, immediate value mode, absolute mode, program counter relative indirect mode (PC relative indirect mode), stack pop mode, and stack bush mode. Of these, in the register direct mode, as shown in FIG. 2, the contents of the register are used as operands. Further, in the register indirect mode, as shown in FIG. 3, the contents of the memory whose address is the contents of the register are used as the operands. Furthermore, the register relative indirect mode is classified into two types depending on whether the displacement value is 16 bits or 32 bits, as shown in Figure 4.
The operand is the contents of the memory whose address is the bit or the value added with the 32-bit displacement value. In addition, disp:1B or disp: in FIG.
32 indicates a 16-bit displacement value or a 32-bit displacement value, respectively. Furthermore, bit displacement values are treated as signed. In the immediate value mode, as shown in FIG. 5, the bit pattern specified in the instruction is treated as a binary number and used as an operand. Note that imm data in FIG. 5 indicates an immediate value. Furthermore, the size of the immediate value imm data is
Specified in the instruction as the operand size. In absolute mode, the address value is 16 as shown in Figure 6.
There are two types depending on whether it is indicated by bits or 32 hits. Then, the contents of the memory whose address is a 16-bit or 32-bit bit pattern specified in the instruction code are used as operands. abs・ in Figure 6
16 and abs:32 indicate 16-bit and 32-bit address values, respectively. Further, when an address is indicated by abs:16, the specified address value is sign-extended to 32 bits. As shown in Figure 7, there are two types of PC relative indirect mode depending on whether the displacement value is 16 bits or 32 bits, and the address is the sum of the contents of the program counter and the 16 bit or 32 bit displacement value. The operand is the contents of the memory. disp:16 and disp:32 in FIG. 7 indicate displacement values of 16 bits and 32 bits, respectively. Note that the displacement value is treated as signed. The value of the program counter referenced in PC relative indirect mode is the start address of the instruction containing the operand. In the multi-stage indirect addressing mode, when the value of the program counter is referenced, the address at the beginning of the instruction is similarly used as the PC-relative reference value. As shown in FIG. 8, the stack pop moat uses the contents of the memory whose address is the contents of the stack pointer (sp) as an operand. After operand access, the stack pointer (sp) is incremented by the operand size. For example, when handling 32-bit data, the stack pointer (sp) is updated by +4 after operand access. It is also possible to specify a stack pointer for operands of size B and H, each with a stack pointer (sp) of +1. Updated by +2. In addition, for operands that are stack popmots or have no meaning. Generates a reserved instruction exception. Specifically, reserved instruction exceptions include the WRITE operand and readmodify-
This is the stack mode specification for the write operand. As shown in FIG. 9, the stack bush moat uses as an operand the contents of a memory whose address is the contents obtained by decrementing the contents of the stack pointer (sp) by the operand size. In stack bush mode, the stack pointer (sp) is decremented before operand access. For example, when handling 32-bit data,
Stack pointer (sp) is 4 before operand access
updated. It is also possible to specify stack bush mode for operands of size B and H, and the stack pointer (sp) is updated by 1 and -2, respectively. In addition, a reserved instruction exception is generated for operands for which the stack command has no meaning. Specifically, the reserved instruction exceptions are the read operand and the read-mod i fy-wr i te.
This is a stack bush mode specification for the operand. "Multi-stage indirect addressing mode" Even complex addressing can basically be broken down into a combination of addition and indirect reference. Therefore, if addition and indirect reference operations are given as addressing primitives and can be combined arbitrarily, any complex addressing mode can be realized. Therefore, the multi-stage indirect addressing mode in this embodiment is an addressing mode based on this idea. Complex addressing modes are particularly useful for inter-module data references and AI language processing systems. When specifying the multi-stage indirect addressing mode, the basic addressing mode specification field specifies one of three types of specification methods: register-based multi-stage indirect mote, PC-based multi-stage indirect mote, and absolute-based multi-stage indirect mote. As shown in FIG. 10, the register-based multi-stage indirect mode is an addressing mode in which the value of a register is used as the base value for multi-stage indirect addressing to be expanded. In the PC-based multi-stage indirect mode, as shown in Fig. 11,
This is an addressing mode in which the value of the program counter is used as the base value for extended multi-stage indirect addressing. The absolute base multi-stage indirect mode is as shown in FIG.
This is an addressing mode that provides the best value for expanding multi-stage indirect addressing. As shown in FIG. 13, the multi-stage indirect mode designation field to be expanded has a unit of 16 bits, and this is repeated an arbitrary number of times. The one-stage multi-stage indirect motor performs displacement addition processing, index register scaling (xi, x2x4.x8) and addition processing, memory indirect reference processing, and the like. Note that when the value of E in each field is "0", it indicates that the multi-stage indirect mode is continued, and when the value of E is "1", it indicates that the address calculation has been completed, that is, the intermediate value tmp is used as the operand address. shall be. In addition, ■ "0" indicates that there is no memory indirect reference, and the value obtained by adding the displacement value (disp) to the intermediate value tmp, and further adding the value obtained by multiplying the index value Rx by the scale value 5cale is added to the new value. It is defined as an intermediate value tmp. In addition, if ■ is "1", it indicates that there is memory indirect reference, and the displacement value (disp) is set to the intermediate value tmp.
and further add the scale value 5ca to the index value Rx.
The content of the address indicated by the value obtained by adding the value multiplied by le is defined as the intermediate value tmp. Furthermore, when M is "0", it indicates that the index is not used, when M is "1", it is treated as a special index, and when the index value Rx is "0", it indicates that the index value is not used. If no addition is performed and the index value Rx is "1", use the program counter as the index value (Rx-PC), and if the index value Rx is "2~", retain the index value. . If D is "0", the value of the 4-bit field d4 in the multi-stage indirect mode is multiplied by 4 to obtain a displacement value, and this is added. Note that the value of field d4 is treated as signed, and is always multiplied by 4 and used regardless of the size of the operand. Furthermore, in the case of D or "1", the value dispx (16/32 bits) specified in the extended part of the multi-stage indirect mode
Let be the displacement value and add this. The size of the extension part is d4 field, and this is added. Note that the size of the extension part is defined by the value of the d4 field. For example, in the case of rQQOl, the value dispx is processed as 16 bits, and the value of the d4 field is r0010.
In this case, the value dispx is treated as a 32-bit value. Also, xx is the index scale (seal e
= 1/2/4/8). Therefore, ×2×4. X8
When scaling is performed, an indefinite value is entered as the intermediate value t, mp after the processing of that stage is completed. Although the execution address obtained by this multi-stage indirect mote is an unpredictable value, no exception occurs. Do not specify scaling for the program counter. 14 and 15 show the instruction format variations using the multi-stage indirect mode, the variations of whether the multi-stage indirect mode continues or ends are shown in FIG. 14, and the displacement size variations are shown in FIG. 15. shown. If a multi-stage indirect mode with an arbitrary number of stages can be used, there is no need for the compiler to differentiate between cases based on the number of stages, which has the advantage of reducing the burden on the compiler. Furthermore, even if the degree of desire for multi-stage indirect references is very low, the compiler must always be able to generate correct code. For this reason, any number of stages is possible in terms of format. Next, the prohibited addressing mode detection process according to the present invention will be explained with reference to FIGS. 16 to 18. FIG. 16 is a detailed circuit block diagram illustrating the configuration of the D stage 2 and A stage 3 shown in FIG. 1, and the same components as in FIG. 1 are given the same reference numerals. The configuration and operation will be explained below. The instruction code 8 output from the instruction decoder-in-latch 15 provided in the IF stage 1 has an operation specification field 24 and an operand specification field 25 separated from each other in the programmable logic array (PALAI) 16 for address decoding. It is individually decoded by the programmable logic array (PALA2) 17 for the mode. The output signal of the programmable logic array 16 for instruction decoding and the parameter 26 of the instruction code 8 are input to the random logic circuit 18, and the intermediate code 2 is input to the random logic circuit 18.
7. The extracted parameters 29 and the like are output. The intermediate code 27 and extracted parameters 29 are inputted to the programmable logic array 20 for instruction decoding, and the inhibited addressing mode pit pattern 30, microinstruction entry, etc. are outputted. Further, the programmable logic array 16 for instruction decoding outputs an Ea signal 4 indicating whether an addressing mode is specified in the instruction code. Programmable logic array 1 for addressing mode
From 7 onwards, it contains information on the addressing mode for officials.
For example, a 6-bit signal is output. This 6-bit signal and the Ea signal 34 are input to the random logic circuit 19. In the random logic circuit 19,
The Ea signal 34 is ANDed with each of the 6-bit signals and output as the used addressing mode bit pattern 28. After inputting the used addressing mode bit pattern 28 and the prohibited addressing mode bit pattern 30,
The prohibited addressing mode detection section 21 (detection means) checks whether the prohibited addressing mode is specified, and its output signal is input to the exception processing section 23. The designation of the prohibited addressing mode is treated as a reserved instruction exception, and when an exception is detected, the exception handling unit 23 sends an EIT flag 32 indicating that an exception has been detected, and an EIT number 33 indicating the type of exception detected. is sent to the F stage 4 as the above R code 11. Note that the programmable logic array 17 and random logic circuit 19 for addressing mode have an operand specification field 25.
By decoding , the bit corresponding to the addressing mode used to specify the operand is set to 1. FIG. 17 is a logic circuit diagram showing an example of the prohibited addressing mode detection section 21 shown in FIG.
0 is the mote signal, mote signal 35 corresponds to memory general mode (MEM), mode signal 36 corresponds to register direct mode (REG), mote signal 37 corresponds to immediate value mode (IMM), mote signal 38 corresponds to the stacked push mode (POP), the mote signal 39 corresponds to the stuck push mode (PUSH), and the mode signal 40 corresponds to the stuck push mode (PUSH).
corresponds to the multi-stage indirect addressing mode (ADDM), and these mode signals 35-40 constitute a 6-bit addressing mode bit pattern, which is input to AND gates (AND circuits) 47-52. Note that the mode signal 35 includes a register indirect mode as a general memory, a register relative indirect mode, an absolute mode, a PC relative indirect mode, etc., and the mode signal 40's multi-stage indirect addressing mode (ADDM) k: is a register-based multi-stage indirect mode. mote, PC-based multi-stage indirect mode,
Includes absolute base multistage drying, etc. 41 to 46 are prohibited addressing mode signals, and the prohibited addressing mode signal 41 is the memory general mode (ME
M), the inhibited addressing mode signal 42 corresponds to register direct mote (REG), the inhibited addressing mode signal 43 corresponds to immediate value mode (IMM),
The prohibited addressing mode signal 44 corresponds to the stack pop mode (POP), the prohibited addressing mode signal 45 corresponds to the stack button mode F (PUSH), and the prohibited addressing mode signal 46 corresponds to the multi-stage indirect addressing mode (ADDM). Correspondingly, the inhibit addressing mode signals 41-46 constitute a inhibit addressing mode bit button 30, and the inhibit addressing mode bit pattern 30 is transferred from the programmable logic array 20 for instruction decoding to the AND gate 47.
52, their AND output is output to the subsequent OR gate 53, an all-zero check is performed, and if an addressing mode prohibited by the prohibited addressing mode bit pattern 30 is used, an OR gate (OR gate 53) is output. The output of the circuit) 53 becomes "1", and processing related to a predetermined exception is performed. Note that the value of the operation designation field (operation designation field 24) input from the first field information input means and the second field information input means
Or, depending on the value of the operand specification filter (operand specification field 25), the value of the operand specification field output from the programmable logic array 17 serving as the first or second output means and the value of the operation specification field output from the programmable logic array 16. When this is output, the prohibited addressing mode detection unit 21 serving as a detection means detects whether the specified addressing mode is abnormal based on the value of the operand specification field and the value of the operation specification field. This is detected by logical operation with the prohibited addressing mode hit pattern 3o outputted from 20. Next, the prohibited addressing mode will be explained with reference to FIG. FIG. 18 is a relationship diagram illustrating prohibited addressing modes, where the vertical columns indicate classifications and the horizontal columns indicate motes. Note that in this embodiment, the use of operand specifications for each addressing mode is prohibited. It is classified into six types, which are independently designated as not prohibited. That is, there are six types in total, including general memory, register direct, immediate value, bush, pop, and multi-stage indirect modes. In this figure, × indicates an addressing mode that is prohibited for a specific access method, ○ indicates an addressing mode that is permitted for a specific access method, and * indicates a special access method. As can be seen from this figure, the memory general mode includes register indirect mode, register relative indirect mode, absolute mode, and PC relative indirect mode, and since all modes use the memory contents as operands,
It can be summarized as follows. In immediate mode, the operand is not accessed to memory or registers, but the bit pattern specified in the instruction code is treated as a binary number and used as an operand, and this does not exist in any mode other than immediate mode. . In boot mode, the stack pointer (sp)
It is distinguished from general memory because only access that involves reading (READ) the contents of Rikihachi memory is allowed, with the contents of memory as an address and the contents of memory as an operand. In pop mode, the operand is the contents of the memory whose address is the contents of the stack pointer (sp) decremented by the operand size, but it is distinguished from general memory because only accesses that involve writing to the memory are allowed. be done. Multi-stage indirect mode includes register-based multi-stage indirect mode, PC Bebe multi-stage indirect mode, and absolute-based multi-stage indirect mode, and uses the memory contents as an operand, but it is not possible to perform address calculation by referring to the memory contents. Therefore, it is distinguished from memory in general. There are 10 ways to prohibit independent addressing modes. For example, in the MOV instruction that transfers the contents of the source operand to the destination operand,
The source operand is the READ operand, and the 18th
As shown by classification number 1 in the figure, bush mode is prohibited. The destination operand of the MOV instruction is the WRITE operand, and as shown by classification number 2 in the figure, immediate value and pop modes are prohibited. Furthermore, the JMP (jump) instruction is an instruction that has a source operand indicating a jump destination address and jumps to that operand address. In this operand, the calculated address itself becomes the operand, and as shown by classification number 4 in the figure, register direct, bush, immediate, and pop-up are prohibited. Note that special instructions allow only specific addressing modes. Next, we will discuss the operation of the above embodiment using a data transfer instruction (MOV:S) in which the source operand is a register and the destination operand is a memory, and the text addressing mode check process will be described in the 19th section.
This will be explained with reference to FIGS. FIG. 19 is a schematic diagram illustrating the bit configuration of the data transfer instruction (MOV:S), where sh indicates the operand designation bit in the 6-bit abbreviated addressing mode, and R
n represents a designated bit that designates the operand number of the register, and WW represents a bit that represents the size of the operand of the designated bit sh. First, when the absolute mode is first used to specify the addressing mode of the destination operand, the following operation is performed. The bit allocation at this time is as shown in Fig. 20, abs: 16, ab
s: 32 corresponds to 16-bit and 32-bit address values. In IF stage 1, a data transfer instruction code in which the WRITE operand is designated as absolute mode is fetched. The fetched instruction code 8 is passed as is to the D Stella 2, and the operation designation field 24 and operand designation field 25 are separately decoded. Operation specification field 24 is input to programmable logic array 16 for instruction decoding. Operand specification field 25 is input to programmable logic array 17 for addressing mode. The output from the programmable logic array 16 for instruction decoding and the parameters 26 of the instruction code 8 are input to the random logic circuit 18, which outputs the intermediate code 27 cutting parameters 29 as a result. For the output signal of the programmable logic array 17 for the addressing mode, a flag of "1" is set in the MEM field for the absolute mode, and (MEM, REG, I
MM, POP, PUSHADDM) = (1,0,0,
0,0,0). Also, at this time, the Ea signal 34 is "1", and the output signal of the programmable logic array 17 for the addressing mode is used as is.
USH, ADDM) = (1, O, O, O, O, O). Further, the intermediate coat 27, the addressing moto pit pattern 28 used, and the cutout parameters 29 are passed to the A stage 3 as the D code 9. The intermediate code 27 and cutting parameters 29 passed to the A stage 3 are input to a programmable logic array 20 for instruction decoding. Since the destination operand is the WRITE operand, it corresponds to classification number 2 shown in FIG.
I, EAPATN2. EAPATN3. EAPATN4
．． EAPATN5) = (0,0,1,1,O,O
)) is generated. Furthermore, in the A stage 3, this prohibited addressing mode pit pattern 30 and mode signals 35 to 40, which are used addressing mode bit patterns passed from the D Stella 2, are input to the prohibited addressing mode detection section 21. In the prohibited addressing mode detection unit 21, the used addressing mode bit patterns (MEM, REG, IMM, POP, PUSH
, ADDM) = (1, Oo, o, o, o) and prohibited addressing mode bit pattern 301E8P8TN
O, EAPATNI, E to PATN2EAPATN3.
PATN4 to E. EAPATN5) = (0,0,1
, 1, 0, 0)) are logically ANDed and each is output. Therefore, the later OR gate 5
3 outputs "0", which is sent to the exception handling unit 23 to confirm that the addressing mode used is valid. On the other hand, when the immediate value mote is used as the addressing mode specification of the WRITE operand, the bit assignment is as shown in Figure 21, and in particular, the immd da
ta indicates an immediate value. Similar to the absolute mode, when a data transfer instruction code with the WRITE operand specified in immediate mode is fetched in IF stage 1, the fetched instruction code 8 is passed as is to D stage 2, and the operation specification field 24. Operand specification field 25 is decoded separately. The operation designation field 24 is input to the programmable logic array 16 for instruction decoding, and the operand designation field 25 is input to the programmable logic array 17 for addressing mode. At this time, the output from the programmable logic array 16 for instruction decoding and the parameters 26 of the instruction code 8 are input to the random logic circuit 18, and as a result, the intermediate code 27. The cutting parameter 29 is output. In the output signal of the programmable logic array 17 for addressing mode, a flag of "1" is set in the MEM field for absolute mode, and the addressing mode hit pattern used is (MEM REG IM
M POP PUSH, ADDM) −(0,
0, 1, Olo, 0). Also, at this time, the Ea signal 34 is "1", and the output signal of the programmable logic array 17 for addressing mode is used as is.
SH, ADDM) - (0, 0, 1, 0, 0, 0)). At this point, the intermediate coat 27, the addressing mode pattern 2B to be used, and the cutting pattern 29 are the D coat 9.
will be transferred to A stage 3. The intermediate code 27 and cutting parameters 29 passed to the A stage 3 are input to the programmable logic array 2o for instruction decoding. Then, similarly to the above example, the prohibited addressing mode bint pattern 30 (
(EAPATNO□E8PATN1.E to P8T2,
EAPATN3. 4. To EAP 8T. EAPATN5) =
(0,0,0,1,0,0)), that is, inhibited addressing mode signals 41 to 46 are generated. Furthermore, in the A stage 3, this prohibited addressing mode bit pattern 30 and the used addressing mode bit pattern 28 delivered from the D Stella 2 are input to the prohibited addressing mode detection section 21. Then, in the prohibited addressing mode detection unit 21, the AND circuits 47 to 52 detect the used addressing mode bit patterns (MEM, REG, IMM, POP, POP,
USH,, ADDM) = (o, o, 1, 1. O, O) and prohibited addressing mode bit pattern 30 ((E
APATNO,EAPATNIEAP8TN2. EAP
N3 to A. EAPATN4. EAPATN5) = (
0, 0, 0, 1゜0.0)) are respectively ANDed, and only the AND of the immediate value and EAPATN2 becomes "1", and the OR circuit 53 informs that the addressing mode used is invalid. The output is sent to the subsequent exception processing unit 23, the EIT flag 32 is set, and the exception number corresponding to the reserved instruction exception is set to the EIT number 33, and the output is sent to the F stage 4. In this way, the operation specification field 24 and the operand specification field 25 are decoded separately,
By comparing the information on the used addressing mode and the information on the prohibited addressing mode, it is possible to reliably detect the designation of the prohibited addressing mode. In the above embodiment, instruction decoding is executed in two stages, but it may be executed in one stage. Furthermore, in the above embodiment, the programmable logic array 4
Although the prohibited addressing mode information output from 7.20 and the specified addressing mode information are compared by taking a logical product, it is possible to perform detection through a programmable logic array or by using other random logic. It's okay. Furthermore, in the above embodiment, since the used addressing mode hit pattern 28 is also used for other purposes in the A stage 3, the Ea signal 34 and the addressing mode program logic 1 are used in the random logic circuit 19.
7 and the output signal is inputted to the prohibited addressing mode detection section 21. However, if only the prohibited addressing mode is to be detected, there is no need to perform the logical product with the Ea signal 34. It may be input to the prohibited addressing mode detection section 21 as is. [Effects of the Invention] As explained above, the present invention includes a first field information input means for inputting the value of the operation specification field, and a method for analyzing the value of the operation specification field input from the first field information input means. a first output means for outputting prohibited address information for the operand specified by the operation specification field; a second field information input means for inputting the value of the operand specification field; a second output means that analyzes the value of the operand specification field inputted from the information input means and outputs specified addressing mode information; and a value of the operand specification field outputted from the first or second output means. Since the present invention is provided with a detection means for detecting an abnormality in the addressing mode specified based on the value of the operation specification field, the number of bits of a logic circuit for decoding an instruction can be significantly reduced. Therefore, it is possible to reliably perform predetermined data processing while detecting the occurrence of sophisticated exception processing with an inexpensive circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a pipeline processing mechanism in a data processing device showing one embodiment of the present invention, and FIG.
Figures 1 to 15 are schematic format diagrams explaining addressing mode types and functions applicable to this invention.
6 is a detailed circuit block diagram illustrating the configuration of the D stage and A stage shown in FIG. 1, and FIG. 17 is a logic circuit diagram showing an example of the prohibited addressing mode detection circuit shown in FIG. Figure 18 is a relative relationship diagram explaining the prohibited addressing mode, Figures 19 to 21 are schematic diagrams explaining the configuration of bit assignments of data transfer commands, and Figure 22 is a diagram of conventional atression mode types and access clusters. It is a correlation diagram explaining the relative relationship of. In the figure, 1 is IF stage, 2 is D stage, 3 is A stage, 4 is F stage, 5 is F Stella, 6 is R stage, 7 is OF stage, 8 is instruction code, 9 is D code,
10 is A code, 11 is R code, 12 is F coat, 1
3 is the E code, and 14 is the S code. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others), Ward 1, Patent Application Showa B3-17!371, Name of the invention i6, Data processing device 3, Relationship with the person making the amendment Patent applicant address Tokyo 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Co., Ltd. Representative Moriya Shiki 4, Agent address: 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo Full text of the specification subject to amendment and drawings 6. Contents of amendment (1) The entire specification shall be amended as shown in the attached sheet. (2) In the drawings, Figures 13, 16, and 1 will be corrected as shown in the attached sheet. Operand specification is performed using the second output means for outputting the above specification, the first or second 1, the title of the invention data processing device 2, the operation specification field for specifying the operation of the claim instruction, and the general-purpose addressing mode. In a data processing device that processes an operand instruction having an operand specification field that can be performed, a first field information input means for inputting a value of the operation specification field; a first output means for analyzing the value of the operation specification field and outputting prohibited addressing mode information for the operand specified by the operation specification field; and a first output means for inputting the value of the operand specification field. 2 field information input means, and the value of the operand specification field inputted from the second field information input means is analyzed to obtain specified addressing mode information, and malfunction of the specified addressing mode is detected. What is claimed is: 1. A pig processing device comprising a detection means for detecting. 3. Detailed Description of the Invention [Field of Industrial Application] This invention processes an operand instruction that has an operation specification field that specifies the operation of the instruction, and an operand specification field that allows operand specification using a general-purpose addressing mode. The present invention relates to a data processing device. (Prior Art) In a data processing device having an orthogonalized instruction set, it is possible to use any addressing mode for each operand of any instruction. However, in reality, there are inappropriate addressing mode specifications for each operand of each instruction. As the instruction set becomes more complex, the number of prohibited combinations tends to increase. Conventionally, this type of data processing device has been disclosed in the literature, for example, 8
6th edition of National Sem1 conduct
or c. rp 5eries 32000 Data book
In particular, the series number N532032 has five types of access classes (
READWRITE:, RMW:, ADDR:, REG
8D to R: etc.), and define each addressing mode (register mode, register mode, etc.) for the operand in each access class.
It defines the interpretation of relative register mode, memory relative mode, immediate mode, absolute child mode, external mode, top of stack mode, memory space mode, scaled index, etc.). Of these addressing modes, three types of addressing modes (register mode, immediate value mode, and top of stack mode) are affected by the address class of the operand. Below, there are five types of access classes (READ, WRIT).
ERMW:, ADDR: REG8D to R:, etc.) and the interpretation of the above three types of addressing mode in each addressing mode will be explained. (READ:) This addressing mode is interpreted as an operand that is read but not written. If register mode is used, the operand is read from the specified register. Also, if immediate value mode is used, it is legal only for operands of this access class. Additionally, when using top-of-stack mode, the stack pointer is post-incremented by a number of bytes corresponding to the length of the operand, thereby ``popping'' the operand from the stack. (WRITE:) This addressing mode is interpreted as an operand that is written but not read. When register mode is used, the specified register receives its operand. Also, if an immediate value mote is used, it becomes undefined for this access class. In addition, when using top-of-stack mode, the stack pointer is decremented by a number of bytes corresponding to the length of the operand, thus ``butching'' the operand onto the stack. (BMW) This addressing The mode is interpreted as an operand that is read, modified, and written to the same location. When register mode is used, the specified register stores the operand. Immediate mode is unspecified for this access class. Additionally, when using top-of-stack mode, the stack pointer gives the address of its operand but is not changed. (ADDR:) This addressing mode is interpreted as an effective address calculation that does not correspond to an operand that cannot be held in a register, or an operand that is being fetched as data. When using register mode, the operand is in memory and the specified register stores its address. Immediate mode is unspecified for this access class. When you specify top-of-stack mode, the stack pointer gives the address of its operand, but is not modified. <REGADDR:) This addressing mode is interpreted to specify a base for placing or aligning data items of non-standard size. When using register mode, data items are held in specified registers. Also, the immediate mode is undefined for this access class. Additionally, when using top-of-stack mode, the stack pointer gives the address of its operand but is not changed. In this way, when the immediate value mode is used for an operand whose access class is other than READ, even if the prohibited mode is specified, only an undefined value is returned and no exception detection is performed. [Problems to be Solved by the Invention] Therefore, in this type of data processing device, exception detection for the prohibited addressing mode is required in order to guarantee more accurate operation. In fact, as a process to detect this prohibited addressing mode, the instruction code including the operand specification field is transferred to the PLA for instruction decoding.
One possible method is to input the information into the following information and detect prohibited combinations. However, both the operation specification field and the operand specification field should be input as information to a programmable logic array (PLA) for instruction decoding to detect whether a valid addressing mode is used for each operand of each instruction. Then, P.A.
Since the number of input bits of L increases and it is necessary to check combinations in detail, the number of product terms of the PAL increases and the size of the PAL used for instruction decoding becomes extremely large. The present invention was made to solve the above-mentioned problems, and includes separately decoding an operation specification field and an addressing mode specification field, and obtaining information about prohibited addressing modes output from a decoder that decodes the operation specification field. The purpose of the present invention is to obtain an inexpensive data processing device capable of detecting prohibited addressing mode designation with a small capacity by comparing information on the used addressing mode outputted from a decoder that decodes an addressing mode designation field. [Means for Solving the Problems] A data processing device according to the present invention includes a first field information input means for inputting a value of an operation designation field, and an operation designation field input from the first field information input means. The first one parses the value of and outputs prohibited addressing mode information for the operand specified by the operation specification field.
a second field information input means for inputting the value of the operand specification field; and a second field information input means for inputting the value of the operand specification field, and analyzing the value of the operand specification field input from the second field information input means to obtain specified addressing mode information. A second output means for outputting the output, and a detection means for detecting invalidity of the specified addressing mode based on the prohibited addressing mode information and the specified addressing mode information output from the first or second output means. It is. [Operation] In this invention, prohibited addressing is performed from the first or second output means based on the value of the operation designation field and the value of the operand designation field input from the first field information input means and the second field information input means. When the mode information and designated addressing mode information are output, it is detected whether the designated addressing mode is invalid based on the prohibited addressing mode information and the designated addressing mode information. (Embodiment) FIG. 1 is a block diagram illustrating a pipeline processing mechanism in a data processing device showing an embodiment of the present invention. Reference numeral 1 denotes an instruction fetch stage (IF stage), which performs prefetching of instructions and Outputs code 8. 2 is a decode stellar (D stage) which decodes the first stage instruction, that is, instruction code 8, and outputs D code 9 and A code 10. 3 is the operand address calculation stage (A Stella),
Second-stage instruction decoding and operand address calculation are performed from the output D code 9 and A code 10, and R code 11 and F code 12 are output. 4 is the operand fetch stage (F stage), which is a micro ROM
It consists of an R stage 6 that performs access, and an OF stage 7 that performs operand brief fetching. 5 is an E stage, which executes a predetermined instruction from the E code 13 and S code 14 output from the operand fetch stage 4. In this embodiment, a five-stage configuration is used as the basis of pipeline processing. E stage 5 has a one-stage store buffer, and some of the high-performance instructions pipeline the instruction execution itself, so there is actually a pipeline processing effect of five or more stages. Further, the coats output from each stage will be explained below. The information passed from 1F stage 1 to D stage 2 is instruction code 8 itself. The information passed from the D stage 2 to the A stage 3 is a D code 9 related to the operation specified by the instruction, and an A code 10 related to address calculation of the operand. Further, the information passed from the A stage 3 to the F stage 4 includes an R code 11 including the entry address of the microprogram routine, parameters to the microprogram, etc.
There are two types: an operand address and an F code 12 containing access method instruction information and the like. Furthermore, the information passed from the F stage 4 to the E stage 5 includes an E code 13 including arithmetic control information and literals, etc.
S code 14 including operands, operand addresses, etc.
There are two. Note that the value of the operation designation field (instruction code 8
The first and second output means (D stage 2 and A stage 3
When the information on the prohibited addressing mode and the information on the specified addressing mode are output from the (a part of the The system is configured to detect whether the addressing mode specified by the address is invalid and to execute predetermined exception handling. Also, each stage operates independently of the other stages, and in theory five stages can operate completely independently. Each stage can perform one process in a minimum of two clocks. Therefore, ideally, pipeline processing progresses one after another every two clocks. Furthermore, in inter-memory operations, memory indirect addressing, etc., there are instructions that cannot be processed with just one basic pipeline process, but for instructions with multiple memory operands, processing is performed based on the number of memory operands. At the decoding stage, pipeline processing is performed by breaking down into multiple pipeline processing units (step codes). Regarding the decomposition method of pipeline processing units, please refer to Japanese Patent Application No. 612.
Since it is described in detail in No. 36456, the details will be omitted, but the pipeline processing unit will be explained below. The pipeline processing unit in this embodiment is determined using the format characteristics of the instruction set. In other words, an instruction is a variable-length instruction in 2-byte units, and is basically constructed by repeating (2-byte instruction basic part, 0 to 4-byte addressing extension part) 1 to 3 times. . The instruction basic part often has an opcode part and an addressing mode specification part, and when index addressing or memory indirect addressing is required, instead of the addressing extension part (a 2-byte multi-stage indirect mode specification part 0 to 4 bytes) Addressing extension part) is added in any number. Also, depending on the instruction, a 2 or 4-byte instruction-specific extension section is added at the end. The basic instruction part includes opcodes, basic addressing modes, literals, etc. Additionally, the addressing extensions include displacement, absolute address, and immediate value 1.
Any displacement of a branch instruction. Register maps for instruction-specific extensions. There are immediate value specifications for I-format commands, etc. In addition, in D stage 2, (2 bytes of basic instruction part + 0
~4-byte addressing extension). (Multi-stage indirection code specifying section + addressing extension section) or an instruction-specific extension section is processed as one decoding unit. The decoding result of each time is called a step code, and from the A stage 3 onwards, this step code is used as the unit of pipeline processing. There is one operand for which a general addressing mode can be specified for one step code. The number of step codes is unique for each instruction, and when multi-stage indirect mode is not specified, one instruction is divided into a minimum of 1 step code and a maximum of 3 step codes. If multiple indirect mode is specified, the number of step coats increases accordingly. Next, the addressing mode in this embodiment will be explained with reference to FIGS. 2 to 15. "Basic Addressing Mode" FIGS. 2 to 15 are format diagrams for explaining addressing mode types and functions applied to the present invention. In these figures, Rn indicates the number of the general-purpose register, (sh) indicates the method of specifying the 6-bit abbreviated addressing mode, and (Ea) indicates the method of specifying the 8-bit general addressing mode. Note that the portion surrounded by dotted lines indicates an expanded portion. In the data processing device in this embodiment, the supported addressing modes are register direct mode,
A total of eight modes are defined: register indirect mode, register relative indirect mode, immediate value mode, absolute mode, program counter relative indirect mode (PCC relative indirect mode, stack pop mode, stack bush mode, etc.).Register direct mode is , as shown in Figure 2, the contents of the register are used as the operands.In the register indirect mode, as shown in Figure 3, the contents of the memory whose address is the contents of the register are used as the operands.Register relative indirect mode is 2 depending on whether the displacement value is 16 bits or 32 bits, as shown in Figure 4.
There are different types. The contents of the memory whose address is the value obtained by adding a 16-bit or 32-bit displacement value to the contents of each register are used as operands. In addition, the fourth
Disp16 and disp・32 in the diagram are each 16
A bit displacement value and a 32-bit displacement value are shown. Note that the displacement value is treated as signed. As shown in FIG. 5, the immediate value mote regards the bit pattern specified in the instruction as it is as a binary number and uses it as an operand. Note that imm data in FIG. 5 indicates an immediate value. Furthermore, the size of the immediate value imm data is
Specified in the instruction as the operand size. In absolute mode, the address value is 16 as shown in Figure 6.
There are two types depending on whether it is indicated by bits or 32 bits. Then, the contents of the memory whose address is a 16-bit or 32-bit bit pattern specified in the instruction code are used as operands. abs in Figure 6:
16 and abs.32 indicate 16-bit and 32-bit address values, respectively. Further, when an address is indicated by abs:16, the specified address value is sign-extended to 32 bits. As shown in Figure 7, there are two types of PC relative indirect modes depending on whether the displacement value is 16 bits or 32 bits, and the address is the sum of the contents of the program counter and the 16 bit or 32 bit displacement value. The operand is the contents of the memory. disp:1B and disp:32 in FIG. 7 indicate displacement values of 16 bits and 32 bits, respectively. Note that the displacement value is treated as signed. The value of the program counter referenced in PC relative indirect mode is the start address of the instruction that includes the operand. In the multi-stage indirect addressing mode, when the value of the program counter is referenced, the address at the beginning of the instruction is similarly used as the PC-relative reference value. In the stack pop mode, as shown in FIG. 8, the contents of the memory whose address is the contents of the stack pointer (sp) are used as operands. After accessing the operand, the stack pointer (sp) is incremented by the operand size. For example, when handling 32-bit data, the stack pointer (sp) is updated by +4 after operand access. It is also possible to specify stack pop mode for operands of size B and H, each with a stack pointer (sp) of +1. Updated by +2. In addition, for those where the stack pop moat has no meaning for the operand. Generates a reserved instruction exception. Specifically, reserved instruction exceptions include the WRITE operand and readmodify-
This is the stack mode specification for the write operand. As shown in FIG. 9, the stack bush moat uses as an operand the contents of the memory whose address is the contents obtained by decrementing the contents of the stack pointer (sp) by the operand size. In stack bush mode, the stack pointer (sp) is decremented before operand access. For example, when handling 32-bit data,
Stack pointer (sp) is 4 before operand access
will be updated only. It is also possible to specify stack bush mode for operands of size B and H, and the stack pointer (sp) is updated by 1 and -2, respectively. Furthermore, a reserved instruction exception is generated for operands for which the stacked bush mode has no meaning. Specifically, the reserved instruction exception is the stack bush mode specification for the read operand and read-modify-write operand. "Multi-stage indirect addressing mode" Even complex addressing can basically be broken down into a combination of addition and indirect reference. Therefore, if addition and indirect reference operations are given as addressing primitives and can be combined arbitrarily, any complex addressing mode can be realized. Therefore, the multi-stage indirect addressing mode in this embodiment is an addressing mode based on this idea. Complex addressing modes are particularly useful for inter-module data references and AI language processing systems. When specifying the multi-stage indirect addressing mode, the basic addressing mode specification field specifies one of three types of specification methods: register-based multi-stage indirect mode, PC-based multi-stage indirect mode, and absolute-based multi-stage indirect mode. As shown in FIG. 10, the register-based multi-stage indirect mode is an addressing mode in which a register value is used as a base value for multi-stage indirect addressing to be expanded. The PC Hose multi-stage indirect mode is as shown in FIG.
This is an addressing mode in which the value of the program counter is used as the base value for extended multi-stage indirect addressing. The absolute base multi-stage indirect mode is as shown in FIG.
This is an addressing mode that is used as the base value for expanded multi-stage indirect addressing. As shown in FIG. 13, the multi-stage indirect mode designation field to be expanded has a unit of 16 bits, and this is repeated an arbitrary number of times. The one-stage multi-stage indirection performs displacement addition processing, index register scaling (xl, x2x4.x8) and addition processing, memory indirect reference processing, and the like. The meaning of each field in FIG. 13 will be explained below. When the value of E is "0", it indicates that the multi-stage indirect mode is continued, and when the value of E is "IJ", it indicates that the address calculation has been completed, that is, the intermediate value tmp is used as the operand address. If is "0", it indicates that there is no memory indirect reference, and the total value of adding the displacement value (disp) to the intermediate value tmp and further multiplying the index value Rx by the scale value 5cale is used as the new intermediate value. It is defined as tmp. In addition, if ■ is "1", it indicates that there is memory indirect reference, and the displacement value (diSp) is set to the intermediate value tmp.
and further add the scale value 5ca to the index value Rx.
The content of the memory whose address is the sum of the value multiplied by le is defined as an intermediate value tmp. If M is “0”, the contents of the register indicated by Rx (
Rx ) as an index. When M is "1", it is treated as a special index, when (Rx) is "0", the index value is not added, and when (Rx) is "1", Use the program counter as an index value Rx=
PC), (Rx) is r2~'' is not defined in this embodiment. When D is "0", the value of the 4-bit field d4 in the multi-stage indirect mode is multiplied by 4 to obtain a displacement value, and this is added. Note that the value of field d4 is treated as signed, and is always multiplied by 4 and used regardless of the size of the operand. When D is "1", the value dispx (16/32 bits) specified in the extended section of the multi-stage indirect mode is set as a displacement value, and this is added. Note that the size of the extension part is defined by the value of the d4 field, d4-rooo
l, the value dispx is treated as 16 bits, and d4·'0010. In this case, the value crispx is treated as 32 bits. Xx is the index scale (scale=1/2
/4/B). x2 for program counter. x4. When scaling by X8 is performed, an undefined value is entered as the intermediate value tmp after the processing of that stage is completed. The execution address obtained by this multi-stage indirect mode is an unpredictable value, but
No exception occurs. Do not specify scaling for the program counter. Instruction format variations due to the multi-stage indirect mode are shown in FIGS. 14 and 15, variations on whether the multi-stage indirect mode continues or ends are shown in FIG. 14, and variations in displacement size are shown in FIG. 15. It will be done. If a multi-stage indirect mode with an arbitrary number of stages can be used, there is no need for the compiler to differentiate between cases based on the number of stages, which has the advantage of reducing the burden on the compiler. Furthermore, even if the frequency of multiple indirect references is very low, the compiler must always generate the correct code. For this reason, any number of stages is possible in terms of format. Next, the prohibited addressing mode detection process according to the present invention will be explained with reference to FIGS. 16 to 18. FIG. 16 is a detailed circuit diagram explaining the configuration of the D stage 2 and A stage 3 shown in FIG.
Components that are the same as those in the figures are given the same reference numerals. The configuration and operation will be explained below. The instruction code 8 output from the instruction decoder-in-latch 15 provided in the 1F stage 1 has an operation designation field 24 and an operand designation field 25 separately, and is transferred to a programmable logic array (P LA 1 ) 16 for instruction decoding. , are individually decoded by the programmable logic array (PLA2)+7 for addressing mode. The output signal of the programmable logic array 16 for instruction decoding and the parameter 26 of the instruction code 8 are input to the random logic circuit 18, and the intermediate code 2 is input to the random logic circuit 18.
7. The extracted parameters 29 and the like are output. The intermediate code 27 and extracted parameters 29 are inputted to a programmable logic array 20 for instruction decoding, and outputs a prohibited addressing mode pit pattern 30, a microinstruction entry address, and the like. Further, the programmable logic array 16 for instruction decoding outputs an Ea signal 34 indicating whether or not an addressing mode is specified in the instruction code. Programmable logic array 1 for addressing mode
From 7 onwards, 6 contains information on the addressing mode used.
A bit signal is output. This 6-bit signal and the Ea signal 34 are input to the random logic circuit 19. In the random logic circuit 19,
The Ea signal 34 is ANDed with each of the 6-bit signals and outputted as the used addressing mode hit pattern 2B. When the used addressing mode pit pattern 28 and the prohibited addressing mode bit pattern 30 are input, the prohibited addressing mode detection unit 21 (detection means)
A check is made to designate the prohibited addressing mode, and the output signal thereof is input to the exception processing section 23. The designation of the prohibited addressing mode is treated as a reserved instruction exception, and if an exception is detected, the exception handling unit 23 sends an EIT flag 32 indicating that an exception has been detected and an EIT number 33 indicating the type of exception detected. It is sent to F stage 4 as R code 11. Note that in the programmable logic array 17 and the random logic circuit 19 for addressing mode, the operand specification field 25 is
The bit corresponding to the addressing mode used to specify the operand is set to 1 by decoding. FIG. 17 is a logic circuit diagram showing an example of the prohibited attrending mote detection unit 21 shown in FIG.
0 is a mode signal, mote signal 35 corresponds to memory general mode (MEM), moto signal 36 corresponds to register direct mode (REG), and mode signal 37 corresponds to immediate mode (
IMM), mode signal 38 corresponds to stacked push mode (POP), mode signal 39 corresponds to stacked bush mode (PUSH), and moto signal 40 corresponds to multi-stage indirect addressing mode (ADDM). The mode signals 35-40 constitute a 6-bit addressing mode bit pattern, which is input to AND gates (AND circuits) 47-52. In addition,
In general, the memory of the mode signal 35 includes register indirect mode, register relative indirect mode, absolute moto, PC relative indirect mode, etc., and the multi-stage indirect addressing mode (ADDM) of the mode signal 40 includes register-based multi-stage indirect mode, Includes PC-based multi-stage indirect mode, absolute-based multi-stage indirect mode, etc. 41 to 46 are prohibited addressing mode signals, and the prohibited addressing mode signal 41 is the memory general mode (ME
M), the inhibited addressing mode signal 42 corresponds to the register direct mode (REG), the inhibited addressing mode signal 43 corresponds to the immediate value mode (IMM),
A prohibited addressing mode signal 44 corresponds to a stacked push mode (POP), a prohibited addressing mode signal 45 corresponds to a stuck push mode (PUSH),
The prohibited addressing mode signal 46 corresponds to the multi-stage indirect addressing mode (ADDM), and the prohibited addressing mode signals 41 to 46 constitute a prohibited addressing mode bit pattern 30, and this prohibited addressing mode bit pattern 30 is used in programmable logic for instruction decoding. Array 20 to AND gate 47
52, their AND output is output to the subsequent OR gate 53, an all zero check is performed, and if an addressing mode prohibited by the prohibited addressing mode bit pattern 30 is used, an OR gate (OR gate) is output. The output of the circuit) 53 becomes "1", and processing related to a predetermined exception is performed. Note that the value of the operation designation field (operation designation field 24) input from the first field information input means and the second field information input means
Or a programmable logic array 16 that becomes the first output means depending on the value of the operand specification field (operand specification field 25).Random logic circuit 18.
The prohibited addressing mode information output from the programmable logic array 20 and the designation (
Use) Based on the addressing mode information, the prohibited addressing mode detecting section 21 serving as a detecting means detects by logical operation. Next, the prohibited addressing mode will be explained with reference to FIG. FIG. 18 is a correlation diagram illustrating prohibited addressing modes, where vertical columns indicate classifications and horizontal columns indicate modes. In addition,
In this embodiment, use of operand specifications for each addressing mode is prohibited. It is classified into six types, which are independently designated as not prohibited. That is, there are six types in total, including general memory, register direct, immediate value, bush, and pop multistage indirect modes. In this figure, × indicates an addressing mode that is prohibited for a specific access method, ○ indicates an addressing mode that is permitted for a specific access method, and * indicates a special access method. The memory general mode includes a register indirect mode, a register relative indirect mode, and an absolute mode PC relative indirect mode, all of which are combined into one mode because they use the contents of the memory as an operand. In immediate mode, the operand is not accessed to memory or registers, but the bit pattern specified in the instruction code is treated as a binary number and used as an operand, and this only exists in immediate mode. . In Bushmot, the stack pointer (sp)
The operand is the contents of the memory whose address is the contents of the memory, but it is distinguished from general memory because only access that involves reading (READ) the contents of the memory is permitted. In pop mode, the operand is the contents of the memory whose address is the contents of the stack pointer (sp) decremented by the operand size, but it is distinguished from general memory because only accesses that involve writing to the memory are allowed. be done. The multi-stage indirect modes include register-based multi-stage indirect mode, PC Bebe multi-stage indirect mode, and absolute-based multi-stage indirect mode, and the memory contents are used as operands, but addresses can be calculated by referring to the memory contents. Therefore, it is distinguished from memory in general. There are 10 ways to prohibit independent addressing modes. For example, in the MOV instruction that transfers the contents of the source operand to the destination operand, the source operand is the READ operand, as shown by classification number 1 in Figure 18. Bushmot is prohibited. Further, the destination operand of the MOV instruction is the WRITE operand, and as shown by classification number 2 in the figure, immediate values and popmots are prohibited. The JMP (jump) instruction is an instruction that has a source operand indicating a jump destination address and jumps to that operand address. In this operand, the calculated address itself becomes the operand, and as shown by classification number 4 in the figure, register direct, bush, immediate, and pop-up are prohibited. Note that special instructions allow only specific addressing modes. Next, regarding the operation of the above embodiment, using a data transfer instruction (MOVS) in which the source operand is a register and the destination operand is a memory, as a specific example, the text addressing moto check process will be described in FIGS.
This will be explained with reference to FIG. FIG. 19 is a schematic diagram explaining the bit configuration of the data transfer instruction (MOV:S), where sh indicates the operand specification field in the 6-bit abbreviated addressing mode, and Rn indicates the specification specifying the operand number of the register. WW indicates a field indicating the size of the operand of the specified bit sh. First, when the absolute mode is first used to specify the addressing mode of the destination operand, the following operation is performed. The bit allocation at this time is as shown in FIG. 20, abs: 16. abs:
32 corresponds to 16-bit and 32-bit address values. A data transfer instruction code in which the WRITE operand specifies absolute mode is fetched into IF stage 1. The fetched instruction code 8 is passed as is to the D stage 2, and the operation designation field 24 and operand designation field 25 are decoded separately. Operation specification field 24 is input to programmable logic array 16 for instruction decoding. Operand specification field 25 is input to programmable logic array 17 for addressing mode. The output from the programmable logic array 16 for instruction decoding and the parameters 26 of the instruction code 8 are input to the random logic circuit 18, which outputs the intermediate code 27 cutting parameters 29 as a result. For the output signal of the programmable logic array 17 for the addressing mode, a flag of "1" is set in the MEM field for the absolute mode, and (MEM, REG, I
MM, POP, PUSHADDM) = (1, O, O,
0, O, O). Also, at this time, the Ea signal 34 is [IJ], and the output signal of the programmable 0-thick array 17 for the addressing mode is used as is.
H, ADDM) = (1, O, O, O, O, O). In addition, the intermediate code 27, the addressing motobit pattern 28 used, and the cutout parameter 29 are the D code 9.
It will be transferred to A stage 3. The intermediate code 27 and cutting parameters 29 passed to the A stage 3 are input to a programmable logic array 20 for instruction decoding. Since the destination operand is the WRITE operand, it corresponds to classification number 2 shown in FIG.
ATNI, PATN2, EAPATN3 to E. EAPATN4. EAPATN5) = (0,0,
1,1,O,O)) is generated. Furthermore, in the A stage 3, this prohibited addressing mode bit pattern 30 and the used addressing mode bit pattern 28 passed from the D stage 2 are input to the prohibited addressing mode detection section 21. In the prohibited addressing mode detection unit 21, AND gates 47 to 52 detect the used addressing mode bit patterns (MEM, REG, IMM, POP, PUSH
, ADDM) = (1, Oo, o, o, o) and prohibited addressing mode bit pattern 30 ((EAPAT
NO, EAPATNI, PATN2 to E. EAPATN3. EAPATN4. EAPATN5)
= (0, 0, 1, 1, 0, 0)) for each bit term, and "0" is output for each. Therefore, "0" is output from the OR gate 53 at the subsequent stage, and a message indicating that the used addressing mode is valid is sent to the exception processing unit 23. Next, when the immediate value mode is used as the addressing mode specification of the WRITE operand, the bit allocation will be as shown in FIG. immd clat in the diagram
a indicates an immediate value. Similar to the absolute mote, when a data transfer instruction code with the WRITE operand specified in the immediate mote is fetched in IF stage 1, the fetched instruction code 8 is passed as is to the D stage 2, and the operation specification field 24. Operand specification field 25 is decoded separately. The operation designation field 24 is input to the programmable logic array 16 for instruction decoding, and the operand designation field 25 is input to the programmable logic array 17 for addressing mode. At this time, the output from the programmable logic array 16 for instruction decoding and the parameter 26 of the instruction code 8 are input to the random logic circuit 18, and as a result, the intermediate node 2 and the cutout parameter 29 are output. In the output signal of the programmable logic array 17 for the addressing mode, a flag of "1" is set in the IMM field for the immediate mode, and the addressing mode bit pattern 28 used is (MEM, REG, IMM,
POP, PUSH, ADDM) = (0, 0, 1, 0,
0, O). Also, this time, Ea
Nobuko 734 is "1", and the output signal of the programmable logic array 17 for addressing mode is used as is. Addressing mode bit pattern 28 (M
EM, REG, IMM, POP, PUSH, ADDM
) = (0,0,1,O,O,O)). At this time, the intermediate coat 27, the used addressing mode pattern 28, and the cutting pattern 29 are D code 9.
will be transferred to A stage 3. The intermediate code 27 and cutting parameters 29 passed to the A stage 3 are input to a programmable logic array 20 for instruction decoding. Then, similarly to the above example, the prohibited addressing mode bit pattern 30 ((
EAPATNO, EAPATNI, EAPATN2, E
APATN3. EAPATN4. EAPATN5)=
(0,0,1,1,0,0)), that is, inhibited addressing mode signals 41 to 46 are generated. Furthermore, in the A stage 3, this prohibited addressing mode bit pattern 30 and the used addressing mode bit pattern 28 delivered from the D stage 2 are input to the prohibited addressing mode detection section 21. Then, in the prohibited addressing mode detection unit 21, the AND circuits 47 to 52 detect the used addressing mode bit pattern 28 (MEM, REG, IMM, PO
P, PUSH, ADDM) = (0, O, 0, 1, O, O
) and prohibited addressing mode bit pattern 30 (
(EAPATNO, EAPATNI. EAPATN2, EAPATN3, EAPATN
4, EAPATN5) = (0, 0, 1, 10, 0
)) is ANDed for each bit term with I
Only the logical product of MM and EAPATN2 is "1",
An output indicating that the addressing mode used is invalid is sent from the OR circuit 53 to the exception handling section 23 in the subsequent stage, and the EIT
The flag 32 is set, the exception number corresponding to the reserved instruction exception is set to the EIT number j3, and the EIT is sent to the F stage 4. In this way, the operation specification field 24 and the operand specification field 25 are decoded separately,
By comparing the information on the used addressing mode and the information on the prohibited addressing mode, it is possible to reliably detect the designation of the prohibited addressing mode. In the above embodiment, instruction decoding is executed in two stages, but it may be executed in one stage. Furthermore, in the above embodiment, the programmable logic array 1
The prohibited addressing mode information output from 7.20 and the designated addressing mode information are compared by performing a logical AND operation, or the detection is performed through a programmable logic array, or by other random logic. Also good. Furthermore, in the above embodiment, since the used addressing mode hit pattern 28 is also used for the purpose of the A stage 3, the Ea signal 34 and the output signal of the programmable logic array 17 for addressing mode are connected in the random logic circuit 19. The logical product is calculated and input to the prohibited addressing mode detection section 21, but if only the prohibited addressing mode is to be detected, there is no need to perform the logical product with the Ea signal 34, and the prohibited addressing mode detecting section 21 is inputted as is. You can also enter . [Effects of the Invention] As explained above, the present invention includes a first field information input means for inputting the value of the operation specification field, and a method for analyzing the value of the operation specification field input from the first field information input means. a first output means for outputting prohibited addressing mode information for the operand specified by the operation specification field; a second field information input means for inputting the value of the operand specification field; a second output means that analyzes the value of the operand specification field inputted from the field information input means and outputs designated addressing mode information; and prohibited addressing mode information outputted from the first or second output means. Since the present invention is provided with a detection means for detecting invalidity of the specified addressing mode based on the specified addressing mode information, the number of bits of the logic circuit for decoding instructions can be significantly reduced. Therefore, it has an excellent effect of being able to reliably execute predetermined pig processing while detecting the occurrence of sophisticated exception processing with an inexpensive circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a pipeline processing mechanism in a data processing device showing one embodiment of the present invention, and FIG.
Figures 1 to 15 are schematic format diagrams explaining addressing mode types and functions applied to this invention.
6 is a detailed circuit block diagram illustrating the configuration of the D stage and A stage shown in FIG. 1, and FIG. 17 is a logic circuit diagram showing an example of the prohibited addressing mode detection circuit shown in FIG. 16. Figure 18 is a correlation diagram explaining the prohibited addressing mode, Figures 19 to 21 are schematic diagrams explaining the configuration of bit assignments of data transfer commands, and Figure 22 is a diagram showing the relationship between conventional addressing mode types and access clusters. It is a correlation diagram explaining a relationship. In the figure, 1 is IF stage, 2 is D stage, 3 is A stage, 4 is F stage, 5 is E Stella, 6 is R stage, 7 is OF stage, 8 is instruction code, 9 is D code,
10 is A coat, 11 is R code, 12 is F code, 1
3 is the E code, and 14 is the S code. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a data processing device that processes an operand instruction, the data processing device has an operation specification field that specifies an operation of the instruction and an operand specification field that allows operand specification using a general-purpose addressing mode, and a first field into which a value of the operation specification field is input. information input means; and a first field information input means for analyzing the value of the operation specification field inputted by the first field information input means and outputting prohibited address information for the operand specified by the operation specification field. an output means, a second field information input means for inputting the value of the operand specification field, and addressing mode information specified by analyzing the value of the operand specification field input from the second field information input means. The second output
output means, and detection means for detecting an abnormality in the designated addressing mode based on the value of the operand designation field and the value of the operation designation field output from the first or second output means. A data processing device characterized by: