JPH02285671A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To inhibit an augmentation in the area of a memory cell array region and to obtain a semiconductor storage device, wherein the unbalance of the capacities between adjacent data lines is dissolved, by a method wherein the electrical connecting regions of word lines with low resistance metallic wirings are provided between complementary data lines for dummy use, which have a sense amplifier and do not have a switching transistor. CONSTITUTION:In a semiconductor storage device, wherein a plurality of word lines, which are extended in one direction within a memory cell array region on a semiconductor substrate, and a plurality of data lines 5a to 5f, which are extended in the direction to intersect orthogonally to the word lines, are formed, the lines 5a to 5f are arranged in such a war that complementary data lines respectively adjoin in parallel to the data lines 5a to 5f and the word lines are electrically connected with low-resistance metallic wirings 6, which are extended in the direction identical with that of the word lines within the memory cell array region, electrical connecting regions 8 of the word lines with the wirings 6 are provided between complementary data lines 14a and 14b for dummy use, which have at least a sense amplifier 15 and do not have a switching transistor which is selected using the address of a column for performing readout of data to the outside and writing of data from the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to improvements in the structure of a semiconductor memory device.

[Prior Art] In conventional semiconductor memory devices, particularly in one-transistor type dynamic memories, word lines of memory cells are constructed of polycrystalline silicon extending in one direction. This configuration is used because it is easy to form memory cells, but as the capacity of semiconductor memory devices increases, the word lines become longer and thinner, and their resistance increases. Signal delay due to this problem has become a problem.

For this reason, recently, low-resistance metal wiring such as aluminum is provided in parallel with the word line and electrically connected to the word line at predetermined distances within the memory cell array area, thereby delaying the word line signal. is prevented.

FIG. 3 is a plan view showing a connection part with a word line provided in the memory cell array area of such a one-transistor type dynamic memory, and FIG.
FIG.

In FIGS. 3 and 4, the word line 4 is formed of polycrystalline silicon extending in one direction, and an aluminum wiring 6 is provided parallel to the word line 4 in a gap provided in the memory cell array area. The contacts and holes 8 are electrically connected to each other.

[Problem to be Solved by the Invention] As described above, in order to provide a connection between a word line and an aluminum wiring, a gap must be provided in the memory cell array area, but this gap may cause problems in circuit operation. It becomes the cause.

This point will be explained below.

FIG. 5 is a block diagram schematically representing the connection section shown in FIG. 3, and parts having the same functions as those in FIG. 3 are given the same numbers. Further, as shown in FIG. 5, a sense amplifier 9 is provided between mutually complementary data lines, and serves to amplify minute signals read out from the memory cells to the data lines 5a to 5f. There is. Then, one of the switching transistors 11 is selected by the column address to read or write data.

Furthermore, there are various parasitic capacitances in actual data lines, and among them, the capacitances between adjacent data lines particularly relevant to the present invention are shown as 10a to 10d.

In FIG. 5, data lines in the memory cell array area,
For example, in 5d, adjacent data line capacitances 10b and 10c exist between the data lines 5c and 5e on both sides, but the data line 5d is adjacent to the connection between the word line and the aluminum wiring.
The capacitance between adjacent data lines of C is only 10b. Therefore, the data lines 5C and 5d, which are complementary to each other, have different capacitances between adjacent data lines, and this capacitance causes an imbalance in the reception of noise.

Further, the finished shape of the data lines 5b and 5c adjacent to the connection portion between the word line and the aluminum wiring may be different from the shape of the data line in the memory cell array region. This is because the density of the pattern is different compared to that in the memory cell array area, resulting in a difference in the thickness of the photoresist and a difference in the etching speed. This difference in finished shape also causes an unbalance in the parasitic capacitance of the mutually complementary data lines 5c and 5d.

In a one-transistor type dynamic memory, the data line and sense amplifier are the parts that handle the smallest signals, and there is a drawback in that the existence of the above-mentioned imbalance in these parts causes malfunction of the circuit.

To deal with such defects, for example, as shown in FIGS. 6 and 7, dummy patterns 13a, which have the same shape as the data line,
If 13b is provided on the side where the word line and the aluminum wiring are connected, the unbalance caused by the difference in the finished shape can be reduced.

However, since the dummy patterns 13a and 13b are generally fixed at a constant potential (for example, the same potential as the plate electrode 3), the mutually complementary data lines 5c and 5d still suffer from unbalanced noise received from adjacent data lines. There is a problem that arises.

In order to solve the above problem, the potential of dummy patterns 13a and 13b having the same shape as the data line may be changed in the same manner as the actual data line, and the pattern may be used as a dummy data line. That is, all circuits connected to the actual data line, such as memory cells, sense amplifiers, precharge circuits, etc., may be connected to the dummy pattern. The difference from an actual data line is that the structure does not include a switching transistor selected by a column address for reading amplified data to the outside or writing data from the outside.

FIG. 8 is a block diagram showing a state in which a dummy data line is provided adjacent to a connection portion between a word line and an aluminum wiring. In the figure, 14a, 14b, 14c, and 4d are complementary dummy data lines, and 5 is a dummy sense amplifier. As a result, the dummy data lines 14a to 14d operate in the same manner as the actual data lines, so the noise that the data line 5c receives from the adjacent data line is almost the same as the noise that the data line 5d receives, which improves circuit operation. Problems will no longer occur.

However, the arrangement shown in FIG. 8 results in an increase in the area of the memory cell array region.
Since there are nearly 10 connection points between the word line and the aluminum wiring provided in the memory cell array region, and in some cases more than 10 points, the problem arises that the influence becomes extremely large.

The present invention has been made in view of the above-mentioned conventional circumstances, and it is an object of the present invention to provide a semiconductor memory device that suppresses an increase in the area of a memory cell array region and eliminates the unbalance of capacitance between adjacent data lines.

[Differences between the invention and the prior art] In contrast to the conventional semiconductor memory device described above, the present invention replaces the connection portion between the word line and the low resistance metal wiring provided in the memory cell array region with a dummy data line and its supplement. The difference is that by providing the data line between the signal and the dummy data line, the increase in the area of the memory cell array region is minimized and the unbalance between the actual data line and the capacitance between adjacent data lines is eliminated.

[Means for Solving the Problems] A semiconductor memory device of the present invention has a memory cell array region in which a plurality of memory cells are arranged in rows and columns on a semiconductor substrate, and extends in one direction within the memory cell array region. a plurality of word lines extending in a direction perpendicular to the word lines and a plurality of data lines extending in a direction perpendicular to the word lines, each of the data lines having a complementary signal data line arranged adjacent to the line in parallel; In a semiconductor memory device that is electrically connected to a low-resistance metal wiring extending in the same direction as the word line in a memory cell array area, an electrical connection area between the word line and the low-resistance metal wiring is provided. , provided at the opening of a dummy complementary data line that has at least a sense amplifier and does not have a switching transistor selected by a column address for reading data to the outside and writing data from the outside. It is characterized by:

[Example] Next, the present invention will be explained using the drawings.

It should be noted that parts having the same functions as those in the prior art are given the same numbers and the description thereof will be omitted.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, mutually complementary dummy data lines 14a
, 14b is provided between the word line and the low resistance metal wiring, and a dummy sense amplifier 15 is provided between the dummy data lines 14a and 14b. Note that dummy data lines 14a, 14. Everything connected to the actual data lines 5a to 5f, such as memory cells and precharge circuits, is connected to b, but these are omitted in FIG.

With this configuration, the dummy data line 1
4a and 14b also operate in the same way as the actual data lines 5a to 5f, and for the actual data lines 5b and 5c, it is as if actual data lines exist on both sides, and the density of the pattern is reduced. Both in terms of noise received from adjacent data lines, it is possible to make them in the same state as the complementary data lines 5a and 5d, respectively.

By providing a pair of complementary dummy 9 data lines 14a and 14b, the above-mentioned effects can be obtained, and the memory cell array area is reduced compared to the case where two pairs of dummy data lines are provided as shown in FIG. Area increase can be minimized.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

Recently, with the miniaturization of patterns in semiconductor memory devices, the distance between adjacent data lines has become smaller, and as a result, the capacitance between adjacent data lines has also increased. Therefore, in order to minimize the imbalance in the capacitance of mutually complementary data lines,
A structure is used in which mutually complementary data lines intersect within the memory cell array region. FIG. 2 shows a device to which the present invention is applied to such a semiconductor memory device.

In FIG. 2, mutually complementary dummy data lines 14
Similarly to the actual data lines 5a to 5h, the data lines a and 14b also intersect within the memory cell array region to reduce the imbalance in capacitance between adjacent data lines.

[Effects of the Invention] As described above, the present invention provides an electrical connection region between a word line and a low-resistance metal wiring between mutually complementary data lines, and connects the mutually complementary data lines with at least The area of the memory cell array area was This has the effect of minimizing the increase in capacitance between adjacent data lines of mutually complementary data lines used in actual data reading and writing, thereby preventing malfunction of the circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
The figure is a block diagram showing a second embodiment of the present invention, FIG. 3 is a plan view showing a conventional semiconductor memory device, FIG. 4 is a sectional view taken along line A-A in FIG. 3, and FIG. FIG. 3 is a block diagram of a conventional semiconductor memory device, FIG. 6 is a plan view of another conventional semiconductor memory device, and FIG. 7 is a block diagram of the semiconductor memory device shown in FIG. FIG. 8 is a block diagram showing yet another conventional semiconductor memory device. 1...P-type semiconductor substrate, ]2- 2...Field oxide film, 3...
...Plate electrode, 4... ...Word line, 5a to 5f...
・・・Data line, 6・・・・・・Aluminum wiring, 7・・・・・・
...N-type semiconductor region, 8...Contact hole, 9...Sense amplifier, 10a to 10f...Capacitance between adjacent data lines, 1]・・・
...Switching transistor, 12...
...I10 line, 13a, 13b..., dummy pattern, 14a-14
d...Dummy data line 15...Dummy sense amplifier. Patent applicant: NEC Corporation

Claims (1)

[Claims] A semiconductor substrate has a memory cell array region in which a plurality of memory cells are arranged in rows and columns, a plurality of word lines extending in one direction within the memory cell array region, and a plurality of word lines extending in a direction perpendicular to the word lines. form multiple data lines,
A complementary signal data line is arranged adjacent to each of the data lines in parallel, and the word line is electrically connected to a low resistance metal wiring extending in the same direction as the word line within the memory cell array region. In a semiconductor memory device, the electrical connection region between the word line and the low resistance metal wiring is connected to a column having at least a sense amplifier and for reading data to the outside and writing data from the outside. 1. A semiconductor memory device characterized in that a switching transistor selected by an address is provided between dummy complementary data lines without a switching transistor.