JPH02285180A - Operation controller - Google Patents

Abstract

PURPOSE:To prevent dishonest operation by providing a two-comparison circuit making at least one code variable in an electronic lock controlling a plurality of switches with a specific order. CONSTITUTION:The first code signal memory means, the second code signal memory means and a comparison circuit are provided to an operation control ling circuit 10, and when input codes from a switch 11 are correspondent to together, a driving signal is transmitted to a solenoid 13. After that, based on a coincidence signal of the comparison means, either one of the first and second code signals is at least promoted to renew the code signal memory. If necessary, a memory means is a memory mode to rewrite to a new code signal. According to the constitution, at least either the first code signal or the second code signal varies, so that the risk of a dishonest use can be prevented even if the code signal is seen by another person.

Description

[Detailed Description of the Invention] This invention relates to an operation control device, particularly an operation control device used as an electronic lock that can be unlocked by operating a plurality of switches in a predetermined order. .

In recent years, systems have been proposed that use magnetic cards or punch cards to lock and unlock door lock control devices instead of using metal keys.

Furthermore, a keyless entry system has been proposed in which an electronic lock is unlocked by inputting the same code symbol as a pre-registered number using a plurality of switches, without using a portable key or card.

For example, as shown in Japanese Patent Publication No. 58-14910, a system for unlocking a door using a card is known. Further, as shown in Japanese Patent Application Laid-Open No. 56-105076 and Japanese Patent Publication No. 59-32632, electronic locks are known that generate an unlocking signal by operating WL number of switches in a predetermined order.

However, if the number of digits in the code code used in a keyless entry system is too large, it is difficult to memorize it, which is inconvenient for the user. On the other hand, if the number of digits in the code code used is small, it becomes possible to illegally unlock the door by repeatedly operating the switch. Furthermore, while the user is operating the switch, someone else may see the code number and then illegally unlock the door.

Therefore, it is an object of the present invention to provide an operation control device that can hardly be operated by anyone other than a specific person who has relatively clearly recognized the correct code even if the code entered by the switch is seen by another person.

The operation control device according to the present invention includes a plurality of switches that generate different code signals, a first code storage means that generates a first code signal, and a second code signal that generates a second code signal. Generated by the second code storage means, one of the first code storage means stored in the first code storage means and the second code storage means stored in the second code storage means, and a plurality of switches. a comparison means that compares the code signs of the comparison means and generates a coincidence signal when they match, and generates a coincidence signal when both of them match, a first coincidence signal of the comparison means and a second coincidence signal of the second comparison means and output means for generating a drive signal to the controlled device when a coincidence signal is generated.

At least one of the first code symbol generated by the first storage means or the second code symbol generated by the second storage means is a variable code symbol.

In this specification, the term "code code" includes numbers, letters, symbols, alphabets, etc., and includes all codes used to identify multiple switches, and the term "variable code code" refers to comparison means. The sign signal is progressive based on the coincidence signal of the pulse generating circuit or is changed based on the count value of the output signal of the pulse generating circuit.

In an embodiment of the invention, either the first code symbol generated by the first storage means or the second code symbol generated by the second storage means may be a variable code symbol.

In one embodiment of the present invention, the comparing means first compares the fixed first code symbol generated by the first storage means and the code symbols generated by the plurality of switches, and when they match, the first fixed code symbol is A match signal is generated, and then the variable second code code generated by the second storage means is compared with the code codes generated by the plurality of switches, and when they match, a second match signal is generated.

In another embodiment of the present invention, the comparison means first compares the variable second code code generated by the second storage means and the code codes generated by the plurality of switches, and when they match, The first storage means generates a second match signal, and then compares the fixed first code code generated by the first storage means with the code codes generated by the plurality of switches, and when they match, generates the first match signal. Occur.

The variable code sign is progressive based on the coincidence signal of the comparing means or is changed based on the count value of the output signal of the pulse generating circuit.

The first code code stored in the first storage means is rewritten with a new code code in place of the first code code when in the storage mode, and the second code code generated by the second storage means is rewritten. is a variable code sign.

When a code signal is generated by operating a plurality of switches in a predetermined order, the comparing means compares the code signal with the first code code stored in the first code code storage means or the second code signal. A comparison is made with one of the second code symbols stored in the code symbol storage means. When these match, the comparison means further operates the plurality of switches to compare the code generated by operating the plurality of switches with the first code stored in the first code storage means or the second code stored in the second code storage means. compared with the other of the second code symbol. When a match is found in the comparison with the other, the comparison means generates a match signal.

The controlled device is driven based on this coincidence signal.

At least one of the first code symbol generated by the first storage means or the second code symbol generated by the second storage means is a variable code symbol.

For example, the user initially uses the code number "
123'' using the switch. Thereby, the comparison means compares the fixed code stored in the first code storage means and the code number r123J, for example. Next, when the user inputs the code number "5" from the switch, the code comparison means compares the code number stored in the second code storage means with the code number "5",
When a match occurs, a match signal is generated to drive the controlled device. At this time, the second code storage means is advanced by the matching signal of the comparison means. For example, the second code symbol storage means is constituted by a counter to which the first code symbol is sequentially added. Therefore, when a matching signal is generated from the comparison means, the second code symbol storage means changes from "5" to "6".
A second code symbol is generated that is progressive.

Therefore, the next time the user generates an input signal using the switch, he inputs the code number "rL23" and then inputs the code number "6" from the switch, allowing the comparison means to generate a matching signal. That is, when the user first inputs the code number "123" when generating an input signal with the switch, the comparison means compares the fixed code code stored in the first code code storage means with the code number r.
Next, when the user inputs the progressive code number "6" from the switch, the code comparison means compares the code number stored in the second code storage means with the code number "6". ” and when they match, a match signal is generated to drive the controlled device.

The second code symbol generated by the second code symbol storage means can be generated in various ways.

For example, when using an up/down counter to sequentially advance the second code symbol by subtraction, count the output of the pulse generator circuit that constitutes the clock circuit, and convert the month, day, or time signals to the second code symbol. from the second code storage means to the comparison means. The order in which the comparing means compares can be determined as appropriate, and it is also possible to first compare the code sign by the switch with the second code sign, and then compare it with the -th code sign.

Further, when the first storage means is in the storage mode, the first code code stored in the first storage means is rewritten with a new code code inputted from the plurality of key switches. Therefore, from then on, the controlled device cannot be operated unless a new code symbol and a second code symbol are input.

Embodiments of the present invention will now be described with reference to FIGS. 1 to 7.

First, as shown in FIG. 1, the operation control circuit 1° includes an input port to which a plurality of switches 11 displaying numbers O to 9 are connected, and an input port to which a switch 12 for setting a password is connected. , an output port to which a solenoid 13 that operates a lock device as a controlled device is connected, and an output port to which a buzzer 14 and a light emitting element 15 as a display device 16 are connected. As shown in FIG. 2, the plurality of switches 11 and the display device are integrally provided on the operation panel.

The operation control circuit 1o includes a first code storage means for generating a first code sign, a second code storage means for generating a second code sign, and a code stored in the first code storage means. When one of the first code code and the second code code stored in the second code code storage means matches the code codes generated by the plurality of switches, the other code code is compared and both match. and comparison means for generating a coincidence signal. The solenoid 13 as a controlled device is driven based on the coincidence signal of the comparison means.

The operation control circuit 1o is operated based on the operation sequence shown in FIG. That is, in step 20, the comparison means determines whether there is a switch input from the switch 11 or not. Here, when a plurality of switches 11 are operated in a predetermined order to generate a code signal, the process proceeds to step 21, where the comparison means converts this code signal into a first code stored in the first code storage means. Compare with sign. When there is a match.

Proceeding to step 22, the comparison means then compares the code input by switch 11 with the second code symbol stored in the second code symbol storage means. When this matches, the comparing means generates a matching signal, and the solenoid 13 is driven based on this matching signal (step 23).
). Subsequently, the second code symbol is progressed in the second code symbol storage means (step 24).

For example, the user initially uses the code number "
058'' is input using the switch 11.

As a result, the comparison means compares the fixed code stored in the first code storage means with the code number r05, for example. Next, the user selects the code number “1” from the switch.
”, the code sign comparison means compares the code sign stored in the second code sign storage means with the code number “1”.
” compared to.

When a match occurs, a match signal that drives the solenoid 13 is generated. At this time, the second code storage means is advanced by the matching signal of the comparison means.

Next, FIG. 4 shows an example in which the operation control circuit 10 is constituted by a discrete circuit. The plurality of switches 11 are connected to a comparator 31 and an OR gate 32 via a BCD (pinary coded decimal) conversion circuit 30 that can prevent chattering. The output of the OR gate 32 is supplied via a one-shot multivibrator 33 to a buzzer 14, a retrigger shot multivibrator 34, and an address counter 35. Buzzer 14 is switch 1゜1
is energized by the output of the OR gate 32, which is generated every time the signal is suppressed, and generates an auditory signal. Retrigger one-shot multivibrator 34 is one-shot multivibrator 3
3, it generates an output having a pulse width of about 5 seconds, and when it receives the next input within 5 seconds, it starts counting the pulse width again from that point. When the output of the retrigger shot multivibrator 34 stops, the one-shot multivibrator 36 generates an output at the falling edge of the pulse, and operates the OR gate 37.3.
A clear signal is given to the address counter 35 through 8. The address counter 35 counts the number of outputs from the one-shot multivibrator 33 and generates an address signal for each digit. The address signal of the address counter 35 is applied to a first memory 40 and a second memory 41. The output terminals of the first memory 4o and the second memory 41 are connected to the comparator 3.
Connected to 1. The digit number detection circuit 39 generates a clear signal when the value of the address counter 35 reaches a certain value.

The one-shot multivibrator 33 is connected to one input terminal of the AND gate 51 via the delay circuit 50.
The output terminal of AND gate 51 is connected to the clear terminal of address counter 35 via OR gates 37 and 38.

The output terminal of the comparator 31 is connected to the first counter 42 , the second counter 43 and the inverting input terminal of the AND gate 51 . The output terminal of the first counter 42 is connected to the set terminal of an R/S flip-flop 45 via a one-shot multivibrator 44 . The ζ terminal and ζ terminal of the R/S flip-flop 45 are connected to the first memory 4, respectively.
0 and the E/D (enable/disable) terminal of the second memory 41. The R/S flip-flop 45 is normally held in a reset state and generates an output from the ζ terminal, so that the first memory 40 is maintained in a readable state. Further, the terminal and ζ terminal of the R/S flip-flop 45 are connected to the E/D terminal of the first counter 42 and the second counter 43, respectively.

Further, the ζ terminal of the R/S flip-flop 45 is connected to one input terminal of an AND gate 46.

The output terminal of the second counter 43 is connected to the other input terminal of the AND gate 46 . The output terminal of the AND gate 46 is a counter 47, and a solenoid 1 as a controlled device.
3 and an OR gate 48. The counter 47 increments every time it receives a signal from the AND gate 46 and applies the incremented code signal to the second memory 41 . Further, the solenoid 13 is actuated by the output of the AND gate 46, and the R/S flip-flop 45 is reset via the OR gate 48. The output of the OR gate 37 is applied to an OR gate 48, and the output of the OR gate 38 is applied to each clear terminal of the first counter 42 and the second counter 43. The counter 47 is constituted by a normal counter, an up/down counter, or other arithmetic circuit.

In the above configuration, the R/S flip-flop 45 is in the reset state in the initial state, and a high level signal is generated from the ; terminal.

A low level signal is generated from the ζ terminal. For this reason,
The first memory 40 and the first counter 42 are kept enabled, and the second memory 41 and the second counter 43 are kept disabled. In this state, when the switches 11 are operated in a predetermined order and an input signal is applied to the comparator 31, the comparator 31 compares the input signal with the code stored in the first memory 40 and matches the input signal. When this happens, a match signal is given to the first counter 42.

In this case, even though one of the switches 11 is operated, if the code signal of the switch 11 and the code signal stored in the first storage device 40 do not match, no output signal is generated from the comparator 31. Therefore, an invalid signal is generated from the AND gate 51 and the address counter 35 is cleared.

However, when the code signal input from the switch 11 and all the code signals stored in the first memory 40 match in all digits, the first counter 42 generates an output and sends the signal via the one-shot multivibrator 44. to switch the R/S flip-flop 44 to the set state.

Therefore, the ζ terminal of the R/S flip-flop 45 generates a low level signal, and the ζ terminal generates a high level signal. Accordingly, the second memory 41 and the second counter 43 are switched to an enabled state, and the first memory 40 and the first counter 42 are switched to a disabled state. In this state.

When the switch 11 is operated once or in a predetermined order to apply an input signal to the comparator 31, the comparator 31 compares the input signal with the code stored in the second memory 41,
When they match, a match signal is given to the second counter 43. In this case, if the code signal of the switch 11 does not match the code signal stored in the second memory 40 even though any switch 11 is operated, the output is output from the comparator 31 in the same way as above. Since no signal is generated, an invalid signal is generated from the AND gate 51 and the address counter 35 is cleared. However, when the code signal inputted from the switch 11 and all the code signals stored in the second memory 41 match in all digits, the second counter 43 generates an output to the OR gate 37 and the AND gate 46 . At this time, since the R/S flip-flop 45 is in the set state, the AND gate 46 generates an output and drives the solenoid 13, and also advances the counter 47 or outputs the R/S flip-flop 45 via the foregate 48. Switch to reset state. Therefore, the code progressively added from the counter 47 is given to the second memory 41. For example, the counter 47 is configured of a counter to which output signals are sequentially added. Therefore, when a match signal is generated from the second counter 43, the counter 47 generates an output progressive from "5" to "6".

Therefore, when the primary user generates an input signal using the switch 11, the comparator 31 can generate a matching signal by inputting the code number r123J and then inputting the code number "6" from the switch. That is, when the user first inputs the code number "123" when generating an input signal using a switch, the comparator 31 compares the fixed code stored in the memory 40 with the input code number r123J. do. Next, the user switches switch 1
When a code number that is the same as the code number "6" that is progressive from 1 is input, the comparator 31 compares the code code stored in the second storage device 41 with the input code number "6", When a match occurs, a match signal that drives the solenoid 13 is generated.

Various modifications can be made to the above-described embodiments of the invention. For example, in the above embodiment, the second code code generated by the second storage means is variable, but the first code code generated by the first storage means or the second code code generated by the second storage means is Any of the generated second code symbols may be variable code symbols.

That is, as shown in FIG. 5, the output of the AND gate 46 is applied to the counters 47 and 57, and the second counter
These counters 47 and 57 can be incremented each time an output is generated. Therefore, the user can operate the solenoid 13 by inputting from the switch 11 the first code code and the second code code that are progressively increased each time the solenoid 13 is operated. In this case, the first code symbol and the second code symbol may be made progressive by different functions or random numbers.

Further, the order in which the comparator 31 compares can be determined as appropriate. In other words, the comparing means first compares the fixed first code symbol generated by the first storage means and the code symbols generated by the plurality of switches, and when they match, generates the first coincidence signal. First, the variable second code generated by the second storage means and the code generated by the plurality of switches can be compared, and when they match, the second matching signal can be generated. The comparing means first compares the variable second code generated by the second storage means and the code generated by the plurality of switches, and when they match, generates a second matching signal. The fixed first code generated by the first storage means and the code generated by the plurality of switches may be compared and when they match, the first coincidence signal may be generated.

Specifically, the Q terminal of the R/S flip-flop 45 and ζ
Just connect the terminals in reverse.

The variable code code is progressive by the counter 47 based on the matching signal of the comparing means, but various progressive codes can be used not only for addition or subtraction, but by subtracting by an up/down counter or calculating according to a predetermined formula. I can do it.

Furthermore, the variable code sign may be changed based on the count value of the output signal of the pulse generation circuit. Specifically, as shown in FIG.
can be connected.

The output of the pulse generating circuit 53 constituting the clock circuit 52 can be counted, and a signal related to the month, day, or time can be given as a second code from the second memory 41 to the comparator 31. Similarly, the first memory 40 also has a clock circuit 52.
may be connected.

Furthermore, as shown in FIG. 7, the calculation mode such as addition and subtraction can be changed by switching the switch 55 connected to the calculation circuit 54, and the desired code input from the switch 11 can be changed to the first code by switching the switch 12. It can be stored in the storage device 40.

That is, when the input code generated by operating the plurality of switches 11 in a predetermined order and the code code stored in the first storage device 40 match, the first counter 42 generates an output. This sets the R/S flip-flop 45 and produces an output from the Q terminal. At this time, one input terminal of the AND gate 60 is connected to the first counter 42 or R/
Since the signal from the Q terminal of the S flip-flop 45 is supplied, when the switch lla is operated, the AND gate 6
0 generates an output, R/S flip-flop 61 is set, and first memory 40 is switched to storage mode.

Here, when the switches 11 are operated in a desired order, a desired code signal is stored in the first memory 40. When a certain period of time elapses after the operation of the switch 11 is stopped, the signal from the retrigger one-shot multivibrator 34 stops, so the one-shot multivibrator 36 generates an output and the R/S flip-flop 61 and other circuits are reset. be done. Thereafter, the solenoid 13 cannot be operated unless the new first code stored in the first memory 40 and the input code signal match. Operate switch 12 instead of switch lla,
The first storage device 4o may be switched to storage mode.

2. As mentioned above, in this invention, at least one of the first code symbol and the second code symbol changes, so even if someone sees the code symbol, the controlled device cannot be operated illegally. There is no danger.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing the operation control device according to the present invention, FIG. 2 is a front view of the operation panel, and FIG. 3 is a flowchart showing the operation sequence of the operation control circuit shown in FIG.
FIG. 4 is an electric circuit diagram showing another embodiment in which the operation control device according to the present invention is constituted by a discrete circuit, and FIG. 5 shows the first code code of the first memory device and the second code code of the second memory device. FIG. 6 is an electric circuit diagram showing another embodiment in which the second code sign changes together with the clock circuit; FIG. FIG. 4 is an electrical circuit diagram showing another embodiment in which the data is switched to a storage mode in which the data can be stored. 100. Operation control circuit, 11. , switch, 139
．． Solenoid (controlled device), 31. . Comparator (comparison means), 409. First storage device (first code storage means), 41. , a second memory (second code symbol storage means). Figure 1 Patent applicant: Kokusan Metal Industry Co., Ltd. Representative: Takashi Shimizu-1〆, -1 (Suzuki or 1 person)\
− ~, n

Claims (7)

[Claims] (1) A plurality of switches that generate different code signals, a first code storage means that generates a first code signal, a second code storage means that generates a second code signal, and a first code storage means that generates a second code signal; When one of the first code code stored in the code code storage means and the second code code stored in the second code code storage means and the code code generated by the plurality of switches match. Comparing means generates a match signal when both match compared with the other;
a controlled device that is driven based on the coincidence signal of the comparison means, and at least one of the first code code generated by the first storage means or the second code code generated by the second storage means. An operation control device characterized by a variable code sign. (2) The operation control according to claim (1), wherein either the first code generated by the first storage means or the second code generated by the second storage means is a variable code. Device. (3) The comparison means first compares the fixed first code generated by the first storage means and the code generated by the plurality of switches, and when they match, generates a first coincidence signal. According to claim (1), the variable second code generated by the second storage means is then compared with the code generated by the plurality of switches, and when they match, a second coincidence signal is generated. Operation control device as described. (4) the comparison means first compares the variable second code generated by the second storage means with the code generated by the plurality of switches, and when they match, generates a second coincidence signal; Claim (1) further comprising: comparing the fixed first code code generated by the first storage means with code codes generated by the plurality of switches and generating a first coincidence signal when they match; Operation control device as described. (5) The operation control device according to any one of claims (1) to (4), wherein the variable code sign is progressive based on a coincidence signal from the comparing means. (6) The operation control device according to any one of claims (1) to (4), wherein the variable code sign is changed based on the count value of the output signal of the pulse generation circuit. (7) a plurality of switches that generate different code signals; a first code storage means that generates a first code; a second code storage means that generates a second code; The first code code stored in the code code storage means and the code code generated by the plurality of switches are compared and when they match, the second code code stored in the second code code storage unit and the code code generated by the plurality of switches are compared. Comparing means for comparing the code symbols generated by the plurality of switches and generating a coincidence signal when they match, and a controlled device driven based on the coincidence signal of the comparison means, the first storage means The first code code stored in the storage means is rewritten with a new code code in place of the first code code when in storage mode, and the second code code generated by the second storage means is a variable code code. An operation control device characterized by: