JPH02277255A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02277255A
JPH02277255A JP9931989A JP9931989A JPH02277255A JP H02277255 A JPH02277255 A JP H02277255A JP 9931989 A JP9931989 A JP 9931989A JP 9931989 A JP9931989 A JP 9931989A JP H02277255 A JPH02277255 A JP H02277255A
Authority
JP
Japan
Prior art keywords
interlayer insulating
insulating film
film
thickness
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9931989A
Other languages
Japanese (ja)
Inventor
Etsushi Adachi
悦志 足立
Yoshiko Aiba
相葉 美子
Hiroshi Adachi
足達 廣士
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9931989A priority Critical patent/JPH02277255A/en
Publication of JPH02277255A publication Critical patent/JPH02277255A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To increase a heat-resisting property and to enhance reliability by a method wherein an interlayer insulating film is formed of a specific phenyl silicone ladder polymer whose end is a hydroxyl group. CONSTITUTION:The following are provided: a semiconductor substrate 1 composed of silicon; a protective film 2 composed of plasma SiN; an interlayer insulating film 4; a contact hole 5 which has been formed in the interlayer insulating film 4 by a photolithographic technique. The interlayer insulating film 4 is formed of a phenyl silicone ladder polymer whose end is a hydroxyl group as expressed by Formula I. In Formula I, (n) represents an integer of 2 to 1000. In addition, a film thickness of the interlayer insulating film 4 is prescribed by a thickness of an electrode layer to be insulated; however, it is preferable that the film is formed in a thickness of 1.0 to 3.0mum in order to keep a good balance among a stray capacitance, a flat property and a processing property. Thereby, a heat-resisting property is excellent; a characteristic is not deteriorated even when an upper-layer wiring part is formed; reliability can be enhanced.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、2層以上の多層配線構造を有する半導体装置
に関する。さらに詳しくは、層間絶縁膜(式中、4個の
R3は同一または異なりそれぞれが水素原子、メチル基
またはエチル基であり、20個のR2は同一または異な
り半数以上のR2はメチル基であるが、残りのR2はエ
チル基、フェニル基、クロルフェニル基、ヒドロキシ基
、メトキシ基またはエトキシ基であり、そしてnは15
00〜200000の分子量を与えるに充分な整数であ
る)で表わされるラダー形オルガノポリシロキサンが開
示されている。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a multilayer wiring structure of two or more layers. More specifically, the interlayer insulating film (in the formula, 4 R3s are the same or different and each is a hydrogen atom, a methyl group, or an ethyl group, and 20 R2s are the same or different, and more than half of the R2s are methyl groups). , the remaining R2 is an ethyl group, phenyl group, chlorophenyl group, hydroxy group, methoxy group or ethoxy group, and n is 15
00 to 200,000, an integer sufficient to give a molecular weight of from 0.00 to 200,000.

前記構造式[1)で表わされるラダー形オルガノポリシ
ロキサンは、シリコン原子数と酸素原子数との比がほぼ
1:1.5で、シリコン原子数と側鎖数との比がほぼl
:1で、従来半導体装置の保護樹脂として用いられてい
た線状ポリシロキサンと相違するもので、シロキサンが
梯子構造であるため耐熱性にすぐれている。構造式(1
)で表わされるラダー形オルガノポリシロキサンのうち
、側鎖R2はすべてがメチル基であるかまたは半数以上
がメチル基で残りがフェニル基であるのがよく用いられ
、とりわけ構造式(■): (式中nは、1500〜200000の分子量を与える
のに充分な整数である)で表わされるラダー形オルガノ
ポリシロキサンがよく用いられる。
The ladder organopolysiloxane represented by the structural formula [1] has a ratio of the number of silicon atoms to the number of oxygen atoms of approximately 1:1.5, and a ratio of the number of silicon atoms to the number of side chains of approximately 1:1.
:1, which is different from the linear polysiloxane conventionally used as a protective resin for semiconductor devices, and because the siloxane has a ladder structure, it has excellent heat resistance. Structural formula (1
) Among the ladder-type organopolysiloxanes represented by the formula (■), it is often used that all of the side chains R2 are methyl groups, or more than half are methyl groups and the remainder are phenyl groups, especially those with the structural formula (■): ( Ladder organopolysiloxanes are often used, where n is an integer sufficient to provide a molecular weight of 1,500 to 200,000.

[発明が解決しようとする課題] 特開昭58−49540号公報によれば、構造式(II
IlのR2がエチル基、プロピル基、フェニル基のばあ
いの熱分解温度はそれぞれ約350.320.400℃
で、メチルのばあい700〜740℃と示されている。
[Problem to be solved by the invention] According to Japanese Patent Application Laid-open No. 58-49540, structural formula (II
When R2 of Il is an ethyl group, a propyl group, or a phenyl group, the thermal decomposition temperature is approximately 350.320.400°C, respectively.
In the case of methyl, it is indicated as 700-740°C.

しかしながら、本発明者らの実験によれば、メチル基の
ばあいせいぜい450℃の耐熱性を有するにすぎないこ
とがわかった。
However, according to experiments conducted by the present inventors, it was found that the methyl group has a heat resistance of only 450°C at most.

したがって、従来のメチル基を側鎖にもつラダー形オル
ガノポリシロキサンを層間絶縁膜に使用した半導体装置
は、耐熱性が低いため上層の配線を形成するプロセスに
おける加工温度に耐えられず、えられた半導体装置の信
頼性が低いという問題点を有することになる。
Therefore, semiconductor devices that use conventional ladder-type organopolysiloxanes with methyl groups in their side chains as interlayer insulating films have low heat resistance and cannot withstand the processing temperatures used in the process of forming upper layer wiring. This poses a problem in that the reliability of the semiconductor device is low.

一方比較的低温で成膜でき、絶縁耐圧の比較的高い層間
絶縁膜としてプラズマSlN膜を利用したものも使用さ
れている。しかし、このものにおいてはSIN膜成膜時
の熱影響によりA#電極膜にヒロックが発生するといっ
た問題を有している。
On the other hand, a plasma SlN film is also used as an interlayer insulating film that can be formed at a relatively low temperature and has a relatively high dielectric strength voltage. However, this method has a problem in that hillocks occur in the A# electrode film due to thermal effects during the formation of the SIN film.

本発明は、前記問題点に鑑みなされたものであって、耐
熱性が高く、平坦性良好な層間絶縁膜をもつ信頼性の高
い半導体装置を提供することを目的としている。
The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a highly reliable semiconductor device having an interlayer insulating film having high heat resistance and good flatness.

[8題を解決するための手段] 本発明の半導体装置は、少なくとも2層配線構造を有す
る半導体装置であって、層間絶縁膜が構造式(I): (式中、jlは2〜1000の整数を示す)で表わされ
る末端水酸基フェニルシリコーンラダーポリマーにより
形成されてなることを特徴としている。
[Means for Solving Problem 8] The semiconductor device of the present invention is a semiconductor device having at least a two-layer wiring structure, in which the interlayer insulating film has the structural formula (I): (where jl is 2 to 1000) It is characterized by being formed from a phenyl silicone ladder polymer with a terminal hydroxyl group represented by (integer).

[作 用] 本発明における末端水酸基フェニルシリコーンラダーポ
リマーの耐熱性は約550℃であるので、層間絶縁膜の
耐熱性を向上することができ、ひいては半導体装置の高
温特性を改善することができる。
[Function] Since the heat resistance of the phenyl silicone ladder polymer with terminal hydroxyl groups in the present invention is about 550°C, the heat resistance of the interlayer insulating film can be improved, and the high-temperature characteristics of the semiconductor device can be improved.

[実施例コ 以下、本発明の半導体装置を図面に基づいて説明するが
、本発明は何もかかる実施例のみに限定されるものでは
ない。
[Embodiment 1] Hereinafter, a semiconductor device of the present invention will be explained based on the drawings, but the present invention is not limited to such embodiments.

第1(a)〜1(e〉図は本発明の層間絶縁膜の成膜手
順についての概略説明図である。
1(a) to 1(e) are schematic explanatory diagrams of the procedure for forming an interlayer insulating film according to the present invention.

第1(ω〜1(e)図において、(1)はシリコンから
なる半導体基板、(2)はプラズマSIN  (IIり
からなる保護膜、(4)は層間絶縁膜、(5)は層間絶
縁膜(4)に写真製版技術により設けられたコンタクト
ホールである。層間絶縁膜(4)は、平坦性、耐熱性な
どを考慮して、構造式(I): [以下余白] で表わされる末端水酸基フェニルシリコーンラダーポリ
マーにより形成されている。nが2〜1000の整数で
あれば、使用温度500℃においても平坦度が害される
ことなく所定の絶縁性を示すが、耐クラツク性の点より
nが30以上の整数であるのが好ましい。nが1以下で
はオリゴマーとなり溶液安定性が悪く、またnがtoo
oをこえれば溶剤に溶けにくくなるので好ましくない。
In Figure 1 (ω~1(e)), (1) is a semiconductor substrate made of silicon, (2) is a protective film made of plasma SIN (II), (4) is an interlayer insulating film, and (5) is an interlayer insulating film. This is a contact hole formed in the film (4) by photolithography.The interlayer insulating film (4) has a terminal end represented by the structural formula (I): It is formed from a hydroxyl phenyl silicone ladder polymer.If n is an integer from 2 to 1000, it will exhibit the specified insulation properties without impairing the flatness even at a service temperature of 500°C, but from the viewpoint of crack resistance, n is preferably an integer of 30 or more. If n is less than 1, oligomers will form, resulting in poor solution stability;
If it exceeds o, it becomes difficult to dissolve in the solvent, which is not preferable.

層間絶縁m (4)の膜厚は、絶縁する電極層の厚さよ
り規定されるが、浮遊容量、平坦性、加工性の兼合いよ
り 1.0〜3.0遍の厚さに成膜させるのが好ましい
。またその成膜法はデイツプ、スクリーン印刷などの方
法が採用しうるが、平坦性、均一性の点よりスピンコー
ド法によるのが好ましい。
The film thickness of the interlayer insulation m (4) is determined by the thickness of the electrode layer to be insulated, but it is formed to a thickness of 1.0 to 3.0 times in consideration of stray capacitance, flatness, and workability. is preferable. Further, as the film forming method, methods such as dip printing and screen printing can be adopted, but from the viewpoint of flatness and uniformity, it is preferable to use a spin code method.

スピンコード法により成膜するばあいは、末端水酸基フ
ェニルシリコーンラダーポリマーは溶媒に溶解して塗布
される。使用する溶媒は安全性の点よりアニソールが好
ましいが、分子量による溶解性の点よりトルエン、キシ
レン、ベンゼンなどの芳香族炭化水素系溶媒、メチルエ
チルケトン、アセトンなどのケトン系溶媒、テトラヒド
ロフラン、ジエチルエーテル、イソプロピルエーテルな
どのエーテル系溶媒、エチルセロソルブおよびN−メチ
ルピロリドンなどを好適に用いることができる。
When forming a film by the spin code method, the phenyl silicone ladder polymer with terminal hydroxyl groups is dissolved in a solvent and applied. The solvent to be used is preferably anisole from the viewpoint of safety, but from the viewpoint of solubility due to molecular weight, aromatic hydrocarbon solvents such as toluene, xylene, and benzene, ketone solvents such as methyl ethyl ketone and acetone, tetrahydrofuran, diethyl ether, and isopropyl. Ether solvents such as ether, ethyl cellosolve, N-methylpyrrolidone, and the like can be suitably used.

スピンコードの回転数は使用する溶媒と溶液の濃度によ
り適宜選定されるが、−例をあげれば溶媒をアニソール
とし濃度を15重量%とじたときは、回転数を350O
rpmとすることができる。濃度と回転数をこのように
規定するのは1.5祠程度の膜厚を均一にコートできる
という理由による。
The rotation speed of the spin cord is appropriately selected depending on the concentration of the solvent and solution used. For example, when the solvent is anisole and the concentration is 15% by weight, the rotation speed is 350 O.
rpm. The reason why the concentration and rotation speed are defined in this way is that a uniform coating can be achieved with a film thickness of about 1.5 mm.

末端水酸基フェニルシリコーンラダーポリマーは通常N
a、 K、 re、 CuSPb、  IIC#、 U
およびThの不純分を含有するが、信頼性の点よりNa
、 K、 Pe。
Phenyl silicone ladder polymers with terminal hydroxyl groups are usually N
a, K, re, CuSPb, IIC#, U
Although it contains impurities of Na and Th, from the point of view of reliability.
, K., Pe.

Cu、 Pb、  HCNについては1 ppm未満、
U%T11については11)I)b未満とするのが好ま
しい。
Less than 1 ppm for Cu, Pb, HCN;
Regarding U%T11, it is preferable that it is less than 11)I)b.

回路素子を有する半導体基板(1)上に形成された層間
絶縁膜(4)は多層配線を構成するために所定箇所にコ
ンタクトホール(5)が形成される。
Contact holes (5) are formed at predetermined locations in an interlayer insulating film (4) formed on a semiconductor substrate (1) having circuit elements to form a multilayer wiring.

このコンタクトホール(9の形成は、層間絶縁膜(4)
上に所定パターンにレジストを塗布したのち、エツチン
グにより所定箇所の層間絶縁m (4)を除去すること
により行なう。使用するレジストは特に限定されないが
汎用性の点よりクレゾールノボラック系のレジストを使
用するのが好ましい。またエツチング液はエツチング速
度、精度の点よりアニソール、キシレンを使用するのが
好ましい。
This contact hole (9) is formed using an interlayer insulating film (4).
This is done by applying a resist in a predetermined pattern thereon, and then removing the interlayer insulation m (4) at a predetermined location by etching. The resist used is not particularly limited, but from the viewpoint of versatility, it is preferable to use a cresol novolak resist. Further, from the viewpoint of etching speed and accuracy, it is preferable to use anisole or xylene as the etching solution.

コンタクトホール(5)が形成されたのち、n−酢酸ブ
チルによりレジストを除去し、熱処理を行ない。
After the contact hole (5) is formed, the resist is removed using n-butyl acetate and heat treatment is performed.

層間絶縁膜(4)を硬化させる。熱処理条件は末端水酸
基の脱水縮合反応の点より 300”C以上とするのが
好ましく、完全硬化させる観点より 350’C以上と
するのがとくに好ましい。
The interlayer insulating film (4) is cured. The heat treatment conditions are preferably 300'C or higher from the viewpoint of dehydration condensation reaction of terminal hydroxyl groups, and particularly preferably 350'C or higher from the viewpoint of complete curing.

コンタクトホール(5)の形成および層間絶縁膜(4)
の硬化がなされたのち、第2電極を成膜し、さらに前記
の手順を繰返して所定のコンタクトホール(5)を有す
る2層目の層間絶縁膜(4)が形成される。
Formation of contact hole (5) and interlayer insulating film (4)
After curing, a second electrode is formed, and the above procedure is repeated to form a second interlayer insulating film (4) having a predetermined contact hole (5).

この手順を繰返せば所望の多層電極を有する半導体装置
が作成できる。
By repeating this procedure, a semiconductor device having a desired multilayer electrode can be produced.

実施例1 所定部分が露出しているチッ化シリコン保護膜(21で
被覆されている回路素子を有する直径的10cm。
Example 1 A silicon nitride protective film (10 cm in diameter) having a circuit element covered with a silicon nitride protective film (21) with predetermined portions exposed.

厚さ 0 、5 amのシリコンウェハ(1)を作成し
、このシリコンウェハ(1)の回路素子上に所定のパタ
ーンで約1廊の厚さのM配線層を形成した(第1(ω図
)参照)。しかるのち、Na、 K、 Pa、 Cu%
pbおよびII C1のそれぞれの含有量が1 ppm
未満であり、UおよびThのそれぞれの含有量が11)
I)b未満である構造式(lit) 。
A silicon wafer (1) with a thickness of 0.5 am was prepared, and an M wiring layer with a thickness of about 1 channel was formed in a predetermined pattern on the circuit elements of this silicon wafer (1) (first (ω diagram)). )reference). After that, Na, K, Pa, Cu%
Each content of pb and II C1 is 1 ppm
and the content of each of U and Th is 11)
I) Structural formula (lit) which is less than b.

で表わされる高純度フェニルシリコーンラダーボリマー
をアニソールに添加し濃度約15重量%の溶液とし、こ
の溶液を前記シリコンウエノ)(1)上に回転速度30
00rp1mでスピンコード法で塗布した。しかるのち
、チッ素雰囲気中で熱処理を250℃の温度で30分間
行ない第1層目の層間絶縁膜(4)を形成した(第1山
)図参照)。そのときの膜厚は 1.5虜であった。
A high-purity phenyl silicone ladder polymer represented by is added to anisole to make a solution with a concentration of about 15% by weight, and this solution is placed on the silicon urethane (1) at a rotation speed of 30%.
Coating was performed using a spin code method at 00 rpm and 1 m. Thereafter, heat treatment was performed at a temperature of 250° C. for 30 minutes in a nitrogen atmosphere to form a first layer of interlayer insulating film (4) (see figure 1). The film thickness at that time was 1.5 mm.

えられた層間絶縁膜(4)に東京応化工業■製0FPR
800からなるレジストを所定パターンで塗布したのち
、アニソール、キシレンを用いてアニソール/キシレン
−1/2の条件にてエツチングを行ない層間絶縁膜(4
)上に所望のコンタクトホール(5)を穿設した。しか
るのち、n−酢酸ブチルによりレジストを除去し、チッ
素雰囲気中で、熱処理を350℃の温度で60分間行な
いコンタクトホール(5)のパターン化を行なうととも
に層間絶縁膜(4)の硬化を行なった(第1(C)図参
照)。
The obtained interlayer insulating film (4) is made of 0FPR manufactured by Tokyo Ohka Kogyo ■.
After applying a resist consisting of 800 nitride in a predetermined pattern, etching was performed using anisole and xylene under conditions of anisole/xylene -1/2 to form an interlayer insulating film (4
) A desired contact hole (5) was drilled on the top. Thereafter, the resist was removed using n-butyl acetate, and heat treatment was performed at a temperature of 350° C. for 60 minutes in a nitrogen atmosphere to pattern contact holes (5) and harden the interlayer insulating film (4). (See Figure 1(C)).

N電極1i!i (3)の形成、層間絶縁膜(4)の形
成、コンタクトホール(5)の穿設・バターニングを繰
返すことにより多層電極を有する半導体装置を作成した
(第1(d)〜1(e)図参照)。
N electrode 1i! A semiconductor device having a multilayer electrode was fabricated by repeating the formation of i (3), the formation of an interlayer insulating film (4), and the drilling and patterning of contact holes (5) (1 (d) to 1 (e)). ) see figure).

えられた半導体装置について20V X  10001
1rの条件で課電を行ない層間絶縁膜(4)による腐食
の有無を調査したが腐食は認められなかった。また層間
絶縁1漠f4)の成形時のNヒロック発生の有無を調査
したがヒロックは認められなかった。さらに耐熱性を調
査するため基板状で400℃X  100Hrの高温試
験を行なったが異常は認められなかった。
About the obtained semiconductor device 20V x 10001
The presence or absence of corrosion due to the interlayer insulating film (4) was investigated by applying electricity under the condition of 1r, but no corrosion was observed. In addition, the presence or absence of N hillocks during molding of interlayer insulation 1/f4) was investigated, but no hillocks were observed. Furthermore, in order to investigate the heat resistance, a high temperature test of 400° C. x 100 hours was conducted on the substrate, but no abnormality was observed.

[発明の効果] 以上説明したように本発明によるときは、高純度、高耐
熱性のフェニルシリコーンラダーポリマを用いて層間絶
縁膜を形成したので、耐熱性にすぐれ上層の配線を形成
しても特性が劣化せず信頼性の高い半導体装置をえるこ
とができる。
[Effects of the Invention] As explained above, according to the present invention, the interlayer insulating film is formed using a high-purity, highly heat-resistant phenyl silicone ladder polymer. A highly reliable semiconductor device whose characteristics do not deteriorate can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1(a)〜1(e)図は本発明の一実施例における半
導体装置の断面図である。 (図面の主要符号) (1):半導体基板 (2):保護膜 (3);配線層 (4):層間絶縁膜 (5):コンタクトホール 代  理  人 大  岩 増  雄 第1(d)口 コンタクトホ
1(a) to 1(e) are cross-sectional views of a semiconductor device according to an embodiment of the present invention. (Main symbols in the drawing) (1): Semiconductor substrate (2): Protective film (3); Wiring layer (4): Interlayer insulating film (5): Contact hole agent Yu Iwamasu, Nihon University, 1st (d) mouth contact Ho

Claims (1)

【特許請求の範囲】[Claims] (1)少なくとも2層配線構造を有する半導体装置であ
って、層間絶縁膜が構造式( I ): ▲数式、化学式、表等があります▼( I ) (式中、nは2〜1000の整数を示す)で表わされる
末端水酸基フェニルシリコーンラダーポリマーにより形
成されてなることを特徴とする半導体装置。
(1) A semiconductor device having at least a two-layer wiring structure, in which the interlayer insulating film has a structural formula (I): ▲There are mathematical formulas, chemical formulas, tables, etc.▼(I) (In the formula, n is an integer from 2 to 1000. 1. A semiconductor device characterized in that it is formed of a phenyl silicone ladder polymer with a hydroxyl terminal group represented by the following formula.
JP9931989A 1989-04-18 1989-04-18 Semiconductor device Pending JPH02277255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9931989A JPH02277255A (en) 1989-04-18 1989-04-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9931989A JPH02277255A (en) 1989-04-18 1989-04-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02277255A true JPH02277255A (en) 1990-11-13

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP9931989A Pending JPH02277255A (en) 1989-04-18 1989-04-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02277255A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05190684A (en) * 1992-01-16 1993-07-30 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPH05326718A (en) * 1992-05-25 1993-12-10 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05190684A (en) * 1992-01-16 1993-07-30 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPH05326718A (en) * 1992-05-25 1993-12-10 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

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