JPH0227654Y2 - - Google Patents
Info
- Publication number
- JPH0227654Y2 JPH0227654Y2 JP1983051084U JP5108483U JPH0227654Y2 JP H0227654 Y2 JPH0227654 Y2 JP H0227654Y2 JP 1983051084 U JP1983051084 U JP 1983051084U JP 5108483 U JP5108483 U JP 5108483U JP H0227654 Y2 JPH0227654 Y2 JP H0227654Y2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- emitter
- signal
- base
- synchronization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 13
- 230000003321 amplification Effects 0.000 claims 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims 2
- 238000001514 detection method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
Description
【考案の詳細な説明】
産業上の利用分野
本考案は、映像信号が三角波信号のような一定
の信号が重畳されてスペクトラム拡散方式により
送信され、受信側においてその重畳された一定の
信号を除去する場合に用いられるクランプ回路に
関する。[Detailed description of the invention] Industrial application field This invention is based on a method in which a video signal is superimposed with a certain signal such as a triangular wave signal and transmitted using a spread spectrum method, and the superimposed certain signal is removed on the receiving side. This invention relates to a clamp circuit used in such cases.
背景技術とその問題点
テレビジヨン信号をSHF帯を用いて送信する
システムでは、第１図に示すように映像信号に例
えばその垂直周期TOの整数倍の周期の三角波信
号を重畳してFM変調するスペクトラム拡散方式
が用いられ、受信機において受信信号をFM復調
した後にその重畳された三角波信号を除去する
が、その場合、三角波信号の除去にはクランプ回
路が用いられる。BACKGROUND TECHNOLOGY AND PROBLEMS In a system that transmits television signals using the SHF band, as shown in Figure 1, a triangular wave signal with a period that is an integral multiple of the vertical period T O is superimposed on the video signal to perform FM modulation. A spread spectrum method is used, and after the received signal is FM demodulated in the receiver, the superimposed triangular wave signal is removed. In this case, a clamp circuit is used to remove the triangular wave signal.
第２図はこの場合に用いられる従来のクランプ
回路の一例で、クランプ用のトランジスタ１１を
有し、そのベースに電源電圧Vccを分圧して所定
のクランプ電位を与える抵抗R1及びR2が接続さ
れ、エミツタが抵抗R3を介して接地され、映像
増幅回路の出力の第１図のように三角波信号の重
畳された映像信号SIが与えられる入力端子１２が
コンデンサ１３を介してエミツタに接続され、そ
のエミツタよりバツフア増幅回路１４を介して出
力端子１５が導出され、映像信号の同期先端部が
検出されて、矢印１で示すトランジスタ１１のイ
ンピーダンスを通じたコンデンサ１３への充電
と、矢印２で示す抵抗R3を通じた放電を繰り返
しながら、直流再生がなされることにより、出力
の信号SOとして三角波信号の除去された映像信号
が得られるようにされたものである。 Figure 2 shows an example of a conventional clamp circuit used in this case, which has a clamping transistor 11, with resistors R1 and R2 connected to its base to divide the power supply voltage Vcc and provide a predetermined clamping potential. The emitter is grounded through a resistor R3 , and the input terminal 12 to which the video signal S I superimposed on the triangular wave signal is applied as shown in Figure 1, which is the output of the video amplifier circuit, is connected to the emitter through a capacitor 13. The output terminal 15 is led out from the emitter via the buffer amplifier circuit 14, the synchronized leading edge of the video signal is detected, and the capacitor 13 is charged through the impedance of the transistor 11 as shown by arrow 1, and the capacitor 13 is charged as shown by arrow 2. By performing DC regeneration while repeating discharge through the resistor R 3 shown in FIG. 3, a video signal from which the triangular wave signal has been removed can be obtained as the output signal S O.
しかしながら、この従来の回路では、第３図Ａ
に示すように、同期先端部Ｓの幅と周期が垂直帰
線期間TBの垂直同期パルスの期間TS及びその前
後の等化パルスの期間TE1，TE2とそれ以外の期
間で異なり、特に垂直同期パルスの期間TSでは
同期先端部Ｓの幅が大きくなるために、同図Ｂに
示すように、出力の信号SOの同期先端部の電位
VSが、垂直帰線期間TBの垂直同期パルスの期間
TSから垂直映像期間の初めの期間にかけて、他
の期間に対して、即ち所定のクランプ電位VCに
対して、上昇してしまう。従つて、第４図Ａに示
すように同期先端部Ｓ、ペデスタルＰ及びホワイ
トピークＷはそれぞれ一定のレベルになるべきも
のが、そうならずに、同図Ｂに示すようにそれぞ
れ垂直帰線期間TBの垂直同期パルスの期間TSか
ら垂直映像期間TVの初めの期間にかけてレベル
が高くなつてしまう。 However, in this conventional circuit, FIG.
As shown in , the width and period of the synchronization tip S are different between the vertical synchronization pulse period T S of the vertical retrace period T B and the equalization pulse periods T E1 and T E2 before and after it, and other periods. In particular, during the period T S of the vertical synchronization pulse, the width of the synchronization tip S becomes large, so as shown in Figure B, the potential of the synchronization tip of the output signal S O
V S is the period of the vertical sync pulse of the vertical blanking period T B
From T S to the beginning of the vertical video period, it increases with respect to other periods, that is, with respect to the predetermined clamp potential V C . Therefore, as shown in FIG. 4A, the synchronization tip S, pedestal P, and white peak W should each be at a constant level, but instead of being at a constant level, as shown in FIG. The level increases from the vertical synchronization pulse period T S of T B to the beginning of the vertical video period TV.
そして、このように同期部分や映像部分のレベ
ルが変化すると、低い周期性のノイズを生じた
り、受信レベルが低下した場合に垂直帰線期間
TBにノイズがあると、同期分離回路での同期分
離がうまくなされなくなつて同期はずれを起こし
やすくなつたり、垂直帰線期間TBに文字放送な
どのための情報がある場合にはその情報に悪影響
を与えたり、色むらを生じるなどの不都合があ
る。 If the level of the synchronization part or video part changes in this way, low periodic noise may occur, or if the reception level drops, the vertical retrace period may change.
If there is noise in T B , the synchronization separation circuit will not be able to separate the synchronization properly, making synchronization more likely to occur, or if there is information for teletext etc. in the vertical retrace period T B , the information There are inconveniences such as having an adverse effect on the color and causing color unevenness.
また、この従来の回路では、三角波信号の重畳
された入力の映像信号SIの同期先端部の電位がク
ランプ電位に対して低いときにはクランプ効果が
よいが、クランプ電位に対して高いときにはクラ
ンプ効果が悪く、そのため重畳された三角波信号
が充分に除去されず、出力の映像信号SOに三角波
成分が残留してしまう。 In addition, in this conventional circuit, the clamping effect is good when the potential at the synchronization tip of the input video signal S I on which the triangular wave signal is superimposed is lower than the clamping potential, but the clamping effect is poor when it is higher than the clamping potential. Unfortunately, the superimposed triangular wave signal is not removed sufficiently, and the triangular wave component remains in the output video signal SO .
考案の目的
本考案は、以上の点にかんがみ、垂直帰線期間
やその直後の期間で映像信号の各部のレベルが変
化することがないとともに、重畳された三角波信
号のような一定の信号を充分に除去することので
きる、新規なクランプ回路を提案するものであ
る。Purpose of the invention In view of the above points, the present invention prevents the level of each part of the video signal from changing during the vertical retrace period or the period immediately after it, and allows a constant signal such as a superimposed triangular wave signal to be This paper proposes a new clamp circuit that can be eliminated.
考案の概要
本考案では、クランプ用のトランジスタのコレ
クタに同期先端部の波形を検出する回路を接続
し、その検出信号を正相増幅回路を介してクラン
プ用のトランジスタのベースに帰還させる。Summary of the invention In the invention, a circuit for detecting the waveform of the synchronization tip is connected to the collector of the clamping transistor, and the detection signal is fed back to the base of the clamping transistor via a positive-phase amplifier circuit.
実施例
第５図は本考案のクランプ回路の一例で、クラ
ンプ用のトランジスタ１１を有し、そのベースに
抵抗R1及びR2が接続され、エミツタが抵抗R3を
介して接地され、入力端子１２がコンデンサ１３
を介してエミツタに接続され、そのエミツタより
バツフア増幅回路１４を介して出力端子１５が導
出される点は、第１図の従来の回路と同じであ
る。Embodiment FIG. 5 shows an example of the clamp circuit of the present invention, which has a clamping transistor 11, whose base is connected to resistors R1 and R2 , whose emitter is grounded via resistor R3 , and whose input terminal is 12 is the capacitor 13
It is the same as the conventional circuit shown in FIG. 1 in that the output terminal 15 is connected to the emitter via the emitter and the output terminal 15 is led out from the emitter via the buffer amplifier circuit 14.
本考案では、トランジスタ１１のコレクタに同
期先端部の波形を検出する検出回路１６が接続さ
れるとともに、その検出信号を正相増幅回路１７
を介してトランジスタ１１のベースに供給する帰
還路１８が設けられる。具体的には、検出回路１
６は抵抗R4とこれに並列に接続されたコンデン
サC4からなり、抵抗R4によつて前述の同期先端
部の電位の変化分ないし重畳された三角波信号の
残留成分、即ち同期先端部の電位の所定のクラン
プ電位に対する誤差分が検出され、コンデンサ
C4によつて高域成分が除去されて適当に平滑さ
れることにより、検出回路１６の出力の信号とし
て同期先端部の包絡線検波信号、即ち同期先端部
の波形の検出信号が得られる。帰還路１８は抵抗
R5と正相増幅回路１７とコンデンサC5からなり、
正相増幅回路１７はトランジスタ１７ａに対して
抵抗R6，R7，R8及びコンデンサC7，C8が接続さ
れたベース接地のトランジスタ増幅回路を構成
し、帰還ループのループ・ゲインが充分大きくさ
れる。 In the present invention, a detection circuit 16 is connected to the collector of the transistor 11 to detect the waveform at the tip of the synchronization, and the detection signal is transmitted to the positive phase amplifier circuit 17.
A feedback path 18 is provided which supplies the base of the transistor 11 via the . Specifically, the detection circuit 1
Reference numeral 6 consists of a resistor R4 and a capacitor C4 connected in parallel with the resistor R4, and the resistor R4 absorbs the aforementioned change in potential at the sync tip or the residual component of the superimposed triangular wave signal, that is, the sync tip's potential change. The error in potential with respect to a predetermined clamp potential is detected and the capacitor
By removing high-frequency components and appropriately smoothing by C4 , an envelope detection signal of the synchronization leading edge, that is, a detection signal of the waveform of the synchronization leading edge is obtained as the output signal of the detection circuit 16. The return path 18 is a resistance
Consisting of R5 , positive phase amplifier circuit 17, and capacitor C5 ,
The positive phase amplifier circuit 17 constitutes a base-grounded transistor amplifier circuit in which resistors R 6 , R 7 , R 8 and capacitors C 7 , C 8 are connected to the transistor 17a, and the loop gain of the feedback loop is sufficiently large. be done.
従つて、正相増幅回路１７の出力側、即ちトラ
ンジスタ１７ａのコレクタをコンデンサC5を介
してトランジスタ１１のベースに接続しない場
合、トランジスタ１１のエミツタ電位は第６図Ａ
に示すように垂直帰線期間TBとその前後の期間
において同期先端部Ｓ、ペデスタルＰ及びホワイ
トピークＷでそれぞれ実線のようになり、トラン
ジスタ１１のベース電位は同図Ｂのようになり、
トランジスタ１１のコレクタの信号波形、即ち検
出回路１６の出力の信号波形は同図Ｃのようにな
り、トランジスタ１７ａのコレクタの信号波形、
即ち正相増幅回路１７の出力の信号波形は同図Ｄ
のようになる。そして、正相増幅回路１７の出力
側、即ちトランジスタ１７ａのコレクタがコンデ
ンサC5を介してトランジスタ１１のベースに接
続されて、正相増幅回路１７の出力の信号がトラ
ンジスタ１１のベースに供給されることによつ
て、トランジスタ１１のエミツタ電位は第６図Ｅ
に示すように同期先端部Ｓ、ペデスタルＰ及びホ
ワイトピークＷでそれぞれほとんど一定になつ
て、第２図の従来の回路で生じる垂直帰線期間
TBやその直後の期間でのレベル変化が打ち消さ
れるとともに、トランジスタ１１のベース電位が
通常のクランプ電位よりも低くなつてクランプ効
果が改善され、重畳された三角波信号も充分に除
去されるようになる。 Therefore, when the output side of the positive phase amplifier circuit 17, that is, the collector of the transistor 17a is not connected to the base of the transistor 11 via the capacitor C5 , the emitter potential of the transistor 11 is as shown in FIG. 6A.
As shown in the figure, during the vertical retrace period T B and the period before and after it, the synchronization tip S, pedestal P, and white peak W are respectively shown as solid lines, and the base potential of the transistor 11 is as shown in the figure B.
The signal waveform at the collector of the transistor 11, that is, the signal waveform at the output of the detection circuit 16 is as shown in FIG.
That is, the signal waveform of the output of the positive phase amplifier circuit 17 is shown in FIG.
become that way. The output side of the positive phase amplifier circuit 17, that is, the collector of the transistor 17a, is connected to the base of the transistor 11 via the capacitor C5 , and the output signal of the positive phase amplifier circuit 17 is supplied to the base of the transistor 11. Particularly, the emitter potential of the transistor 11 is as shown in FIG.
As shown in FIG. 2, the synchronization tip S, pedestal P, and white peak W are almost constant, and the vertical retrace period that occurs in the conventional circuit shown in FIG.
Level changes during T B and the period immediately after it are canceled out, and the base potential of transistor 11 becomes lower than the normal clamp potential, improving the clamping effect, and the superimposed triangular wave signal is also sufficiently removed. Become.
考案の効果
本考案によれば、クランプ用のトランジスタの
コレクタに同期先端部の波形を検出する回路を接
続し、その検出信号を正相増幅回路を介してクラ
ンプ用のトランジスタのベースに帰還させるよう
にしたので、従来のように垂直帰線期間やその直
後の期間で映像信号の各部のレベルが変化するこ
とがなく、同期はずれを起こしやすくなつたり、
色むらを生じるなどの不都合がなくなるととも
に、重畳された三角波信号のような一定の信号も
充分に除去されるようになる。また、付加する素
子の数も少なくて済み、構成も簡単になる。Effects of the invention According to the invention, a circuit for detecting the waveform of the synchronization tip is connected to the collector of the clamping transistor, and the detection signal is fed back to the base of the clamping transistor via a positive-phase amplifier circuit. As a result, the level of each part of the video signal does not change during the vertical retrace period or the period immediately after it, unlike in the past, which makes it easy to lose synchronization.
Inconveniences such as color unevenness are eliminated, and certain signals such as superimposed triangular wave signals are also sufficiently removed. Further, the number of elements to be added can be reduced, and the configuration can be simplified.
第１図はクランプ回路の入力の映像信号の一例
を示す波形図、第２図は従来のクランプ回路の一
例を示す接続図、第３図及び第４図はその動作の
説明のための波形図、第５図は本考案のクランプ
回路の一例を示す接続図、第６図はその動作の説
明のための波形図である。
図中、１１はクランプ用のトランジスタ、１２
は入力端子、１３はコンデンサ、１４はバツフア
増幅回路、１５は出力端子、１６は検出回路、１
７は正相増幅回路、１８は帰還路である。
Fig. 1 is a waveform diagram showing an example of a video signal input to a clamp circuit, Fig. 2 is a connection diagram showing an example of a conventional clamp circuit, and Figs. 3 and 4 are waveform diagrams for explaining its operation. , FIG. 5 is a connection diagram showing an example of the clamp circuit of the present invention, and FIG. 6 is a waveform diagram for explaining its operation. In the figure, 11 is a clamp transistor, 12
is an input terminal, 13 is a capacitor, 14 is a buffer amplifier circuit, 15 is an output terminal, 16 is a detection circuit, 1
7 is a positive phase amplifier circuit, and 18 is a feedback path.
Claims (1)
に供給し、該ベースに所定のクランプ電位を与え
る素子と、 上記トランジスタのエミツタと接地電位点との
間に接続された第１の抵抗と、 上記トランジスタのエミツタと上記第１の抵抗
とに接続され、映像信号が入力される入力端子
と、 上記入力端子と上記トランジスタのエミツタと
の間に接続された第１のコンデンサと、 上記トランジスタのコレクタと電源との間に接
続された第２の抵抗と、 該第２の抵抗に対して並列に接続された第２の
コンデンサと、 上記トランジスタのコレクタから得られる信号
を増幅して上記トランジスタのベースに帰還する
正相増幅部と、 上記トランジスタのエミツタと出力端子との間
に接続されたバツフア増幅部と、 からなるクランプ回路。[Scope of Claim for Utility Model Registration] A clamping transistor, an element that divides the power supply voltage and supplies it to the base of the transistor to give a predetermined clamping potential to the base, and a connection between the emitter of the transistor and a ground potential point. an input terminal connected to the emitter of the transistor and the first resistor and into which a video signal is input; and an input terminal connected between the input terminal and the emitter of the transistor. a first capacitor connected between the collector of the transistor and the power supply; a second capacitor connected in parallel to the second resistor; A clamp circuit comprising: a positive phase amplification section that amplifies the obtained signal and feeds it back to the base of the transistor; and a buffer amplification section connected between the emitter of the transistor and the output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5108483U JPS59157363U (en) | 1983-04-06 | 1983-04-06 | clamp circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5108483U JPS59157363U (en) | 1983-04-06 | 1983-04-06 | clamp circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59157363U JPS59157363U (en) | 1984-10-22 |
| JPH0227654Y2 true JPH0227654Y2 (en) | 1990-07-25 |
Family
ID=30181511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5108483U Granted JPS59157363U (en) | 1983-04-06 | 1983-04-06 | clamp circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59157363U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4644198A (en) * | 1984-10-31 | 1987-02-17 | Rca Corporation | Signal clamp |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5720070A (en) * | 1980-07-11 | 1982-02-02 | Toshiba Corp | Direct-current regenerating circuit for television signal |
-
1983
- 1983-04-06 JP JP5108483U patent/JPS59157363U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5720070A (en) * | 1980-07-11 | 1982-02-02 | Toshiba Corp | Direct-current regenerating circuit for television signal |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59157363U (en) | 1984-10-22 |
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