JPH02276398A - Apparatus and method for electronic cross-connection - Google Patents

Abstract

PURPOSE: To connect a communication line from a center station electronically to a specific subscriber line by providing a controller means that simultaneously generates a couple of unique command signals and a command signal bus and sending a digital information signal therethrough. CONSTITUTION: When a new subscriber is subscribed to a central station 10, for example, a central monitor installation 42 sends a signal to a communication adaptor card 66 through an electric communication information network 46. Then the card is connected to a memory 130 of an MCU 1 under its management via a management monitor terminal. The operator revises indirectly port assignment stored in the memory 130 and adds a special port and a special central station port is assigned to an assignment program. Thus, it is not required for the operator at a site to visit a digital cross connector apart remotely to connect a special subscriber electric communication line to a special central station electric communication line.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an intelligent digital electronic cross-connector device for remote deployment and management of a local telephone communication network. The present invention further relates to a method for electronic interconnection of telephone transmission systems by transmitting digital information signals substantially independent of signal processing.

[Technical background of the invention] The telephone tree carries signals between the central office and the subscribers.

The information signals include voice and data information signals originating from or transmitted to the subscriber as well as monitoring requests.

Communication lines typically extend from a central office to a feeder wiring interface (FDI), often referred to as a cross-connect device. In any prior art system, this cross-connect system requires a metal connection from the central office to the wiring medium that extends from the cross-connect system to the subscribers. At the request of a subscriber or by order from the central office, a craftsman/technician is sent to the cross-connect equipment, which is typically located far away from the central office, to physically connect the hard wires of the equipment. Connection conversion of the cross-connect device is performed by changing the cross-connect device. Therefore, replacing a current version of a cross-connect device is a relatively labor-intensive task.

U.S. Patent No. 4.520 of Fields et al.
, 234 discloses a remote cable switching system that utilizes a switching matrix having a logical matrix and a record of the current matrix state of the switching subsystem. A switching matrix module is a plurality of relays. No. 4,539,564 to Smithson et al. discloses a central matrix of a number of solid state analog switches. U.S. patent cylinder 4°525.60 of Wever et al.
No. 5 also discloses a system that uses relays to access telephone lines.

Joel Jr. (Joel) US Patent No. 3.562,
No. 435 discloses a system having an automatic main wiring frame. The system includes a permutation storage and network control line for controlling a switched network placed between the telephone lines, where relays are used.

[Technical Problem of the Invention] It is an object of the present invention to provide a highly functional digital electronic cross-connect device capable of electronically connecting a communication line from a central office to a particular subscriber line.

It is also an object of the present invention to provide a cross-connect device that maps ports connected to a central office to ports connected to subscribers in a one-to-one relationship.

It is a further object of the present invention to provide an electronic cross-connect device in which the one-to-one mapping occurs in software according to a program, and in which this program map can be changed remotely from the device.

It is a further object of the present invention to provide a highly functional digital switching matrix that is remotely managed and to some extent remotely maintained and provides analog and digital communications to the external plant environment.

It is a further object of the present invention to provide an electronic cross-connect device for communicating with remote facilities via a telecommunications link.

It is also an object of the invention to provide a cross-connect device that is completely transparent not only to the central office but also to the subscribers, by eliminating a large number of plug-ins.

Another object of the present invention is to provide an electronic cross-connect device in which the connections are made electronically rather than by hard wires.

SUMMARY OF THE INVENTION In one embodiment of the invention, an electronic cross-connect device provides a communication path for information signals between first and second telecommunications lines. Each line is coupled to at least one port on the interface module. Lines extending to the central office are coupled to an information network interface module, and lines extending to the subscribers are coupled to a subscriber interface module.

Each module has multiple ports.

Each module is also coupled to two 8-bit unidirectional buses that provide for the transfer of information signals between modules. In the interface module, information from the connected telecommunications line is converted into parallel formatted digital signals. When signal information is first captured at a port, the interface module sends a signal to the bus interface module, which then notifies the master controller. The master controller's memory contains subscriber port assignments and central office port assignments for all operational ports. According to the predetermined program, the receiving port address and the receiving port address are loaded into a dedicated speed VCAS (Voice Channel Address Supervision) memory. This address is strobed into each interface. Each interface has a latch buffer combination connected to a unidirectional bus that sends information from the receive port to the accept port when the port is strobed, and from the accept port to the receive port. This allows for two-way transfer of information.

VCAS memory maintains the port address until the communication between the two telecommunications lines is terminated. Then, the main controller removes the port and module address from the CAS memory. The interface module may also be arranged to connect to a D31 line and the time slot demultiplexing and demultiplexing 24 information carrying channels on that line; relates to a method of transferring information between one or more ports.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to electronic cross-connect devices and methods of providing communication links or paths for telecommunications lines.

FIG. 1 is an illustration of a prior art telephone system. Central office 10 has a plurality of telecommunications lines extending therefrom. Telephone line group 12 leads to central office terminal 14 .

This central office terminal 14 typically selects a block of information signals from one communications channel and transfers that channel to the other two.
Information-carrying information signals are multiplexed by time multiplexing on three channels. In general, 24 channels are multiplexed together onto a pair of lines.
``Telecommunications line'' usually refers to a pair of electrical wires that carry information signals; however, ``telecommunications line'' refers to a pair of electrical wires that carries single or multiplexed channels or other media such as fiber optics or radionic cables. Also referring to the wire method, the central office terminal 14 is connected to a digital switch 18 (DSX) via a line 16, and this DSX 18
It is finally controlled by a command signal issued from the central station 10. DSX 18 can only switch a single 24-channel multiplexed signal from one output (or input) line to another output (or input) line in line group 20.

These 24 channels are time multiplexed together in a pulse code modulation (PCM) bit stream that moves at approximately 1.5 Mbit/s, but the DSX18 can demultiplex these signals and The output of DSX 18 is applied to remote terminal 22, where the channels cannot be rerouted to a single telecommunications line. Remote terminal 22 demultiplexes the PCM bit stream and transmits the demultiplexed signal to telecommunications line 20.
6 lines 20 in addition to the feeder wiring interface (
FDI) 24. Feeder wiring interface 24 is often referred to as a cross-connect device.

This connects the line coming out from the central office 10 to subscriber Sl,
32 or S3, typically by a hardwire, metal-to-metal connection.

The central office 10 may include a second line 26, which is a discrete telephone line connected directly to the FDI 24; likewise, this line 26 is typically hardwired to one of the subscribers 81-S3. Connected.

Another type of telecommunications line extending from the central office 10 is a local or data communication line 28 (eg, line D31).
, which carry digitally compressed signals, these communication lines are typically extended to a knowledgeable subscriber, such as the industrial subscriber 83 shown schematically. 6 Lines 28 may be private networks, leased lines, or private lines. This is a private line.

FIG. 2 is a block diagram illustrating a telecommunications system using the electronic cross-connect device of the present invention.

Clarity numbers referring to items similar to those in FIG. 1 are the same as in FIG.

Channel bank 30 is substantially similar to central office terminal 14 of FIG. Generally, line 16 in FIG. 1 corresponds to digital line carrier 32 in FIG. That is, the digital line carrier (DLC>32) directs the multiplexed PCM bit stream from the central office 10 to the intelligent digital electronic cross-connect device 34 (XCON) of the present invention. (DLIM) 36. The discrete telephone line group 26 is connected to the communication network interface module (NIM) 38 of the connected to,
X CON 34 is coupled to a central monitoring facility 42 via output/input devices (Ilo>44 and telecommunications links 46. On the subscriber side of the telephone system, subscribers S4 and S5 are connected to subscriber interface modules (
SIM) 48 and subscribers S6 and 37
is connected to the subscriber interface module (SIMD) 5 (l port of the has been done.

FIG. 3 is a block diagram illustrating the electronic cross-connect device, designated as XC0N 34 in FIG. The cross-connect device 34 includes the following main components: a network interface module (e.g., NIM60), a subscriber interface module (e.g., 31M62), a busbar interface module 64 (BIM), a main controller 1 and 2 (MCU
1, MCU2), VCAS memory 116, and communication adapter card 66. In this embodiment, there are 38 N1M cards or modules and 76 31M cards or modules. The NIM and SIM are all connected together via unidirectional 8-bit data records 68 and 70.

These busbars 68,70 are on separate backplanes occupying individual rack levels. Line 68 transfers the digitally formatted parallel signal from the SIM to the NIM.

Bus 70 carries similar signals from the NIM to the SIM.

Each NIM, e.g. N1M60, has a central office 10 (Figure 2).
It is connected to 24 pairs of telecommunications lines originating from the

The six pairs of telecommunications lines are sometimes referred to herein as a single telecommunications line because information is sent to the NIM through the pair. There are approximately 900 lines entering electronic cross-connect device 34 from central office 10.

At the other end, i.e. the subscriber end, each SIM,
For example, SIM 62 has 24 pairs of lines connected to it to the subscriber. There are approximately 1,800 lines serving subscribers.

Each wire pair is connected to one port of one of the SIMs. Therefore, the cross-connect device 34 has approximately 2
, 700 ports.

SIM and NIM have unidirectional buses 68 and 70
exchange information signals with each other via

Typically, the port address is connected to the SIM and NI via voice channel address supervision (VCAS) buses 72 and 76.
A communication link is opened between the SIM and the NIM through a unidirectional bus. A particular card or module is selected based on the signal on the 8-bit module selection motherboard #, 74. At the subscriber interface, port addresses are selected by VCASs bus 76 and subscriber module select bus 78.

Therefore, 8-bit bus lines 74 and 78 select a card or module, and VCASn and VCASsi lines 72 and 76 select a particular port address. Typically, a latch, buffer combination is opened on an N1M card, and a similar A latch/buffer combination is opened on the SIM card to simultaneously transfer data from a particular NIM and SIM to the appropriate direction on buses 68 and 70.

At the beginning of the communication period, the type of signals received at each port are decoded according to a predetermined program and sent via bidirectional 8-bit signal data bus 80 to busbar interface module (BIM) 64. NIM and STM are each polled via signal grant line 88;
Download signal data to bus 80. In one embodiment, there are thirty signal grant lines 88. Ten of those lines lead to specific racks that hold NIMS and SIMS.

BIM 64 activates a particular NIM or SIM via line 88 and monitors changes in conditions on signal bus 80 to determine whether the SIM or NIM should be serviced. That is, it transfers data to a specific module.

The BIM 64 includes a signal bus interface 90 and a rack and card (R and C) signal bus selector 92. For control of information on unidirectional buses 68 and 70, VCAS memory 116,
VCAS port selection logic 94, NIM module selection logic 96 and subscriber module selection logic 9
8 is on the BIM64 card, but is usually far away.

BIM64 typically provides a translation function that translates the virtual address of each telephone line interface module, as seen by a master control unit (MCU), onto a particular rack and plane. B'IM64 is a microprocessor
110 and various other elements described below. Microprocessor 110 is coupled to main t'a 112 via backplane logic 114, as is VCAS memory 116.

VCAS memory 116 and its associated controls operate normally. VCAS memory - 116 has two VCs
It is divided into AS tables, one of which is active for 125 microseconds (dispensing processing cycle). Call processing means stoving the port-to-port map from the active VCAS table. The VCAS table contains NIM addresses and port addresses for active ports, i.e. information-carrying ports, as well as SIM addresses and ports, such that communication links are opened periodically between two designated ports via buses 68 and 70. holds the address. A separate timed circuit associated with VCAS memory 116 stoves the port-to-port map to SIM and NIM via busbars 76 and 78. The static VCAS table is updated during that 125 microsecond period while new or old maps are reclaimed by the MCU. Therefore, the MCU and BIM 64 operate on the VCASC-S port stove virtually regardless of time.

Main control units (MCUs) 1 and 2 provide diagnostic capabilities to the digital cross-connect device 34, maintain a database with all port-to-port assignments, and maintain a VCAS memory 1
16 to change the port-to-port map and monitor the information signal exchange between the SIM, NIM, and DLIM. Two main control units for fail-safe redundancy! There is 1.2. Each MCU 1.2 is capable of controlling the system due to redundancy in the operating and application software and line assignment (port-to-port) database. The spare MCU is used for BIM in case the active MCU fails.
has the ability to stop active MC1J (set by default) after consultation with MC1J. In this situation, a high-priority error message is sent to the retention management terminal (
MAT).

The MCU is a MVME-135 board purchased from Motorola.

The on-board microprocessor 120 is a 68020 microprocessor purchased from Motorola, which is a 32-bit device. The MCUl includes a location monitor that performs two jobs for the device:
It monitors the bus for error messages and provides bus arbitration. location monitor 12
2 determines where the BIM and MCU will be located,
It also determines which MCtJ can access the main bus 122.

This implementation of the invention designates a single MCU as primary when configuring the device, and the other MCU is placed for redundancy. Further, other ellipse configurations such as time division using MC1J may be used.

MCUI, 2 also includes interrupt handler VME 124. Interrupt handler 124 monitors main bus 112 via backplane interface logic 12G. Location monitor 122 also handles backplane interface logic 126, as well as MCU
1.

2 also includes a t-line requester 128. Request device 128
generally requires access to a portion of main bus 112.

Main bus 112 is a 32-bit bus. Data generally passes through interrupt handler 124 . Backgrain interface logic 126 typically includes signals on main bus 1.
12 or from the main bus 112. MCUI, 2 includes memory 130 with diagnostic, monitoring and port assignment programs.

MCUI and 2 are connected to communication adapter card 66 via busbar 112. Additional communication links are provided for each M
The R3-232 communications adapter card 66 facilitated by the R3-232 communications device 134 of the CU 1.2 includes an
O line aW1 is included. Communication adapter 66 is serviced by MCUI,2 via an interrupt. The communication link (X,25 protocol) to the MAT is via a dedicated line in some implementations. This communication link and line a
Horizontals are well known in the art.

In operation, the digital cross-connect device works as follows: When the subscriber lifts up the telephone handset, an off-hook signal is detected on one of the ports (Plo) of e.g. S I N62 (562). . 31N62
is the signal bus 80 when polled with 81M64.
This is a "mailbox" configuration, producing the coded data signal as obtained above. Periodically (125 microsecond windows), the BI
M selects the NIM and SI by selecting rack and card locations from signal bus selector 92.
Poll each M. When polled, 3
A 1N62 buffer/latch provides the data signal on signal bus 80. The 81M64 senses that data signals and microprocessor-110 state changes increase the interrupts that the MCUI senses via the main bus 112, for example. Since there are as many as 114 interface modules, the 0 interrupts required by the BIM are detected by the interrupt handler 124, and then the MCUI
A microprocessor 120 executes a program in memory 130 to obtain signal data from the 81M64 and analyzes that data in accordance with another program to detect and decode "off-hook" signals and to detect and decode "off-hook" signals for that particular SIM/port. After obtaining the port-to-port map from the database in the memory 130 for the card and port address S6
2. Load the cards and port addresses of Plo and the appropriate corresponding ports leading to the central office, eg, N60, P23, into VCAS memory 116. SIM port 362, Plo is mapped to NIM port N60, P23.

S62, Plo, N60, P23 are placed in the static VCAS table in VCAs memory 116.

At some predetermined time (every 125 microseconds), that particular table becomes active and all addresses of the mapped ports are stoved to all SIMs, NIMs, and DLIMs. All ports that are active, ie, capable and ready to carry information, are listed in the table. The port address and module selection signals are provided by the V CA S port selector 94,
Various NIM and SI via N1M module selector 96 and SIM module selector 98
Sent to M. As such, VCASsffl line 76 and module select bus 78 carry signals specifying S62 and Plo, and VCASn bus 72 and module select bus 76 carry signals specifying N60 and P23. The latch buffer subsystems of the 31N62 and N1M60 are opened simultaneously and the digitally encoded audio signal is routed from the 31N62 to the unidirectional bus 68 to the N1M6.
Sent to 0. N1M 60 then rearranges its parallel formatted digital signals and provides a simulated off-hook signal to port 23 and the telecommunications line connected to central office 10. Central office 10 then responds to the off-hook signal with a tone.

This beep indicates loop closure. The information signal may be a tone signal. In addition, 10 other information signals between the subscriber and the central office are routed to the digital cross-connect device 3 by ports that are stoved every 125 microseconds.
4 is sent in two directions. V of VCAS memory 116
As long as the CAS table is stoved and the ports are active, the maps between S62, pio and N60, P23 are continuously sent to the interface module.
Such other signals, such as dialing codes, are sent as well.

Communication between central office 10 and the subscriber is bidirectional because the buffer and latch subsystems of N1M60 and 31N62 are opened simultaneously and information or data is transferred to buses 68 and 70 in an It-directed manner. When a hang-up signal etc. from a subscriber is input, the SIM 62 changes the signal state on the signal data bus 80, and the signal becomes 8.
It is polled at 1M64 and finally sent to the MCU. The MCU then reads map 3 from the VCAS memory 116.
62, Plo, N60, P23 are removed. Thereafter, no further communications link exists between central office 10 and the subscriber until an off-hook signal is detected or an equipment test program is run.

To add a new subscriber to central office 10, central monitoring facility 42 (FIG. 2) sends a signal through telecommunications information network 46 to communications adapter card 66. The MAT is connected to the memory 130 of the microprocessor-1, particularly the program residing in the memory on the MVME-135 card, namely the MCUI. The operator can indirectly modify the port assignments stored in memory 130, add special subscribers, ie, special ports, and assign special central office ports to the assignment program. The next time the new subscriber goes off-hook, the operations described above occur and a new port-to-port map is loaded into VCAS memory 116. Thus, the electronic cross-connect system 34 does not require a field operator to travel to a remote digital cross-connect system to hardwire special subscriber telecommunications lines to special central office telecommunications lines.

FIG. 4 illustrates a typical NIM in a block diagram. There is little difference between the NIM and SIM described here; the digital line interface module (
DLIM) 36, information network interface module 3
8, subscriber interface module 48, subscriber interface module-digital 50, and digital line interface 52. These modules do not differ much because the telecommunications information signals they receive are formatted according to general industry wide standards; therefore, they currently require The main problem solved by the electronic cross-connect device of the present invention, for which commercially available hardware and software can be used, is its ability to increase the capacity and power that can be increased by the dual unidirectional bus structure. Dynamic call processing capability.

Some prior art systems utilize switching matrices that store incoming information signals and then read them out to special ports at certain time slots. However, said devices are not able to transfer information fast enough, and telecommunications links through cross-connect devices are
Rather than mapping one port to a second port, 24 channels or subscriber ports are mapped to a central office port by multiplexing the 24 channels and providing the multiplexing information to the network interface port leading to the central office. Was. In order for the central office to change port assignments, all 24 subscribers or 24 channels had to be converted to different lines extending to the central office.

Additionally, prior art devices were unable to monitor the information signal to determine if a monitoring request was within an award number without removing the information signal from the exchange matrix.

The present invention does not utilize switched matrix memory, but instead utilizes two unidirectional 8-bit buses with NIM and SIM dual baud 1-RAM at either end; A dual photoRAM 5 with a memory card is used to simultaneously transfer data between active modules.

FIG. 4A shows one embodiment of an interface module. For example, a telephone line 210, including ring and tip lines, is a subscriber loose interface line (S L
IC>212. 5LIC212
is connected to the CODE C214 which is a COG/decoder, 5LIC212 is also connected to the buffer 21
This buffer 213 is also connected to the 32-bit bus. In one embodiment, eight 5LICs or one buffer are connected. 5LIC
Both C0DEC212 and CODEC214 are well known in the art. C0DEC 214 receives the FSYNCO signal and the clock (CLK) signal. The tarok signal is generated by a logic cell array (LCA) which will be described later. C0DE
C214 and a total of 24 C0DECs in this embodiment.
Other CODECs such as n have two busbars, PCM1
n and PCMout. The PCM1n bus sends modulated pulse code (PGM) data to the CODEC. The PCMout bus transfers the series modulated pulse code from the CODEC. 5LIC212 receives and COD
The information decoded by the EC 214 is provided to a shift register (SR) 216 via the PCMout bus.

Register 216 converts serial data to parallel data;
Convert parallel data to serial data. This latter data is sent to the CODEC through the PCM1n bus.

The output of the shift register is an 8-bit parallel formatted digital word that is applied to an octal tristate latch with two latches and a through-bus connector. This latch is illustrated in the schematic diagram of FIG. 5, and includes latches A and B, and transceiver-to-bus connection 220, of which only one of the two latches is used here. . At a certain point in time, the information on the bus 222 is latched into the latch A, and immediately after that, the information on the 8-bit bus 224 is loaded via the controller C without affecting the information on the latch A. 218. The information in latch A can then be launched onto bus 224 on the appropriate command signal. Tri-state latch 218 is then activated, causing 5R216 and P
Parallel formatted information signals from CM0ut can be transmitted to the microprocessor-drive module, while parallel formatted signals from the processor to 5R216 and PCM1n can be stored in latch A. A typical PCMn signal is ultimately sent to COD E C 214.

The microprocessor 238 periodically (every 125 microseconds) sends each 5 LIC via the buffer 213.
poll. A flag occurs if a 5LIC or off-hook signal is detected. microprocessor
recognizes the flag and connects 5LIC and C0DEC
A timing sequence is written into logic cell array (LCA) 232 to retrieve information from.

Figure 6 illustrates a timing diagram for this operation, bits 8.1.2.3.4.5.6.7.8 and 1
The clock pulses are also shown in the timing diagram. Frame sync pulses are generated at the LCA and sent from the LCA 232 to the particular CODEC in question. This frame sync pulse is unique to that particular CODEC in a given timeslot. Generally, a frame synchronization signal is provided to each CODEC on a separate line. For C0DEC214, the synchronization pulse is FS
I am YNCO. Therefore, the frame synchronization pulse is C
0DEC, and the information from that C0DEC must be sent to the PCM out bus and then to the shift register 216 in the predetermined time slot; in fact, since the information is serial, the shift register converts the serial data into parallel data. It operates to convert into.

At time t1, the complement of the board acknowledge signal BDTACK is low. The BDTACK signal is the inverse of a portion of signal CLK4. At the same time, the load count LD/CNT clock is increased by the CLK4 signal. As soon as tl passes, the line that generates the LD/CNT clock, that is, L
CA 232 switches to track the complement of the main tally signal, which is not a clock. Therefore, LD/C
The NT clock signal falls and goes low at time t2.9 After time t2, the LD/CNT clock rises due to the rising edge of the non-talok signal. At that time, the previous C0D
The last bit of the EC PCM1n signal is latched into the shift register 216 from latch A of the tristate latch 218.

When BDTACK starts to rise at time t3, P CM
Information from the shift register to out is latch 218
transfer bus 220 into the microprocessor memory. At the same time, the multiplexing switch now
D/CNT is switched for the line generating LD/CNT such that it follows CLK4. Thus, time t4
Then, LD/CNT decreases. LD/CNT after t4
At the falling end of the current P CM from latch 218 (latch A therein) and from the microprocessor
in data is latched into a shift register. In other words, the P CM in data is transferred from the microprocessor to latch A (FIG. 5), and then the shift register contents are changed to match latch A at the falling end of LD/CNT at time t4. After time t4, the information in shift register 216 is serially sent to CODE C 214 via PCM1n. At the same time, C0DF.

C214 shifts PCMout data to shift register 2.
At time t5, clock count 1 is high, but the first section of P CM in bit 1 indicates that the P CM out signal is in latch A (latch 218).
) may be invalid because it was latched into shift register 216 some time ago, so PCM1
The n bit 1 is determined to be valid when the non-clock signal starts rising high at time t6 or when it is high at t7.

At that point, P CM from shift register 216
in is shifted out to CODE C 214 as the PCM0IIt bit is shifted into its shift register, and the signaling continues iteratively as shown.

Latch 218 is connected to a 32-bit internal bus 230. In particular, the top seven data pits used in this 32-bit bus 230 are connected to the latch 218. Latch 218 receives latch control signals and a logic cell array (
It is controlled by a permission signal from LCA) 232.

LCA 232 interrupts the microprocessor of each active CODEC, PCMout parallel forma parallel bordered data random access memory (RAM) 23
6 is written.

The interrupt vector tells the microprocessor where to store information in RAM.

The RAM addresses are the port addresses of the SL IC, CODEC, and telephone line. Therefore, COD
The port intelligence information obtained by the E C 214 is written directly to the dual port RAM 236 on the read/write (R/W> signal from the microprocessor 238).

The dual port RAM 236 is configured such that even addresses are written with data (EW) on the bus 230 side, and data at odd addresses is read from the RAM (OR). Dual port RAM 23
On the other side of 6 is an 8-bit busbar 238. Data is read out from the RAM from even addresses (E
R) is read into buffer 240.

Information is sent to bus 238 at odd addresses from latch 242.
from the dual port RAM 236.

Buffer 240 is connected to an 8-bit unidirectional bus through the other SIMs and NIMs. latch 24
2 is attached to a busbar 70 that extends from the other SIMs and NIMs to the particular interface module in question.

The base address of the port in question 0 described below for the VCAS operating cycle is the appropriate VCASt line (VC
ASn72 and VcAS376) and are sent to the buffer 224. High class address is RAM 236
The address location is sequential or related to the unique port address of the interface module. Signal VADDR assists in the transfer. This implementation B
The company uses five lines on the VCASt line. The module selection signal is sent to comparator 246 through one of the appropriate buses (74, 76). When the port address and module selection address are recognized simultaneously via comparator 246, buffers 240, 244 and latch 242
It is fully functionalized via a control line represented by line 250. The stove control signal T/R also controls the VCAS cycle and is controlled by the logic associated with the VCAS memory.
Sent to the CAS-9 line. Logic selector 252 is connected to the high end data segment of 32-bit internal bus 230. Logic selection device 252 also receives command VADDR generated by I10 device 254. These signals,
Further controlled by the port address and module select signals, the buffer, latch combination 240
, 242 are functionalized. Stove signal T/R (8th
), the information is first read from the even ports on the bus 238 side to the buffer 240;
The contents of are placed on the unidirectional bus 78. After the data settles on the unidirectional bus 70, the latch 242 opens, thereby latching or capturing the information on the bus 70. This is the T/R of the VCAS cycle shown in Figure 8.
Occurs due to metastasis. *In mind, VCAS is the first in the cycle.
Part has a write cycle, and then the second half of the cycle has a read cycle. FIG. 7 shows a method for simultaneously transmitting data between board (i.e. module) Received. This is SIM, NIM and DL
This happens on a separate backplane in the rack that connects all the IMs to a unidirectional bus. The information from the latch 242 is then written to the dual port RAM from the bus 238 at the odd address (OW), after which the microprocessor 238 reads the data from the odd address from the bus side 230 (OR). The data is latched into latch A of tristate latch 218 (FIG. 5).

The information signal transfer from the port to the outside continues as above,
Compared to the transfer of data via a unidirectional bus, 5L
Reading of information signals from IC and CODEC to dual photo RAM is slow; similarly, reading of information signals from RAM to C0DEC/
Data transfer to the 5LIC is also relatively slow, and the microprocessor periodically runs a program to assist in this transfer.

Each interface module is equipped with a 32-bit microprocessor (Motorow 68020 in the preferred embodiment).
Microprocessor), 32-bit wide 32-byte static RAM 260.16-bit wide 16-byte EPR
Includes OM2e2 and logical switching device 264.

One of the problems with prior art devices was that information could not be transferred from the device quickly enough.

Telephone band limits are set at the 4 kilohertz level. Following known sampling methods, it is possible to sample at twice that frequency without loss of information. Therefore, the signal could be sampled every 8-1r Rohtz, but with 900 channels (i.e., 1
800 active ports), data transfer time constraints require the VCAS cycle to transfer data within a transfer window of 139 nonaseconds.

EPROM 262 is generally a slow access memory, but R A * 26 is a 32-bit wide static RAM.
0 is very fast. The programs stored in EPROM 262 relate to decoding, encoding, and supervisory signal generation programs. These programs include off-hook state, ringing state, counting pulses from rotary dial telephone, providing loop start control signal, earth start control signal, reverse signal, 5LIC
and detects coin detection and response signals to CODEC. Other test and diagnostic programs are also included, such as the installation of a test port on the telephone line interface (DSil internal line). It also includes a program for sampling information signals. The program in EPROM 262 is loaded into RAM 260 by default. Logic switch 264 determines when the initialization routine is complete and activates a hardware switch to remove the RA from EPROM 262.
Forward all memory accesses to M260. R
Since there is no refresh place in AM260, RAM
260 is very fast. It will be appreciated that microprocessor 238 will recognize that logic switch 264 is set to EPROM2.
Verify the copy of the program in RAM 260 before switching 62.

Additionally, by default, logic cell array (LCA) 232 is configured according to the unique port pair attached to the interface module. Logic cell arrays are available from Advanced Micro Devices or XLINX. system clock 2
64 inputs to a logic cell array 232 such that the array produces a clock signal that is sent to all of the major devices of the interface. Microprocessor - 238 is approximately 2
Runs at 0MHz HZ.

The processor is interrupt driven. Therefore, the logic cell array 232 interrupts the microprocessor by raising a flag with the address vector and the special C0DEC
Indicates that data should be obtained from the RAM 23G and stored at the specified address in RAM 23G.

See Figure 6 for the timing sequence, especially the frame synchronization pulse and load counting clock (LD/CNT).
explained.

When 5LIC 212 detects an off-hook signal, a flag is raised by buffer 213. Microprocessor-238 generates a representative off-hook signal and converts the off-hook signal into dual port signal data RA.
Send to M270. Dual port RAM 270 connects to the high data segment of 32-bit internal bus 230. A read/write signal (R/W) is also provided from the microprocessor 238 to RAM 270 on SPORTOR.RAM 270 is connected to buffers 272 and 274, which are connected to signal data bus 8 and Each is connected to an 8-bit signal address bus 276 that is part of signal line 88 in the figure. Board select bus 278 allows buffer 272 to send and receive data when BIM 64 polls a special interface module. , buffers 272 and 274 are functionalized.

A typical off-hook coded signal for RAM 270 is placed in buffer 272, [11M64 is the signal data bus 8 when it polls a special module.
Write down the state change at 0. The BIM 64 then transfers the signaling data from the buffer and finally passes the data to the MCU, which detects and verifies the off-hook signal and retrieves the port assignments from memory 130 before communicating with the subscriber on the next VCAS cycle. The port-to-port map is placed in VCAS memory so that communication paths are opened on unidirectional buses 68 and 70 to and from the central office.

Similar activities are sampling of information signals (activity signals),
This also happens for standby and line testing.

In accordance with the principles of the present invention, a digital electronic cross-connect device is configured to be modular. Therefore, each telephone line interface has 24 channels with 5 LIs.
Controls whether the 24 channels are routed via C and CODECs to 24 individual subscribers or whether they are time multiplexed together and placed on a digital carrier loop (DS1 line) configured to do so.

For the DS1 time-to-time ratio signal, Sl, IC, C0D
EC, shift register 216 and latch 218 are omitted. FIG. 4B shows the front end of a digital line interface module (DLIM). The digital transport loop essentially consists of a transmission line 912 and a receive line
It consists of 14 parts. In one embodiment, the line interface device is a Rockwell No.

This is a centralized line based on 8069. Crystal 918 is LIU
916 to generate a 176M HZ signal. The interface device is Tl1-transceiver 920
connected to. In some embodiments, transceiver 92
0 is a centralized line according to Rockwell No. 8070. The data to be transmitted is transmitted by the transmitter (TX) FIFO92
2 to transceiver 920. The information received by transceiver 920 is received tR (RCR) F I
Sent to FO924. Operational signals and error data signals are governed by input/output buffer 926.
F I FO 922, F I FO 924 and buffer 926 are connected to the internal three interfaces leading to the microprocessor on the interface module board shown in Figure 4A.
Connected to 2-bit bus 23 (l).

Transceiver 920 to line interface device 9
The line TXD extending to 16 always transmits serially formatted data. LIU916 adjusts the signal and
The signal is sent to lines 912 and 914. Since the transmission information signal must always be present, the FIFO9
22 must load the information signals even if they represent empty fields, D
SL carries 24 channels time-multiplexed together,
Therefore, since there must be a continuous flow of information or data signals on the transmission line 912, the TXFIF
The O 922 must constantly load information; in one embodiment, a complete 192-bit frame of information is loaded into the TX FIFO 922. A DSL format frame is a multiplexed 24 channel block of information and framing pits. Every 125 microseconds, the DLIM's microprocessor
22 loads one entire frame excluding its framework. Therefore, the TX FIFO 922 has a 24-byte information signal corresponding to 24 channels. F I F
O922 and 924 are dual port RAM5s with counters at their inputs and outputs.

Transceiver 920 transmits TXFIF0922 at appropriate times.
Stove/read information from.

Timing is set by the received bit stream from line 914. Crystal 918 produces signals that are matched to the received multiplexed data stream for error detection. Line interface device 916 sends various signals to logic cell array 232 and also to the microprocessor when a pull-in frame is about to be received. Send Agome. LIU is
Transmission lock (TCLK) and transceiver-920
The transmission frame is synchronized to a time with respect to a properly received frame of information, producing a receive clock (RCLK) that is sent to the receiver. As such, LCA 232 produces signals that are provided to transceiver 922 such that the transceiver obtains transmitted frames from FIFO 922, error signals and other data signals are governed by I10 buffer 926.

Received frames of information are placed in receive FIFO 924. The microprocessor knows that the received frame of information is in FIFO 924, so the microprocessor
230 and transmit it to the two unidirectional til! In one implementation, the receive FIFO 924 stores 64 bytes of information. However, if two or more received frames are sent to that FIl? There is no hope of keeping him at O. Once a received frame of information is placed in the FIFO 924, the microprocessor can easily merge the information. good.

This corresponds to port 1, and the data is stored at the appropriate address in the dual port RAM, which corresponds to port l.

Microprocessors operate at much faster speeds than in transmitting and receiving information frames. Microprocessor 238 receives information signals from PIFO 92 in accordance with vector interrupts developed by LCA 232.
4 to dual baud) to the RAM 236. Data transfer via unidirectional buses 68 and 70 proceeds as described above.

Because the 24 channels of information signals are fully amplified and stored at unique "port" addresses in dual-baud RAM 236, information can be replayed by simply changing the port-to-port map and sending the data to another interface module. Can be multiplexed. Generally, if a single channel information signal is to be split and remultiplexed into 23 different channels, the inter-hot map is simply changed to send the information to a different NIM. To send a designated information signal outside the multichannel, the designated information signal is sent to a specially configured SIM or NIM. The special interface module has a program that copies the information signal from the odd address 0WOR to the even address ER-EW. The MCU memory mapping program adds a special module port to the receiver D.
Map to LIM port. The receiving DLIM port corresponds to one channel time slot of another multiplexed DSL signal.

Data transfer between 31M and 31M is performed by an intermediate interface module (NIM or DLIM>
This can be done by sending it to . This module is configured like the module described above for remultiplexing the information signal onto another 24 channel DSL line.

In a similar manner, data from one channel can be "bridged" to several output ports by defining a regression acceptor or start port. for example,
N3. Information from P2O is transferred to SIM4. Port 5, SlM
If you intend to send to 2O, port 12 and SIM35, port 23, the VCAS table should be N5P20/S4
P5; N3 P20/520P12. and N3
It may be P20/535P23. The interface module is arranged to be connected to a fiber optic line and an ISDN (Universal Services Digital Network) line.

Figure 9 shows the busbar interface module (BIM) 6
4 and VCAS memory 116, and associated VCAS
The line control device 950 will be explained in a block diagram, all of which are connected to the main bus 112. BIM64
The BIM includes a microprocessor 310, which in the preferred embodiment is a Motorola 68020.32-bit microprocessor;
, EPROM 314 , and logic switch 316 , signal input/output device 318 includes NIM, SIM, DL
Provides an interface for signal data bus 80 and module select bus 278 to and from IM and other interface devices.

Device 318 is equivalent to units 90 and 92 of FIG. 3; microprocessor 310, RAM 312, and EPROM 314, and logic switch 316 operate in much the same manner as similar components of the interface module do. EPROM 314 stores certain programs or routines for governing monitoring requirements and diagnostics of the interface module. These programs, in the initial settings of BIM64,
RAM 312, but if they are successfully enabled, the logical switch 316 will
The ROM 314 is made non-functional. 81M64 also includes memory, microprocessor and input/output devices 318
An off-hook occurrence is first detected by the SLM and by the change in data state that occurs on the signal data bus 80 when the 81M64 polls its special SIM from the select bus 278. , 81M64 connects the main line 112 to M
Notify CUI. Then the MCU connects the port, e.g. 3
62, Plo, N60, P23 to VCAS memory 11
Map to 6.

If necessary, data signals can be further transmitted back to the SIM in question via a signal data bus 80. 81M64
performs virtual address translation (to physical address) and MCU
Provides low-level error detection and processing from By default, all SIMs, NIMs, and DLIMs are polled and addresses are assigned via the 81M64 and MCU. The MCU then uses the virtual address translated by the BIM.

VCAS memory 116 is 2 bytes of high speed static RAM. Memory consists of two VCAS tables, table 1
It is divided into Table 2. The port-to-port map is placed by the MCU in an adjacent memory location in the static VCAS table.

The port-to-port map is connected to VCAS by controller line 950.
Stoved from memory.

The control device line 950 includes a latch 952 and a counter 95.
4. Crystal 956, clock 958. A frequency divider line 959 that generates a 125 microsecond pulse, i.e., V
Includes CAS cycles, logic lines 960, and VCAS input/outputs 330. Hardware switch 5W328
is activated by the MCU with command Shinkin SWX. Switch 328 selects the active V C'A S table. Crystal 956 and clock 958 feed counter 954 and divider line 959.
A counter 954, which issues HZ clock pulses, counts adjacent addresses and the appropriate VCAS table.

Therefore, the VCAS table is VCASI10330
to the port-to-port map, i.e. - for example S62゜P
lo, N60. Output P23. If only five active channels are installed between an interface module, counter 954 counts the five adjacent addresses. :J, the logic circuit 930 has a T/R of each VCAS write/read cycle of 122 nonaseconds.
Generate a signal. If all ports are operational, the VCAS table must be completely stoved in 125 microseconds; the system is designed to govern 1,024 channels. When the MCU adds a new port-to-port map to the static VCAS table, the MCU changes the state of latch 952 by adding another address location.
Change the state of 2 appropriately. If contiguous memory location 1 through 10 is used in the vCAS table and the port-to-port map in memory location 2 must be removed, then M
The CU transfers the port-to-port map to address slot 10,
After addressing slot 2, change the state of latch 952.

VCASI10330 is functionally the VCAS in Figure 3.
Port selection logic 94, N module selection 96, and S
Described as module selection. l10330 is connected to the port selection bus 72°76 and the module selection bus 74.
．． Simply adjust or arrange the signal to be appropriately stoved into 78.

The cross-connect device is architecturally designed to allow subscriber or information network interface modules to be placed anywhere in the backplane space. As power increases, individual supplier/subscriber modules are queried by the BIM to determine their location within the signal bus address range. - Once a module is placed, BIM begins defining the type for that module. The module responds with a bit pattern indicating its type (ie, information network or subscriber module). Once the type and location are defined,
The control MCU assigns addresses to the modules via the BIM. The MCU on the module writes an address to the 8-bit uniformity comparator, which establishes the module's virtual address within the system. Once the virtual address is assigned, the BIM assigns the signal bus active MCU
Serving as a translator for signal bus communication between the signal bus active MCU and further between the signal bus active MC1J and peripheral communication with individual peripheral devices, it performs the translation from virtual addresses to physical addresses between the signal bus active MCU and further between the peripheral communication and peripheral devices. Offload equipment error and failure detection processing.

The MCU is responsible for domestic duties such as maintaining the integrity of VCAS tables 1 and 2.

The MCU also diagnoses the input module and BIM, and connects the maintenance management terminal (MAT) through the communication adapter card 66.
6 MCUs required to provide 18 links to
It is also required to provide call processing such as supervisory signals required for coin operated telephones.

BIM provides bus error detection for VCAS and signal bus data streams. A line error timeout timer is installed on each data transfer. If the module does not respond for a timeout period, a bus error handling routine is initiated. A unidirectional format is established for VCAS, so the MCU is simply initiating channel opening and is essentially isolated from subsequent information flow.

When an error is detected in a VCAS transfer cycle, the MCU requests a sample of the information signal via the signal data bus to be sent across the unidirectional bus. Although the sampling routine resides in the SIM and NIM, it can be specified to extract non-intelligent but verifiable signals from the SIM, for example. The sample is MC
Sent to U. Another corresponding sample can be taken from the complementary NIM and the two samples can be checked by the MCU. If the signal is not verified, you can change the port assignments and check the data again.

FIG. 10 is a block diagram of a system information network controlling several electronic digital cross-connect devices. Especially for XC0N410 and XC0N412, cross connect equipment! 410 and 412 connect modem bank 41 via telecommunication lines 414 and 416.
8. The file server 420 is a cross-connect device 1141 with different information network terminals (one terminal 422 and the other terminal 424).
0 and 412. terminal 42
2 and 424 can access main frame 426 via gateway server 428. Additionally, dial call remote terminal 430 can access cross-connect devices 410 and 412 via a modem bank.

In this method, for each interface device, the MCU
Not only can remote testing be performed simply by calling the routines and installing a special port-to-port communication path behind the central terminal, but any special subscriber is connected to the central office.

It can be coupled to fit one of the output or connection ports. For example, if a subscriber originally had a ring and tip line leading to his residence, and he converted to a touchtone system, the central office would configure the MC to respond to that touchtone communications protocol.
All you need to do is change the port configuration of U's memory 2.

Access to the MCLJ database with all port assignments is protected by multiple password levels. Special port checks are done primarily in the background.

The invention is easy to understand from both the central office and subscriber sides. The dialton originates from the central station,
Sent through an interface device. Off-hook signals from subscribers are similarly routed through it to the central office. The interface module simply recognizes, converts and retransmits these signals as appropriate. Therefore, the module generates the appropriate voltage on the line. The interface device may be arranged to demodulate the multiplexed 24 channel PCM highway signal, after which the demodulated JEJ signal can be routed based on a specific mapping routine in the memory of the MCUI. For digital loop interface modules, substantially only the external appearance of the photo is modified to accommodate the special communication protocol. Also, the 5LIC is not required for the 081 line, instead of the 5LIC and CODEC, a parallel formatted digital that can be stored in dual port RAM at the special end of the unidirectional bus by placing a suitable conversion line mechanism on the port. Try to get a signal. Alternatively, you can essentially put the data in a suitable buffer and use VCAS
It is governed in much the same way as for successive/write cycles.

Each interface, BIM and MCU has its own clock, so the devices operate independently.

The claims appended hereto are intended to cover these and other items within the scope and spirit of the invention.

[Effects of the Invention] Since the present invention is as described above, it is possible to electronically connect a communication line from a central office to a particular subscriber line, and also connect a port connected to the central office to a subscriber. This has the effect that it can be mapped to the connected ports in a one-to-one relationship.

[Brief explanation of drawings]

1 is a block diagram illustrating a prior art telecommunications system, FIG. 2 is a block diagram illustrating a telecommunications system utilizing an electronic cross-connect device according to the present invention, and FIG. 3 is a block diagram illustrating a telecommunications system according to the principles of the present invention. A block diagram illustrating a cross-connect device, FIG. 4A, shows a typical intermodule.
4B is a block diagram illustrating a portion of the digital line interface module; FIG. 5 is a block diagram illustrating a tristate bus transceiver or latch located inside the port shown in FIG. 6 is a time chart diagram illustrating timing; FIG. 7 is a schematic diagram illustrating bidirectional data flow on a unidirectional bus coupled to an interface module;
FIG. 8 is a schematic diagram illustrating the read/write stove cycle of the audio channel address monitoring (CAS) cycle; FIG. 9 is a block diagram illustrating the bus interface module; and FIG. 10 is a cross-connect arrangement according to the principles of the present invention. FIG. 2 is a schematic diagram illustrating remote control. 10...Central office 30...Channel bank 34...Electronic cross-connect device 36, 38.40.48.50.52...Interface module Applicant Gibralter Technologies Corporation Director Patent attorney Mamoru Ushiki

Claims (14)

[Claims] (1) A plurality of first telecommunications lines connected to a plurality of first telecommunications lines.
the first comprising an interface means, a plurality of second interface means connected to a plurality of second telecommunication lines, and first and second unidirectional busbars coupling the first and second interface means; and an electronic cross-connect device for providing a communication path for information signals between second telecommunication lines, wherein each interface means is coupled to a single interface means and connected to a plurality of ports respectively coupled to a respective telecommunication line. means for obtaining a discrete digital formatted signal for each port from an information signal received on a telecommunications line; and a first unidirectional means for transmitting the discrete digital formatted signal from one port to another interface means. means for simultaneously transmitting via a bus and accepting transfer of additional formatted signals via a second unidirectional bus from the second port to the first port; and simultaneous transmitting and accepting means controlled by one of a pair of command signals unique to the second port, and transmitting additional information signals from the first port to the respective lines based on the additional formatting signal. means, the cross-connect device comprising controller means for simultaneously generating the pair of unique command signals; and command signal means for coupling the plurality of first and second interface means to the controller means. An electronic cross-connect device comprising a busbar. (2) The cross-connect device includes means for changing the command signal so that the discrete formatted signals can be forwarded to further ports without changing the direction of the discrete formatted signals from the other ports. The electronic cross-connect device according to claim 1, characterized in that: (3) The simultaneous transfer and reception means simultaneously supplies the obtained formatted signal to the first unidirectional bus for each port and latches the additional formatted signal on the second unidirectional bus. 2. The port according to claim 1, further comprising means for temporarily storing the obtained formatted signal and the additional formatted signal during the time between port-to-port transfers. electronic cross-connect equipment. 4. The electronic cross-connect device of claim 3, wherein the temporary storage means is a multiple dual port random access memory means. (5) The formatted signal acquisition means includes means for converting the received information signal into a parallel formatted digital signal, and each interface means controls the flow of the formatted signal from the acquisition means and the conversion means to the port. shall include a processing device and a processing storage means for
2. The electronic cross-connect system of claim 1, wherein the unidirectional busbar transfer is substantially independent of the processing device and processing storage means. (6) The electronic cross-connect according to claim 1, wherein the first and second bus bars are parallel format buses, the simultaneous transfer means is a parallel format bus, and the simultaneous transfer means utilizes parallel format signals. Device. (7) In an electronic cross-connect device that provides a communication path for information signals passing between a plurality of first and second telecommunication lines, the cross-connect device is connected to half of the first lines, and each of the lines a plurality of first interface means each connected to at least one first port; and a plurality of second interface means each connected to half of the second lines, each line being connected to at least one second port. , each interface means comprising:
means for obtaining a discrete adjustment signal for each port from the information signal received on the connection line; and simultaneously transferring the discrete signal from a certain first port to a certain second port via the bus,
and means for transferring additional discrete signals from the second port to the first port via the bus, the means being controlled by a pair of port transfer command signals to the first and second ports. and means for sending an information signal from each port to a connecting line based on the transferred discrete signals, and the cross-connect device further includes mapping port-to-port transfers to the pair of port transfers. An electronic cross-connect device comprising means for generating a command signal, means for applying the transfer command signal to the transfer means and a corresponding interface device, respectively, and means for changing the mapping means. (8) The electronic cross-connect device according to claim 7, wherein the mapping means includes storage means for storing port transfer command signals for each port. (9) The mapping means and the applying means operate substantially independently of the changing means in applying the port transfer command signal to the transferring means.
The electronic cross-connect device described. (10) The mapping means includes a dual section of active and stationary sections and a device for calling the active section and switching alternately between the active and stationary sections, and the changing means performs map conversion of the stationary section. 10. The electronic cross-connect device of claim 9, further comprising central processing unit means for changing the mapping means. (11) A process of providing a port on each communication path, a process of acquiring an information signal on the communication path and formatting the information signal into a discrete signal, and converting the first port that received the information into a second port according to a predetermined program. a step of mapping to the first and second ports; and a step of simultaneously transferring formatted signals between the first and second ports in two directions according to the mapping step. , removing the mapping between the first and second ports after the information signal is no longer present on the first and second telecommunication lines; and modifying the program and thus the mapping from a remote location. A method for electronically providing a transmission path for information signals of a communication path between a first and a second telecommunication line, characterized in that the method comprises: (12) A step of detecting the received information signal and determining the existence of a monitoring request, a step of generating a monitoring signal according to a predetermined procedure based on the monitoring request, and a step of transmitting the monitoring signal from the port. Claim 11 characterized in that it includes:
Method described. 13. The method according to claim 11, further comprising the step of temporarily storing the map relationship of the ports. 14. The method of claim 11, wherein the mapping step occurs asynchronously and substantially independently of the formatting signal transfer step.