JPH02275664A - Reference-voltage generating circuit - Google Patents

Reference-voltage generating circuit

Info

Publication number
JPH02275664A
JPH02275664A JP1097939A JP9793989A JPH02275664A JP H02275664 A JPH02275664 A JP H02275664A JP 1097939 A JP1097939 A JP 1097939A JP 9793989 A JP9793989 A JP 9793989A JP H02275664 A JPH02275664 A JP H02275664A
Authority
JP
Japan
Prior art keywords
voltage
output
section
output voltage
selector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1097939A
Other languages
Japanese (ja)
Inventor
Minoru Seki
関 稔
Hideo Takahashi
秀雄 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1097939A priority Critical patent/JPH02275664A/en
Publication of JPH02275664A publication Critical patent/JPH02275664A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable trimming even when the constant voltage of a constant voltage source is made higher than desired reference output voltage by installing an output voltage selector for selecting a voltage dividing path. CONSTITUTION:An output voltage selector 4 is inserted between a nodal point B, at which the output terminal of an internal reference voltage section 1 and a resistance section 6 for trimming are connected, and the input terminal of an output buffer section 2. The i1-i32 and T6-T10 and output terminal S of the output voltage selector 4 correspond to j1-j32 and T1-T5 and an output terminal F respectively, the input terminal i1 is connected at the nodal point B, and i2-i32 are connected to nodal points N1-N31 respectively. Consequently, the same internal reference voltage VB or one of the divided voltage is selected as selective output voltage VS at the output terminal S by digital control signals input to the terminals T6-T10. Accordingly, reference output voltage lower than internal constant voltage can also be trimmed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は基準電圧発生回路に関し、特にトリミング用抵
抗部を有する集積回路の基準電圧発生回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reference voltage generation circuit, and more particularly to a reference voltage generation circuit for an integrated circuit having a trimming resistor section.

〔従来の技術〕[Conventional technology]

第2図は従来の基準電圧発生回路の一例の回路図である
FIG. 2 is a circuit diagram of an example of a conventional reference voltage generating circuit.

出力バッファ部2は内部基準電圧部1からの内部基準電
圧VBの1倍を出力するボルテージホロア回路である。
The output buffer section 2 is a voltage follower circuit that outputs one times the internal reference voltage VB from the internal reference voltage section 1.

帰還電圧セレクタ3は、内部基準電圧部1の出−ダで選
択するものである。
The feedback voltage selector 3 is used for selection at the output of the internal reference voltage section 1.

デコーダはディジタル信号を入力端T1〜T。The decoder receives digital signals from input terminals T1 to T.

から入力して電子スイッチを駆動する。input to drive the electronic switch.

定電圧源5の定電圧VTは内部基準電圧部1の内部にあ
るエンハンスメント型トランジスタ及びデイブレラシラ
ン型トランジスタのしきい値電圧によシ決まる。
The constant voltage VT of the constant voltage source 5 is determined by the threshold voltages of the enhancement type transistor and the dabrella silane type transistor inside the internal reference voltage section 1.

抵抗Ra、Rb及びrはトリミング用抵抗部6の各抵抗
で、ここではRa 、Rbが各1個、rが32個使用さ
れている。
Resistors Ra, Rb, and r are the respective resistors of the trimming resistor section 6, and here, one each of Ra and Rb and 32 r are used.

各抵抗間の接点Nl ” N3zは、セレクタ3の上か
ら順に入力端jt−j3zに対応して接続されている。
The contact points Nl''N3z between the respective resistors are connected to the input terminals jt-j3z of the selector 3 in order from the top.

第3図は第2図の帰還電圧セレクタの回路図である。FIG. 3 is a circuit diagram of the feedback voltage selector of FIG. 2.

帰還電圧セレクタ3は、ディジタル入力端T1〜T、か
らの入力信号によシ行ゲート部3R及び列ゲート部3c
のデコーダを駆動し、8×4のトランスファゲートのマ
トリックスゲート部3Mを有している。
The feedback voltage selector 3 is connected to a row gate section 3R and a column gate section 3c according to input signals from digital input terminals T1 to T.
It drives a decoder and has a matrix gate section 3M of 8×4 transfer gates.

この基準電圧発生回路はトリミング用抵抗部6の節点の
例えばN1に接続するjl又はN1γに接続するjl7
がセレクタ3で選択される場合に、出力バラフッ部20
基準出力電圧Vjが簡単に求められるようになっている
This reference voltage generation circuit is connected to a node of the trimming resistor section 6, for example, jl connected to N1 or jl7 connected to N1γ.
is selected by the selector 3, the output balance section 20
The reference output voltage Vj can be easily obtained.

またこれらの電圧より逆に所定の基準出力電圧■jに最
も近くなるような節点番号を求めることができる。
Further, from these voltages, it is possible to find the node number that is closest to the predetermined reference output voltage ■j.

内部基準電圧部1の内部基準電圧をVB、また定電圧源
5の定電圧をVT、出力バッファ部2の基準出力電圧を
■j、セレクタ3で選択した第j番目の入力電圧端Jj
の番号を」(但しj=1〜32)、出力バッファ部2の
オフセラ)[圧をVIO%選択番号jを1及び17とし
た場合の基準出力電圧■、をVl  p ■17とする
と次の第(1)〜(5)式が得られる。
The internal reference voltage of the internal reference voltage section 1 is VB, the constant voltage of the constant voltage source 5 is VT, the reference output voltage of the output buffer section 2 is ■j, and the j-th input voltage terminal Jj selected by the selector 3
(however, j = 1 to 32), the offset voltage of the output buffer section 2) [pressure is VIO% When the selection number j is 1 and 17, the reference output voltage ■ is Vl p ■ 17, then the following Equations (1) to (5) are obtained.

Vj= Vs + Vro        −−(1)
VB=(1+(Ra+(k−1)r)/(Rb+(33
−k)r))Vr  ・−・・(2)第(1) 、 (
21式よシ Vj=(1+(Ra+(k  1)r)/(Rb+(3
3−k)r〕)Vt+Vxo−(3)j=1.17の時
、■j=■l、■17であるから第(3)式よシ第(4
) 、 (5)式が得られる。
Vj=Vs+Vro --(1)
VB=(1+(Ra+(k-1)r)/(Rb+(33
-k)r))Vr ・---(2)th (1), (
According to formula 21, Vj=(1+(Ra+(k 1)r)/(Rb+(3
3-k)r])Vt+Vxo-(3) When j=1.17, ■j=■l, ■17, so the equation (3) becomes the
), formula (5) is obtained.

V 1== (1+Ra/ (几b+3z r ) )
 VT +V 10・・・・・・ (4) Vly=(1+(Ra+16 r )/(LCb+16
r ))Vr + Vz。
V 1== (1+Ra/ (几b+3z r ) )
VT +V 10... (4) Vly=(1+(Ra+16 r)/(LCb+16
r)) Vr + Vz.

・・・・・・ (5) 第2図では、実際の値として几a ” 0.48 kΩ
(5) In Figure 2, the actual value is 0.48 kΩ.
.

Rb=10.212 kΩ及びr=0.213にΩを使
用し、また所望の基準出力電圧Vjを3.1vとすると
第+31 、 +4)及び(5)式より第(6)式が得
られる。
Using Ω for Rb = 10.212 kΩ and r = 0.213, and assuming the desired reference output voltage Vj to be 3.1v, equation (6) is obtained from equations +31, +4) and (5). .

j=(251,1+4Vty  85Vl)/(3,1
−5vl+4Vly)  +++  (6)また、第1
4) 、 +5)式より第+71 、 (81式が得ら
れる。
j=(251,1+4Vty 85Vl)/(3,1
-5vl+4Vly) +++ (6) Also, the first
From equations 4) and 5), equations +71 and (81) are obtained.

VI?=1.28525VT+VIO−・”  (7)
v1=1.0282vT十■工。    ・・・・・・
 (8)今VT=3.OV、VX□=10mVとすると
、第+6) 、 (7)及び(8)式よりj=1.1と
なり、第(3)式よりv0=λ099VKなる。
VI? =1.28525VT+VIO-・” (7)
v1 = 1.0282vT 1.・・・・・・
(8) Now VT=3. When OV, VX□=10 mV, j=1.1 from equations (7) and (8), and v0=λ099VK from equation (3).

またVT= 1.9 V、”to = −20mVとす
ると、第(6)。
Also, if VT = 1.9 V and "to = -20 mV," No. (6).

(7)及び(8)式よシ、j=3o、9となシ、第(3
)式より■。
According to equations (7) and (8), j = 3o, 9 and the (3rd
) From the formula ■.

=3.106Vになる。=3.106V.

従って、本基準電圧発生回路は定電圧■1が1.9V〜
3.070間でセレクタ3によりトリミングが可能であ
る。
Therefore, in this reference voltage generation circuit, the constant voltage (1) is 1.9V~
Trimming is possible with the selector 3 between 3.070 and 3.070.

すなわち、定電圧vTが所望の基準出力電圧■。That is, the constant voltage vT is the desired reference output voltage ■.

よりも低い電圧の場合においてトリミングを行っていた
Trimming was performed when the voltage was lower than that.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の基準電圧発生回路では、定電圧源の定電
圧が所望の基準出力電圧より高い時はトリミングできな
いという欠点があった。
The conventional reference voltage generation circuit described above has a drawback that trimming cannot be performed when the constant voltage of the constant voltage source is higher than the desired reference output voltage.

本発明の目的は内部の定電圧よりも低い基準出力電圧も
トリミングできる基準電圧発生回路を提供することにあ
る。
An object of the present invention is to provide a reference voltage generation circuit that can also trim a reference output voltage lower than an internal constant voltage.

〔課題を解決するだめの手段〕[Failure to solve the problem]

本発明の基準電圧発生回路は定電圧及び帰還電圧をそれ
ぞれ入力し演算増幅して内部基準電圧を出力する内部基
準電圧部と、複数のトリミング抵抗を節点を介して直列
接続し前記内部基準電圧を分圧するトリミング抵抗部と
、前記節点の1つの電圧を前記帰還電圧として選択する
帰還電圧選択部と、前記内部基準電圧または前記節点の
電圧の1つを選択し基準出力電圧として出力する基準出
力電圧選択部とを含んで構成されている。
The reference voltage generation circuit of the present invention has an internal reference voltage section that inputs a constant voltage and a feedback voltage, operationally amplifies them, and outputs an internal reference voltage, and a plurality of trimming resistors connected in series through nodes to generate the internal reference voltage. a trimming resistor unit that divides the voltage; a feedback voltage selection unit that selects one voltage at the node as the feedback voltage; and a reference output voltage that selects one of the internal reference voltage or the voltage at the node and outputs it as a reference output voltage. It is configured to include a selection section.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.

基準電圧発生回路は、第2図の内部基準電圧部1の出力
端とトリミング用抵抗部6の接続する節点Bと出力バッ
ファ部2の入力端間に出力電圧セレクタ4を挿入したこ
とが異る点以外は従来の基準電圧発生回路と同一である
The reference voltage generation circuit differs in that an output voltage selector 4 is inserted between the node B where the output terminal of the internal reference voltage section 1 and the trimming resistor section 6 are connected in FIG. 2, and the input terminal of the output buffer section 2. Other than this point, it is the same as the conventional reference voltage generation circuit.

出力電圧セレクタ4は、第3図の帰還電圧セレクタ3七
同−回路で、11−132 z Ta 〜T10及び出
力端Sはそれぞれ」1〜J 32 + T1−T6及び
出力端Fに対応している。
The output voltage selector 4 is the same circuit as the feedback voltage selector 3 in FIG. There is.

入力端i1は節点Bに接続し、12〜isxはそれぞれ
節点N1〜N31に接続している。
Input terminal i1 is connected to node B, and input terminals 12 to isx are connected to nodes N1 to N31, respectively.

従って、端子T6〜’l’toに入力されるディジタル
制御信号によって出力端Sには第2図に説明した従来と
同じ内部基準電圧VB又はその分圧電圧の一つが選択出
力電圧■sとして選択される。
Therefore, depending on the digital control signal input to the terminals T6 to 'l'to, the same internal reference voltage VB as the conventional one explained in FIG. 2 or one of its divided voltages is selected as the selected output voltage ■s at the output terminal S. be done.

次に回路の動作を説明する。Next, the operation of the circuit will be explained.

内部基準電圧部1の内部基準電圧をvB%また定電圧源
5の定電圧をvT1T1出力バラフッの基準出力電圧を
Vj、トリミング用抵抗部6の各分圧を入力する帰還電
圧セレクタ3が選択した第jの入力端番号を」(但しj
=1〜32)、出力電圧セレクタ4が選択した第iの入
力端番号をi(但しi = 2〜32)、出力バッファ
部2のオフセット電圧をVIOとすると次の第(91、
(11式が得られる。
The internal reference voltage of the internal reference voltage section 1 is set to vB%, the constant voltage of the constant voltage source 5 is set to vT1, the reference output voltage of T1 output is set to Vj, and the feedback voltage selector 3, which inputs each divided voltage of the trimming resistor section 6, selects j-th input terminal number" (however, j
= 1 to 32), the i-th input terminal number selected by the output voltage selector 4 is i (where i = 2 to 32), and the offset voltage of the output buffer section 2 is VIO, then the following (91,
(Equation 11 is obtained.

VB =((Ra十几b+32r)/〔几b+(a 3
  Dr )) VT・・・・・・ (9) Vj=(C几り+(34=)r)10Lb +(33−
j)r))VT+VIO・・・・・・ 0.1 ここでi = lとすると第2図の従来例で説明した場
合と同一になるので、1=1117の時Vj=V1゜V
j7とし、Ra=0.48にΩ、几bり10.212に
Ω、r=0.213にΩ及び所望の基準出力電圧Vjを
3.1■とすると第(1v式が得られる。
VB = ((Ra 10 b + 32 r) / [几 b + (a 3
Dr)) VT・・・・・・ (9) Vj=(C几り+(34=)r)10Lb+(33−
j) r)) VT+VIO...0.1 Here, if i = l, it will be the same as the case explained in the conventional example in Fig. 2, so when 1 = 1117, Vj = V1°V
j7, Ra=0.48 is Ω, R=0.212 is Ω, r=0.213 is Ω, and the desired reference output voltage Vj is 3.1■, then the formula (1v) is obtained.

j=(251,1+4V+y   85V+)/(3,
15V1+4V17)   −−(11)これは従来例
で説明した第(6)式と同じ式である。
j=(251,1+4V+y85V+)/(3,
15V1+4V17) --(11) This is the same equation as equation (6) explained in the conventional example.

例としてZIV≦■T≦3.4■の場合を説明する。As an example, the case where ZIV≦■T≦3.4■ will be explained.

+7+ 、 (8)式よりVxo=Oとすルト、V17
=4.3699V。
+7+, from formula (8), Vxo=O and V17
=4.3699V.

Vx=3.4959Vとfx リi(6に!’)j=−
9,22とfxす、1≦j≦32を満足せずi = l
ではトリミング不可能である。
Vx=3.4959V and fx ri (to 6!')j=-
9, 22 and fx, 1≦j≦32 is not satisfied, i = l
It is impossible to trim.

従って、i〉1として基準出力電圧よりも内部基準電圧
が高い場合をトリミングする。
Therefore, when i>1, trimming is performed when the internal reference voltage is higher than the reference output voltage.

例えばVT =3.4Vでトリミング可能とするKは第
α1式でj=1の時■l≦3.1vを満足すればよいか
ら、仮にVIo = Oとすると第(10−1)式が得
られる。
For example, K that allows trimming at VT = 3.4V only needs to satisfy ■l≦3.1v when j = 1 in the α1 equation, so if VIo = O, the equation (10-1) is obtained. It will be done.

i≧8,05            ・・・・・・ 
(10−1)よってi = / 0とおくと、第α1式
より第04が、まりj =1 、17 O時Vj =V
+ 、 Vj7 テhルから、 VIO=0とすると第
(13、(14)式が得られる。
i≧8,05 ・・・・・・
(10-1) Therefore, if i = / 0, then from the α1 formula, the 04th is the mari j = 1, 17 O, Vj = V
+ , Vj7 tel, and when VIO=0, equations (13 and (14)) are obtained.

Vj = ((Rb +24.r)/(Rb +(33
−j)R) )Vt+Vxo    ・・・・・・ α
つVl =0.90VT         −・”  
Q31Ly  =  1.1 25VT       
           −・・  04)ここでvT=
3.4vとすると、第Q31 、 Q41式ヨF) V
+ =3.06v、v17=3.825■であるから、
第(11)式jすj=2.o3、よって」=2とすると
第α3式よりV鵞=3.099Vになる。
Vj = ((Rb +24.r)/(Rb +(33
−j)R) )Vt+Vxo ・・・・・・ α
Vl=0.90VT-・”
Q31Ly = 1.1 25VT
−・・04) Here vT=
If it is 3.4v, then formulas Q31 and Q41 (yoF) V
+ = 3.06v, v17 = 3.825■, so
Equation (11) j=2. o3, therefore, if ``=2, then V = 3.099V from the α3 equation.

ここで、VT=2.IVとすると、第α国、C14)式
よりVl ’ 1.85 V−Vj7 =Z3625 
V テアルカラ、第(11)式よシj=3z2、よって
j=32とすると第α3式よりVz =3.086 V
になる。
Here, VT=2. If it is IV, from the αth country, formula C14), Vl ' 1.85 V-Vj7 = Z3625
V The Alkara, according to equation (11), j = 3z2, so if j = 32, then from equation α3, Vz = 3.086 V
become.

従って、ZIV≦vT≦3.4■の場合でもトリミング
可能となシ、所望の基準出力電圧■oより高い定電圧V
Tでもトリミング可能となる。
Therefore, trimming is possible even when ZIV≦vT≦3.4■, and a constant voltage V higher than the desired reference output voltage o
Trimming is also possible with T.

なお、両セレクタ3及び4は、第3図の列ゲート部3c
の代υにインバータ、NAND及びトランス7アゲート
による論理回路でもよい。
Note that both selectors 3 and 4 are connected to the column gate section 3c in FIG.
Instead of υ, a logic circuit using an inverter, NAND, and transformer 7 agate may be used.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明はトリミング用抵抗部と次
段出力バッファ部の入力端の間に分圧径路を選択するた
めの出力電圧セレクタを設けることにより、定電圧源の
定電圧が所望の基準出力電圧より高い場合でもトリミン
グできるという効果がある。
As explained above, the present invention provides an output voltage selector for selecting a voltage dividing path between the trimming resistor section and the input terminal of the next-stage output buffer section, so that the constant voltage of the constant voltage source can be adjusted to a desired level. This has the effect that trimming can be performed even when the output voltage is higher than the reference output voltage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の回路図、第2図は従来の基
準電圧発生回路の一例の回路図、第3図は第2図の帰還
電圧セレクタの回路図である。 1・・・・・・内部基準電圧部、2・・・・・・出力バ
ラフッ部、3・・・・・・帰還電圧セレクタ、4・・・
・・・出力電圧セレクタ、5・・・・・・定電圧源、6
・・・・・・トリミング用抵抗部、v8・・・・・・内
部基準電圧、VF・・・・・・帰還電圧、Vj・・・・
・・基準出力電圧、Vs・・・・・・選択出力電圧、V
T・・・・・・定電圧。 代理人 弁理士  内 原   晋 箭3図
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of an example of a conventional reference voltage generating circuit, and FIG. 3 is a circuit diagram of the feedback voltage selector of FIG. 2. 1...Internal reference voltage section, 2...Output balance section, 3...Feedback voltage selector, 4...
... Output voltage selector, 5 ... Constant voltage source, 6
...Trimming resistance section, v8...Internal reference voltage, VF...Feedback voltage, Vj...
...Reference output voltage, Vs...Selected output voltage, V
T... Constant voltage. Agent Patent Attorney Shinsuke Uchihara 3

Claims (1)

【特許請求の範囲】[Claims] 定電圧及び帰還電圧をそれぞれ入力し演算増幅して内部
基準電圧を出力する内部基準電圧部と、複数のトリミン
グ抵抗を節点を介して直列接続し前記内部基準電圧を分
圧するトリミング抵抗部と、前記節点の1つの電圧を前
記帰還電圧として選択する帰還電圧選択部と、前記内部
基準電圧または前記節点の電圧の1つを選択し基準出力
電圧として出力する基準出力電圧選択部とを含むことを
特徴とする基準電圧発生回路。
an internal reference voltage section that inputs a constant voltage and a feedback voltage, operationally amplifies them, and outputs an internal reference voltage; a trimming resistor section that divides the internal reference voltage by connecting a plurality of trimming resistors in series through nodes; The feedback voltage selection unit selects one voltage at a node as the feedback voltage, and the reference output voltage selection unit selects one of the internal reference voltage or the voltage at the node and outputs it as a reference output voltage. Reference voltage generation circuit.
JP1097939A 1989-04-17 1989-04-17 Reference-voltage generating circuit Pending JPH02275664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1097939A JPH02275664A (en) 1989-04-17 1989-04-17 Reference-voltage generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1097939A JPH02275664A (en) 1989-04-17 1989-04-17 Reference-voltage generating circuit

Publications (1)

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JPH02275664A true JPH02275664A (en) 1990-11-09

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5889233A (en) * 1995-08-14 1999-03-30 Nec Corporation Multilayer wiring structure
KR100335033B1 (en) * 1997-10-09 2002-09-27 가부시끼가이샤 도시바 Semiconductor integrated circuit and semiconductor memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5889233A (en) * 1995-08-14 1999-03-30 Nec Corporation Multilayer wiring structure
KR100335033B1 (en) * 1997-10-09 2002-09-27 가부시끼가이샤 도시바 Semiconductor integrated circuit and semiconductor memory

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