JPH0227493A - Boltzmann machine type neuro-computer system - Google Patents

Abstract

PURPOSE:To make a Boltzmann machine into a circuit by inserting a transistor (TR) for weighting to the circuit combining the units of respective input, hidden and output layers at the section of the layers. CONSTITUTION:Units U1 and U2 respectively consist of an adder Add and a comparator COMP, and a weight W12 is consists of a TR 14. A threshold potential theta is applied to the comparator COMP, when the output of the adder is larger than theta, the output of the unit is set at 1 (firing), when it is smaller than theta, the output is set at 0, and the output of a threshold unit is used for the threshold theta. For the TR 14, an AND gate 11, the latch of the output, a counter 12, a DA converter 13 are provided, and the unit output (the output of the comparator) is added to the AND gate 11 together with a reference pulse. Further, a random noise generator 16 is provided, and the output is applied through an amplifier 15 to one input terminal of the adder of the respective units. Thus, the Boltzmann machine can be formed as hardware.

Description

[Detailed Description of the Invention] [Summary of the Invention] It is an object of the present invention to provide a method for circuitizing a Boltzmann machine in relation to a Boltzmann machine type neurocomputer system, particularly its neural network, and to provide an addition method in which random noise is input together with an input signal. The circuit includes a plurality of units including a comparator and a comparator that fires when the output of the adder and the threshold voltage are input and the former exceeds the latter, and connects the units of the input, hidden, and output layers between layers, A gate circuit which inserts a transistor for weighting, receives the outputs and reference pulses of the two combined comparators, and converts the period during which both of the outputs are in a firing state into a number of pulses, and the output pulse of the circuit is A counter for counting, a DA converter for converting the output of the counter into analog and applying it to the base of the transistor, and a neural network attached to each transistor are configured.

[Industrial application field]

The present invention relates to a Boltzmann machine type neurocomputer system, particularly to its neural network.

In recent years, in the field of computer information processing, research and development of non-Neumann-type computers has been progressing in contrast to so-called Neumann-type computers, and one approach is research on neural network-type computers that simulate the operation of neural tissues. is attracting attention. Among these, the concept of a Boltzmann machine, which has a network configuration equivalent to a thermodynamic system, guarantees that the energy state follows the Boltzmann distribution and reaches a thermal equilibrium state after a sufficient amount of time is seen as promising.

[Conventional technology]

The principle of the Boltzmann machine was proposed by Hinton et al. around 1983 (Geffrey E.

Former nton, et, al Boltzman l'1
achin: Con5traintSatisfac
tion networks that learn,
Technical Report CMU-C5-8
4-119), the outline is as follows.

The network consists of units Ui (t=1.
2+ .
1 or 0) to other units. Each bond has a bond strength Wij, and Wij takes a positive or negative real value.

The network is E−−Σ Wij Si Sj+Σθi Si
......(1) i<J, each unit has an energy E such that E is small (θ is a threshold value), and the th unit is 0.
The increment ΔEk of E due to the change from 1 to 1 is ΔE, = ΣWk, Si-θ8...
It is expressed as (2). The network set up in this way is equivalent to a thermodynamic system of interacting binary elements, and the end point of its operation is expected to be in a thermal equilibrium state. However, there is no guarantee that the thermal equilibrium state is the minimum energy point.
If there is degeneracy in energy, there is a possibility that the energy has simply fallen into a minimum point. To avoid this danger, the following probability Pm is introduced into the operating principle of the system.

Pm = 1/(1+exp(-ΔEk/T)
)...”・(3) This Ph represents the probability of being the th unit when the energy gap is ΔEk, T
is a parameter corresponding to the temperature of the system. If Pm is defined in the above equation, this network becomes a so-called "system in contact with a heat bath of temperature T", and the probability that the network will be in global state A with energy EA follows the Boltzmann distribution, and after a sufficient time it will reach thermal equilibrium. guaranteed to reach the state.

There are three types of Boltzmann machine units: incoming units, outgoing units, and hidden units. These 3
Not all types of units necessarily exist, and there may be networks with no hidden units or no distinction between outgoing units.

A Boltzmann machine is not a network that performs predetermined operations according to a set procedure, but rather a network that can learn procedures for a certain purpose by itself using information provided from the outside world. There are basically no restrictions on the purpose.

Learning occurs based on information from the outside world.

Information specifically refers to visible units (people, output).
This is the bit pattern given to 1 = (S,,S,,...Sk)
...... (4) - If you summarize it, it can be considered as one vector quantity. Here, k is the number of visible units. During learning, a plurality of such vectors are generally given, and these are called environments. Learning takes place in the environment, and the information from the environment is fixed within the network in a different form. The anchoring process is performed through changing the weights of the connections.

During learning, the indicator of equation (5) is introduced. This represents the distance quantity between two probability distributions.

G=ΣP (Va) j! n[P(Va)/P
' (Va)] ""... (5) In the above equation, vA indicates the A-th state of the visible unit, and P(Va) is the probability when the probability distribution of the vA state is dominated by the environment, and P'(va) means the probability of the VA state in which the network operates as a closed system without being influenced by the outside world. The former state is called a clamp state, and the latter state is called a free run state.

G takes a non-negative value and becomes 0 when and only when the distributions of P (vA) and P' (VA) are completely equal.

The definition of Boltzmann machine learning is to make G as small as possible.
Ideally, it should be 0. Because what is Goo?
This is because it means that the free-running network can completely reproduce the learned environment. In order to change the weight of the connection toward GζO, it is necessary to know the behavior of G with respect to the weight, and the following equation is known for this.

σG/σWij=-(Pij-P'ij)/T...
...(6) In the above equation, Pij represents the probability that the j-th and first units are simultaneously 1 in the clamped state when the system reaches thermal equilibrium, and P'ij represents the probability that the j-th and first units are simultaneously 1 in the free-run state. represents the probability of the same event at . Therefore, if the weights are changed using the following equation, it is possible to operate the network with self-loss of Gζ0.

ΔWij-ε (Ptj-P'ij)
(7) Here, ΔWij is the weight increment, and ε is the minimum step of weight change. In order to achieve Gζ0, a multi-step operation is generally performed in which the network is operated at a high temperature to bring it to a roughly low energy state, and then operated at a low temperature to search for the true lowest energy state. This process is called simulated annealing.

Boltzmann machines can be made into various types depending on the number and configuration of units, but next we will explain the learning procedure using a 4-3-4 encoder as an example.

4-3-4 encoder, as shown in FIG.
1, and four output crab units 01 to 04. These are connected as shown. Utk is an always-on threshold unit, which couples all units of the network. An arbitrary combination of bit patterns is given to t,,O, from the outside to such a network, and the combination is learned. A flowchart is shown in FIG.

In the initial state of step (2), all units are not clamped, and the coupling strength Wij is an arbitrary value. In the clamp state of step (2), the combination of bit patterns of the input unit It and the output unit O1 is fixed in accordance with the probability distribution to be learned, and the network is run to realize a thermal equilibrium state. To bring the system closer to a state of thermal equilibrium, simulated annealing is performed in which the temperature parameter T is varied from large to small in an appropriate sequence. In FIG. 18, the portions where simulated annealing is performed are indicated by (T). Step (2) determines Pij in the thermal equilibrium state achieved in (2). In the next step ■1
．． Remove the clamps from ,O, and run the network,
Annealing similar to step (2) is carried out to reach a thermal equilibrium state, and in the next step (2), P'ij is determined. In step ■■
, ΔW determined from Pij and P'ij obtained by
Update Wij based on ij. Then, the learning loop from ■ to ■ is repeated a predetermined number of times, and the learning is terminated when the information on the combination of bit patterns has been sufficiently converted to Wij (step ■).

A Boltzmann machine that has been properly trained using this method is 1. In a free-run state where only input vectors are given to Oi, it is possible to recall the output vector that should be at Oi.

[Problem to be solved by the invention]

Boltzmann machines are expected to be able to quickly execute multivariable optimization problems and pattern recognition, which are weak points of Neumann combinators, but there have been no reports of examples of creating actual machine models using circuits. Not yet. The only published reports rely on software simulation as a method to realize the functionality of Boltzmann machines.

However, with software methods, even when processed on a large computer and even with a 4-2-4 configuration, it takes nearly 3 hours, and even when considering learning methods, it takes a long time to obtain results. Call.

The purpose of this invention is to provide a method for circuitizing a Boltzmann machine.

Another object of the present invention is to simplify the amount of network connections by having a microprocessor perform the calculation of ΔW i j that determines the weight of the counter and connections in the circuitized Boltzmann machine. It is something to do.

[Means to solve the problem]

FIG. 1 shows the configuration of the Boltzmann machine of the present invention. If we take out the two mutually connected units of the Boltzmann machine, it will look like Fig. 1(a), and these units Ul+U
! is composed of an adder Add and a comparator COMP as shown in FIG. A threshold potential θ is given to the comparator COMP,
- If the adder output is greater than θ, the unit output is 1 (fire); if it is smaller than θ, the unit output is 0. As shown in FIG. 17, this threshold value θ uses the output of a threshold unit Uth provided in the network. The threshold unit is always in an ON state and is connected to all other units, and the weights of the connections are also subject to learning. For transistor 14, AND gate 11
, its output latch and counter 12, DA converter 1
3 is provided, and the unit output (comparator output) is applied to the analogue 11 together with the reference pulse. A random noise generator 16 is also provided, and its output is applied via an amplifier 15 to one input terminal of an adder in each unit.

The configuration of the second invention is shown in FIG. This is intended to simplify the amount of connections between each unit of the network by having a microprocessor perform the calculation of ΔWij that determines the weight of the connection and the counter 12 shown in FIG. 1. 21 is a microprocessor, 1b
data string CDAT L, 0 corresponding to “it is PX”
It performs calculations for counting the DAT 2, changing the connection weight Wij, and setting the output to the DA converter 26. Although not shown, this microprocessor includes a RAM for storing output values and a ROM for storing a series of operations (processing programs).

Further, 22 is a bidirectional bus driver for data read/write, and 24 is a counting data string CD^Tl, CD
This is a latch circuit that temporarily stores A↑2.

25 reads these counting data strings or DA
This is a decoding circuit for selecting data output from the microprocessor 21 to the conversion and latch circuit 26.

Reference numeral 30 denotes a weight circuit section, which includes a transistor 27 whose resistance value changes in a signoid pattern as Wij changes, a resistor 28 which converts the current output of the transistor into a voltage, and a comparator 2.
9. Threshold voltage source 31. and an inverter INV. 32 is a binarization amplifier for the output of the circuit section 30;
3 is a circuit that performs an AND operation between the disulfurized signals; 34 is a circuit that performs an AND operation between the reference clock CLK and the output of the AND circuit 33, and outputs data strings CDAT 1 and CDAT 2;

[Effect]

The operation of the circuit shown in FIG. 1 will be explained. According to the Boltzmann machine principle, each unit is required to:

(1) The unit has a probability P i = 1 depending on the sum of its inputs NBTi (i-1゜2,...”・n)
Fires at /exp(-Nll!Ti/T).

(2) The probability Pij (i, j −1, 2, “”n) of any two units in the network firing at the same time can be determined, and the connection weight Wlj must be able to be changed based on that value. .

(3) The temperature parameter T is variable, and it is desirable to change it quickly.

The circuit shown in FIG. 11(c) satisfies the above three conditions. That is,
The adder Add of each unit outputs the summation of inputs NETi, and the comparator COMP fires with probability Pl according to the summation.

Random noise is superimposed on the input of the adder, and the average of this noise is 01, the variance is σ: normal distribution N(0, σ
Then, the adder output Vt is V i =NETi+N
(0, a") -N (NETi, σ")...-
00, it is still a normal distribution. Comparing this Vi with θ,
If the signal is binarized so that it is on when it exceeds θ, the total time ti during which Ui is on within a sufficiently long time T is expressed by the following Gaussian integral.

At this time, ti/T is the probability Pi of unit Ui firing
become.

Although the Gaussian integral of equation 021 cannot be processed analytically, it is known to be a good approximation of the sigmoidal function shown in FIG. This first Δ
Ek/T Figure 3 represents Pm-1/(1+e), and the curve CI is the curve C! when T = 1.0. is T −0,2
5, and the curve C1 is at T-4,0. This ΔE corresponds to NETi.

Changing the temperature parameter T is achieved by changing the gain of the amplifier 15 to change the amplitude of the noise. Reducing the amplitude means decreasing T, and a curved line appears in FIG. 3. The opposite is true if the amplitude is increased.

Outputs V + , V z of units U, Uz and frequency f
.

When all the reference pulses are at H level, the frequency of the AND gate 11 becomes H level. The counter 12 counts these H level pulses during the measurement time T.

The reference pulse is a pulse that is the logical product of the outputs V, , V, and makes it possible to measure the period during which the logical product is at H level with a counter. If this count value is C, then unit U+
, the probability that Uz fires at the same time P,! is PI! -C/ f o T
""03). This probability Pl! The connection weight Wlt can be changed by determining in the learning (clamp) state and the free run state. It is the following formula % Formula % Specifically, the weight is changed by the counter amount C1! which is given based on the following formula from the counter values c and c' of the two states of clamp and free run. It is done by

CI! =ε(C-C')/f, T...
・051 counter 12 is the above C1! The DA converter 13 converts this into analog and adds it to the base of the transistor 14, and the collector and emitter of the transistor 5.
Change the resistance value between. This changes the weight WIt of the connection from U8 to U.

By repeating the configuration shown in FIG. 1(b) to create n units and their combinations, a Boltzmann machine having n units can be realized on hardware.

The operation of the circuit shown in FIG. 2 will now be described.

The principle of the Boltzmann machine is as described above, and when it is shown as n incoming units, n hidden units, and n outgoing units, it becomes as shown in FIG. Each of the n input units is called an input layer, each hidden (intermediate) unit is called a hidden (intermediate) layer, and each output unit is called an output layer. In other words, the number of units in each layer is not necessarily the same, and in this case, it is assumed that there are 4 units in the output layer and 3 units in the hidden layer.

During learning, an input pattern is input into the input layer, and the resulting pattern is also set in the output layer.In this example, each unit is 4 units, so the above pattern is a 4-bit pattern. During this operation, the amplifier 32, the AND circuit section 33, and the reference clock AND circuit section 34 shown in FIG. 2 create a data string CDAT 1 in which 1 bit becomes data of a pulse train corresponding to the coupling strength of each unit.

CDAT2 (these correspond to the output of the AND circuit 11 in FIG. 1) are counted by the processor 21, and ΔW
i j is calculated, and the DA converter 26 outputs W i j
It is output as , and stabilizes to a value somewhere in the unit group after a certain period of time. This is the state in which one learning has been completed, and after repeating this several times, the learning is completed by setting the system to a free run state and subtracting the systematic parameters. After this, if a new bit pattern is added to the input layer, the output layer will output a result according to the learned content.

In the weight circuit section 30, the transistor 27 takes a resistance value according to the weight, which is converted into a voltage by the resistor 28 and applied to the comparator 29. This has a shape as shown in FIG. 4(a). A reference value is given to the comparator 29 by a threshold voltage source 31, and the comparator output is as shown in FIG. This signal is binarized (shaped into a rectangular wave) by the amplifier 32, and becomes as shown in FIG. 4(C). This is logically ANDed in the AND circuit section 33, and then logically ANDed with the clock CLK in the AND circuit section 34, so that the pulse width is expressed by the number of clocks. This clock is a pulse train in which each bit corresponds to the coupling strength of each unit, and this is the data C-8 Tl, CDAT2.

〔Example〕

FIG. 6 shows a more specific example of FIG. 1(b).

As in all figures, parts that are the same as in other figures are given the same reference numerals. As is clear from the comparison with Figure 1,
An inverter INV is inserted between the adder Add and comparator COMP of each unit. Further, the output of the DA converter 13 is transmitted to the transistor 14 for the weight Wl- of the connection from unit Ut to Ul, and vice versa from unit U1 to U2.
The transistor 14a for the coupling weight W2° is controlled. These transistors 14.14a and adder Add
A voltage follower VF is inserted between the input terminal and the input end of the output impedance to lower the output impedance.

The threshold value θ is given by the threshold value unit Ui (output is always at H level), but there are AND gates 11b and ll on this path.
c, latch and comparator 12b.

12c, DA converter 13b, 13c,) transistor 14
b, 14c, which have the same configuration as that for weights.

The embodiment of FIG. 2 is shown in FIGS. 7 to 15. FIG. 7 shows the microprocessor 21. A bus driver 22, a latch circuit 24, and a DA conversion and latch circuit 26 are shown. The rectangular frame indicates an integrated circuit chip. The 0 circuit 26 receives data from the processor 21 and calculates the connection weight of each unit W I I HI
＋W l l H2+ ・・・・・・WOaNs+
W11□, W. . . . Outputs W, , I3 In this example, the number of units in each of the input layer, hidden layer, and output layer is 4°3.4, so the type of connection is 4X3X4, 48
There are several.

8 to 11 show specific examples of the weighting circuit section 30. FIG.

In Fig. 8, the weight Wl of the connection between the input layer and the hidden layer is 1 to W.
Input layer outputs 11 to 14 (indicated by the same reference numerals as the units; the same applies hereinafter) are generated by receiving r a M 1 and the hidden layer outputs H・1 to l(/3. Also, in FIG. 9, the same weight W1
1□~W14□ and the input layer heavy mold, ~11° are received to produce hidden layer outputs H1~H8. Moreover, in FIG. 10, the weights of the connections between the hidden layer and the output layer W 61 M l to W 64 M
3 and the output layer output o'1~0''4, the hidden layer output H
1 to H1. Furthermore, Fig. 11 shows the weight of the same connection WO
t□~W o 4 M s and hidden layer output 1411~H'
a and generates output layer outputs O1-04.

12 and 13 show the amplifier 32 and the AND gate section 33.
．． 34 specific examples, FIG. 12 shows the outputs O1~O,,H,~
In response to H3 and clock CLK, data string CDAT 2 is output, and in FIG. 13, data string CDAT 1 is output in response to outputs 1 to I1, H5 to H1 and clock CLK. Although the amplifier 32 that performs binarization is schematically shown in these figures, it is connected to the operational amplifiers OP, ~O, as shown in FIG.
It is composed of P4, shaping inverter I, -14, etc. In this circuit, the threshold value 31 is provided by a Zener diode ZD. Further, FIG. 15 constitutes a threshold voltage source 31. In FIG. An example of a random noise (white noise) generation circuit is shown. The amplitude of the output pulse of this circuit can be changed by operating a variable resistor.

The microprocessor 21 is preferably 16 bits or more, and the bus driver, latch, etc. are adapted to this.

Although the required number of 8-bit chips are used for the DA conversion and latch circuit 26, chips of other bit lengths may be used. Further, instead of converting the pulse width into the number of pulses using the clock CLK and the AND gate 34, a V-F converter may be used.

FIG. 16 shows the processing procedure programmed into the processor 21. As shown in the figure, the input commands include free run mode, clamp mode, and reset mode.

In clamp mode, Pij is calculated, and in free run mode, P'ij is calculated, and from these, ΔWij
is determined and output to the DA converter 26. In reset mode, each counter is cleared. As a result, the WijO value, which is the weight of synaptic connections, can be quantified and all the data can be summarized.

In the circuits shown in FIGS. 1 and 6, an AND gate 11, a latch and counter 12, and a DA converter 13 are provided at the coupling part of each unit.
Since there are a large number of connection parts (48 in the 4-3-4 configuration as described above), it is important to simplify this part when implementing the system into an actual device.

In this regard, according to Figure 2, the counter is the processor 2.
1 can be shared, and the amplifier 32 and logic sections 33 and 34 can be simplified. Furthermore, a new output value determined from the count value can also be realized by directly accessing the DA converter.

〔Effect of the invention〕

As described above, according to the present invention, a Boltzmann machine, which conventionally existed only as software, can be realized as hardware, thereby making it possible to dramatically increase the speed.

In addition, since the counter section and weight determination section of the Boltzmann machine composed of this hardware are substituted by the processor, the amount of network connections can be simplified, and the high-speed processor (
For example, if the frequency is 10 MHz or higher), the software speed for counting becomes faster, so the number of units that can be handled can be increased.

[Brief explanation of the drawing]

Figures 1 and 2 are diagrams explaining the principle of the present invention, Figure 3 is a characteristic diagram of a sigmoidal function, Figure 4 is a diagram explaining pulsing, and Figure 5 is an explanation of a Boltzmann machine with an n-n-n configuration. 6 is a block diagram showing the embodiment of FIG. 1, FIGS. 7 to 13 are circuit diagrams showing the embodiment of FIG. 2, FIG. 14 is a partial circuit diagram of FIG. 13, Figure 15 is a circuit diagram of the white noise generator, Figure 16 is a flowchart showing the processing procedure, Figure 17 is an explanatory diagram of a Boltzmann machine with a 4-3-4 configuration, and Figure 18 is for explaining the operation of Figure 17. This is a flowchart. W1! 11 is an AND circuit, 12 is a latch and count circuit, 13 is a DA converter, 14 is a transistor, and 30 is a weight circuit section.

Claims (2)

[Claims] 1. An adder (Add) receives random noise along with the input signal, and a comparator (CO) receives the output of the adder and a threshold voltage (θ) and fires when the former exceeds the latter.
A plurality of units (U_1, U_2, ·
), and the circuit that connects the units of the input, hidden, and output layers between the layers includes a transistor (
14) and the outputs (V_1, V
_2) and a reference pulse are input, and a gate circuit (11) converts the period during which both of the outputs are in a firing state into a pulse number, a counter (12) that counts the output pulses of the circuit, and an analog output of the counter. A DA converter (13) is connected to each transistor (
14) A Boltzmann machine type neurocomputer system comprising a neural network attached to the system. 2. Configure the input, hidden, and output layers with multiple units that take a binary output state, and set the weights (
In a Boltzmann machine type neurocomputer system equipped with a neural network connected with W_i_j), an analog input binarization circuit (30, 32, 33) changes the connection weight (W_i_j) from an analog quantity to a digital quantity.
, 34), a DA conversion and latch circuit (26), and a processor (21), the output of the binarization circuit is counted by the processor to obtain the weight increment (ΔW_i_j), and from this, the connection weight is calculated. (W_
i_j) is determined, set in the latch circuit (26), and inputted to the binarization circuit.