JPH02274139A - Data transmission system - Google Patents

Data transmission system

Info

Publication number
JPH02274139A
JPH02274139A JP1096682A JP9668289A JPH02274139A JP H02274139 A JPH02274139 A JP H02274139A JP 1096682 A JP1096682 A JP 1096682A JP 9668289 A JP9668289 A JP 9668289A JP H02274139 A JPH02274139 A JP H02274139A
Authority
JP
Japan
Prior art keywords
data
clock
pulse
nrz code
transmission signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1096682A
Other languages
Japanese (ja)
Inventor
Kunio Takada
高田 邦夫
Masashi Oba
大庭 政司
Sei Sukegawa
聖 助川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1096682A priority Critical patent/JPH02274139A/en
Publication of JPH02274139A publication Critical patent/JPH02274139A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To superimpose a clock on an NRZ code by superimposing pulsive recessed section onto the data of level 1 of an NRZ code at a transmission section and superimposing pulsive projecting sections onto the data of level '0'. CONSTITUTION:In the case of transmitting the data as the NRZ code, a pulsive clock pulse is synthesized with the NRZ code and a transmission signal as shown in figure is generated and transmitted. In this case, a recessed section A having a width corresponding to the clock pulse is formed with respect to the data of a level 1 and a projecting section B having a width corresponding to the clock pulse is formed to the data with a level 0. Thus, in the reception section, the rising point in the transmission signal is extracted to generate the clock.

Description

【発明の詳細な説明】 〔概 要〕 NRZ符号で与えられるデータを伝送するデータ伝送シ
ステムに関し。
[Detailed Description of the Invention] [Summary] This invention relates to a data transmission system that transmits data given by NRZ code.

NRZ符号に対してクロックを重畳できるようにするこ
とを目的とし。
The purpose is to enable a clock to be superimposed on the NRZ code.

送信部において、NRZ符号の値「1」のデータに対し
てパルス状の凹所を重畳し、かつ値「0」のデータに対
してパルス状の凸所を重畳する構成とする。
The transmitter is configured to superimpose a pulse-like depression on data with a value of "1" of the NRZ code, and superimpose a pulse-like protrusion on data with a value of "0" of the NRZ code.

〔産業上の利用分野〕[Industrial application field]

本発明は、NRZ符号で与えられるデータを伝送するデ
ータ伝送システムに関する。
The present invention relates to a data transmission system that transmits data given in NRZ codes.

同軸線や光ファイバ等を用いた有線伝送システムにおい
ては、伝送速度の高速化、装置の小型化消費電力の低減
化が要求されており1そのためにも回路構成の簡素化が
必要になってきている。
In wired transmission systems using coaxial lines, optical fibers, etc., there are demands for higher transmission speeds, smaller equipment, and lower power consumption.1 To achieve this, it has become necessary to simplify the circuit configuration. There is.

(従来の技術) 一般にデジタル伝送に当っては、データを伝送すると共
にクロックを伝送する必要がある。従来の場合には、N
RZの原符号から、CMr符号やAMI符号などに符号
変換壱行い、伝送路に送出する方式が採用されている。
(Prior Art) Generally, in digital transmission, it is necessary to transmit a clock as well as data. In the conventional case, N
A method is adopted in which the original code of RZ is converted into a CMr code, AMI code, etc., and then sent to a transmission path.

〔発明が解決しようとする課題] 上記従来の場合には、CMI符月やAM、I符号を用い
ているために、送信部における符号器や受信部における
復号器の回路が複雑なものであった。
[Problems to be Solved by the Invention] In the above conventional case, since CMI symbols, AM, and I codes are used, the circuits of the encoder in the transmitter and the decoder in the receiver are complicated. Ta.

本発明は、この点を解決ずべく、NRZ符号に対してク
ロックを重畳できるようにすることを目的としている。
The present invention aims to solve this problem by making it possible to superimpose a clock on the NRZ code.

〔課題を解決するための手段〕[Means to solve the problem]

第1図は本発明の原理説明図を示す。 FIG. 1 shows a diagram explaining the principle of the present invention.

本発明の場合1図示の如きNRZ符号で与えられるデー
タを伝送するに当って、パルス状のり℃】ツタ・パルス
を上記NRZ符号と合成するようにする。そL7て1図
示の如き送信信号を生成して伝送するようにする。
In the case of the present invention, 1. When transmitting data given by an NRZ code as shown in the figure, a pulse-like signal is combined with the NRZ code. L7-1 generates and transmits a transmission signal as shown in the figure.

〔作 用] 第1図図示の場合には、(ii’l」のデータ(こ対し
て、クロック・パルスに対応する幅をもつ凹所Aがつく
られ、値「0」のデータに対して1 クロック・パルス
に対応する幅をもつ凸所Bがつくられている。
[Function] In the case shown in Figure 1, a recess A having a width corresponding to the clock pulse is created for data (ii'l), and for data of value "0". 1 A protrusion B is created with a width corresponding to one clock pulse.

このために、受信部においては、第1図図示の「送信信
号」にお&Jる立上り点を抽出して、これによってクロ
ックを生成することが可能となる。
Therefore, in the receiving section, it is possible to extract the rising point of the "transmission signal" shown in FIG. 1 and generate a clock based on this.

〔実施例] 第2図は送信部の説明図であり、第2図(A)は送信部
の構成、第2図(B)は第2図(A)図示上の点の波形
を示す。
[Example] FIG. 2 is an explanatory diagram of a transmitting section, where FIG. 2(A) shows the configuration of the transmitting section, and FIG. 2(B) shows waveforms at points shown in FIG. 2(A).

図中の符号JOは送信部、11ないし16は夫hフリン
ブ・フロップ、  17−1. 17−2は夫々アンド
回路、18はナンド回路、19はオア回路を表している
。また図中の点の1■、■、■。
Reference numeral JO in the figure is a transmitter, 11 to 16 are husband-h frimb flops, 17-1. 17-2 represents an AND circuit, 18 a NAND circuit, and 19 an OR circuit. Also, points 1■,■,■ in the figure.

■は第2図(B)図示と対応している。2 corresponds to the illustration in FIG. 2(B).

合筆2図(13)図示の如きNRZ符号のデータがフリ
ップ・フロップ11のD端子に供給されるとする。第2
図(B)図示の如きデ二−テイをもつ「クロック人力」
がフリップ・フロップ13に供給され1かつ「り4」ン
ク入力」に対してn倍の周波数をもつ「1倍クロック」
が各フリップ・フロップ11ないし16に供給される0
図示の場合にはn=4の場合を表しているが、nがより
大きい値をとることが望まれる。
Assume that NRZ code data as shown in Figure 2 (13) is supplied to the D terminal of the flip-flop 11. Second
Diagram (B) "Clock human power" with the data shown in the diagram
is supplied to the flip-flop 13, and a "1x clock" having a frequency n times higher than the "link input" is supplied to the flip-flop 13.
is supplied to each flip-flop 11-16.
Although the illustrated case represents the case where n=4, it is desirable that n take a larger value.

0倍クロックにおけるパルス1個分の遅れをもゲて点■
の波形が立上り、かつパルス1個分の幅をもって点■の
波形が立下る。
The point is calculated by taking into account the delay of one pulse in the 0x clock.■
The waveform at point (2) rises, and the waveform at point (2) falls with a width of one pulse.

また0倍クロックにおけるパルス1個分の遅れをもって
点■の波形が立下り、かつパルス2個分の幅をもって点
Oの波形が立りる。
Further, the waveform at point (2) falls with a delay of one pulse in the 0x clock, and the waveform at point O rises with a width of two pulses.

このようにして得られた点■、■の波形と、パルス2個
分の遅れを与えた点■の波形とを用いて。
Using the waveforms at points ■ and ■ obtained in this way, and the waveform at point ■ which was delayed by two pulses.

アンド・オアの論理をとることによって2点■の波形が
得られ1 フリップ・フロップ16によって整形が行わ
れて1点■の波形として示す如き送信信号が得られる。
By performing the AND-OR logic, a waveform of two points (2) is obtained, which is then shaped by the flip-flop 16 to obtain a transmission signal as shown as a waveform of one point (2).

第3図は受信部の説明図であり、第3図(A)は受信部
の構成、第3図(B)は第3図(A)図示上の点の波形
を示す。
FIG. 3 is an explanatory diagram of the receiving section, with FIG. 3(A) showing the configuration of the receiving section, and FIG. 3(B) showing waveforms at points shown in FIG. 3(A).

図中の符号20は受信部、21はフリップ・フロップ、
22は遅延回路、23はノット回路24はアンド回路、
25は濾波器、26は矩形波生成回路を表(−でいる。
In the figure, 20 is a receiving section, 21 is a flip-flop,
22 is a delay circuit, 23 is a NOT circuit 24 is an AND circuit,
25 is a filter, and 26 is a rectangular wave generation circuit.

なお1図示遅延回路22とノット回路23とアンド回路
24とは微分回路を形成している。
Note that the delay circuit 22, NOT circuit 23, and AND circuit 24 shown in FIG. 1 form a differentiating circuit.

今図示の如き入力信号が与えられたとする。人力信号の
立下−りに対応し2て1点■の波形としてパルスかつ(
られる。当該パルスが濾波器25に供給されて1点■の
波形として示す如き正弦波が生成され、矩形波生成回路
26によって図示の如きデューティをもつ矩形波が生成
される(点■の波形)。
Assume that an input signal as shown in the figure is given. Corresponding to the falling edge of the human input signal, the pulse and (
It will be done. The pulse is supplied to the filter 25 to generate a sine wave as shown in the waveform at one point (2), and the rectangular wave generation circuit 26 generates a rectangular wave having the duty as shown (waveform at point (2)).

点■の波形として示す矩形波の立下り点を用いて、入力
信号がフリップ・フリップ21にセントされる。即ち1
図示の場合、データrl、0.00.1・・・」が解読
される。
The input signal is sent to the flip-flip 21 using the falling point of the rectangular wave shown as the waveform at point 2. That is, 1
In the illustrated case, data rl, 0.00.1...'' is decoded.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く1本発明によれば、送信部や受信部に
おける回路構成が大幅に簡素化される。
As explained above, according to the present invention, the circuit configurations of the transmitting section and the receiving section are significantly simplified.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理説明図、第2図は送信部の説明図
、第3図は受信部の説明図を示す。 図中の符号IOは送信部、20は受信部を表す。
FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is an explanatory diagram of a transmitter, and FIG. 3 is an explanatory diagram of a receiver. The symbol IO in the figure represents a transmitter, and 20 represents a receiver.

Claims (1)

【特許請求の範囲】 NRZ符号で与えられるデータを送信する送信部(10
)と、当該データを受信する受信部(20)とをそなえ
たデータ伝送システムにおいて、 上記送信部(10)において、上記NRZ符号で与えら
れるデータに対してパルス状のクロック・パルスを合成
し、値「1」のデータに対して当該データ内に上記クロ
ック・パルスに相当する幅の凹所を形成すると共に、値
「0」のデータに対して当該データ内に上記クロック・
パルスに相当する幅の凸所を形成した送信信号を送出す
るよう構成され、 かつ上記受信部(20)において、受信された上記送信
信号に対して、信号の立下り点を抽出してクロックを生
成すると共に、当該生成されたクロックにもとづいて上
記受信された送信信号をデコードするよう構成された ことを特徴とするデータ伝送システム。
[Claims] A transmitting unit (10
) and a receiving unit (20) that receives the data, in the transmitting unit (10), synthesizing a pulse-like clock pulse with the data given by the NRZ code, For data with a value of "1", a recess with a width corresponding to the clock pulse is formed in the data, and for data with a value of "0", a recess with a width corresponding to the clock pulse is formed in the data.
It is configured to send out a transmission signal in which a convex portion with a width corresponding to a pulse is formed, and the reception section (20) extracts a falling point of the received transmission signal and clocks it. A data transmission system characterized in that the data transmission system is configured to generate a clock and decode the received transmission signal based on the generated clock.
JP1096682A 1989-04-17 1989-04-17 Data transmission system Pending JPH02274139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1096682A JPH02274139A (en) 1989-04-17 1989-04-17 Data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1096682A JPH02274139A (en) 1989-04-17 1989-04-17 Data transmission system

Publications (1)

Publication Number Publication Date
JPH02274139A true JPH02274139A (en) 1990-11-08

Family

ID=14171563

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1096682A Pending JPH02274139A (en) 1989-04-17 1989-04-17 Data transmission system

Country Status (1)

Country Link
JP (1) JPH02274139A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637743A (en) * 1992-04-22 1994-02-10 Sony Tektronix Corp Serial data receiver
JP2010021626A (en) * 2008-07-08 2010-01-28 Fujitsu Ten Ltd Data communication apparatus
US7664168B2 (en) 2004-11-09 2010-02-16 Canon Kabushiki Kaisha Data carrier device, data carrier driving device, data communication system using data carrier driving device and data communication method
US7734940B2 (en) 2006-04-18 2010-06-08 Canon Kabushiki Kaisha Data communication device has data signal generation circuit and transmission circuit on basis of reference voltage and received signal
JP2015504635A (en) * 2011-11-16 2015-02-12 クゥアルコム・インコーポレイテッドQualcomm Incorporated Apparatus and method for recovering burst mode pulse width modulation (PWM) and non-zero return (NRZ) data

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637743A (en) * 1992-04-22 1994-02-10 Sony Tektronix Corp Serial data receiver
US7664168B2 (en) 2004-11-09 2010-02-16 Canon Kabushiki Kaisha Data carrier device, data carrier driving device, data communication system using data carrier driving device and data communication method
US7734940B2 (en) 2006-04-18 2010-06-08 Canon Kabushiki Kaisha Data communication device has data signal generation circuit and transmission circuit on basis of reference voltage and received signal
JP2010021626A (en) * 2008-07-08 2010-01-28 Fujitsu Ten Ltd Data communication apparatus
JP2015504635A (en) * 2011-11-16 2015-02-12 クゥアルコム・インコーポレイテッドQualcomm Incorporated Apparatus and method for recovering burst mode pulse width modulation (PWM) and non-zero return (NRZ) data
US9270287B2 (en) 2011-11-16 2016-02-23 Qualcomm Incorporated Apparatus and method for recovering burst-mode pulse width modulation (PWM) and non-return-to-zero (NRZ) data

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