JPH02273968A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the number of processes after the issuance of writing command by performing writing by turning an MOS transistor into a depletion type. CONSTITUTION:An MOS transistor composed of a gate 5 and an N-type source/ drain region 6 is formed in an element region 2 isolated by a dielectric isolation layer 3 on one surface of a semiconductor substrate 1 doped with P-type impurity. On the whole surface of the substrate 1, an insulating film composed of, e.g. SiO is formed, and an aperture 7 is formed in said insulating layer 8. In the semiconductor substrate 1 exposed in the aperture 7, N-type impurity is additionally introduced by, e.g. ion implantation. Hence a low concentration region 6A is turned into a high concentration region 6B, and the MOS transistor is converted to a depletion type, which is subjected to writing. Thereby the number of processes after the issuance of writing command can be reduced.

Description

[Detailed description of the invention] [overview] Regarding NAND type mask ROM.

The purpose is to be able to provide mask ROM products in a short delivery period.

An insulated gate is formed in each of a plurality of element regions arranged in a matrix on a semiconductor substrate of one conductivity type, and a low concentration of an opposite conductivity type is formed near at least one of both edges along the extending direction of the insulated gate. forming a source region and a drain region in each of the device regions, the source region and the drain region facing each other with the insulated gate and the low concentration region therebetween and containing impurities of opposite conductivity type at a higher concentration than the low concentration region; forming an insulating layer on the semiconductor substrate in which the source region, the drain region, and the low concentration region are formed; an opening located on the low concentration region and in contact with at least the insulated gate; The method includes the steps of forming an impurity in the insulating layer in a predetermined element region and introducing an impurity of an opposite conductivity type into the semiconductor substrate exposed in the opening.

[Industrial application field]

The present invention relates to a semiconductor device, particularly a mask ROM (Rea
(only memory), which involves a method of manufacturing multiple MOS devices arranged in a matrix on a semiconductor substrate.
) has a transistor as a memory cell and has a MOS on the same column.
The sources and drains of the transistors are connected in series, the gates of the MOS transistors on the same row are connected to the same word line, and only the MOS transistors constituting the write cell are depletion type. This invention relates to a mask ROM writing method.

[Conventional technology]

At present, mask ROMs of 4 Mbits or more use a NAND type structure that can easily be highly integrated. Namely.

As shown in Figure 3, among a plurality of MOS transistors arranged in a matrix, the MOS transistors on the same column
S) The sources and drains of the transistors are connected in series, and the MOS transistors are on the same row.) The gates of the transistors are connected to the same word line (tag), and the MOS transistors correspond to a predetermined write cell.) Only the transistors are formed in a depression type. be done.

For reading, 9 For example, if the above MO3) transistor is an n-channel type, set the unselected word line (tag) to a high level, and
This is done by setting the M word line (ridge) to a low level. For example, when the word line tag is selected, if Q and t of the MOS transistors whose gates are connected to the word line are depletion type, +
Bit line R to which the source/drain of Ql□ is connected
Power supply voltage VDD appears at Lt.

The power supply voltage V does not appear on the other bit lines.

In this way, write cells, ie, □, are successively written.

[Problem to be solved by the invention]

Normally, a mask ROM is manufactured after write data is determined. Therefore, efforts are being made to simplify processes and improve structures in order to shorten delivery times.

The above NAND type mask RQ? MOS that constitutes f)
An n-channel transistor is used as the transistor. Conventionally, a writing method has been used in which ions of mainly arsenic (^S) are implanted as an n-type impurity into the channel region directly under the gate of a MOS transistor corresponding to a writing cell to convert it into a depletion type.

Since n-type impurity ions such as ^S generally have a small range (Rp), it is difficult to implant them through a gate made of polysilicon or the like. therefore.

Prior to the step of forming the gate, it was necessary to ion-implant the required impurities. For this purpose, formation and patterning of the conductive layer for the gate.

Many processes, including the formation of source/drain regions, must be performed after an instruction to write data to the mask ROM is given, making it difficult to respond to urgent demands.

In view of the above-mentioned conventional problems, an object of the present invention is to disclose a manufacturing method that makes it possible to provide mask ROM products in a shorter delivery period than conventionally.

[Means to solve the problem]

The above object is to - form an insulated gate in a defined device region on a semiconductor substrate of a conductivity type; a step of forming a doped region in the element region; and a step of forming a source region and a drain region which are opposite to each other with the insulated gate and the low doped region in between and contain impurities of opposite conductivity type at a higher concentration than the lightly doped region. a step of forming an insulating layer on the semiconductor substrate on which the source region, the drain slope, and the low concentration region are formed; According to the present invention, the method includes the steps of: forming a contacting opening in the insulating layer in a predetermined element region; and introducing an impurity of an opposite conductivity type into the semiconductor substrate exposed within the opening. This is achieved by a method for manufacturing a semiconductor device.

[For production]

In the present invention, enhancement type MOS I-transistors each having a lightly doped drain region are formed in a matrix on a substrate as a memory cell in the NAND mask ROM, and based on a write instruction,
By selectively introducing impurities into the low concentration drain region of a predetermined MO3) transistor to increase the concentration, it is converted into a depletion type transistor. A MOS transistor having a lightly doped drain region as described above is used, for example, as a high voltage transistor in a peripheral circuit of an EFROM, and can be formed using this technology.

The principle of the present invention will be explained with reference to FIG.

In the same figure, (a) shows a MOS transistor corresponding to a non-written cell, and (b) shows a MOS transistor corresponding to a written cell, in a state where writing has been performed according to the present invention.

First, the MOS l-transistor corresponding to the write cell will be explained. Referring to Figure 1(a), 1 normal M
Similar to the manufacturing process of OS l-transistors, 9 e.g. P
A MOS comprising a gate 5 and an n-type source/drain region 6 is placed in an element region 2 separated by an isolation insulating layer 3 on one surface of a semiconductor substrate 1 doped with type impurities.
) a transistor is formed. Reference numeral 4 indicates a gate insulating film. Then cover the entire surface of board 1.

For example, an insulating layer 8 made of 5t(h) is formed.

The above-mentioned MOS transistor has an n-type low concentration region (low concentration drain region) 6A formed close to one edge of the gate 5 in the extending direction (perpendicular to the plane of the paper), and is of an enhancement type. , width to low concentration region 6 (-)
and depth (D) and impurity concentration.

Further, the concentration of the p-type impurity in the semiconductor substrate 1, the gate length, the impurity concentration of the source/drain region 6, etc. are determined.

In the case of the MOS transistor corresponding to the write cell,
As shown in FIG. 1 (0)), when the formation of the insulating layer 8 is completed, an open lower portion is formed in the insulating layer 8 on the low concentration region 6^, and the semiconductor substrate 1 is exposed in the open lower portion. 1. An n-type impurity is additionally introduced, for example, by ion implantation. As a result, the low concentration region 6A becomes a high concentration region 6B, and the MOS
The l-transistor is converted to depression type. That is, writing is performed.

A low concentration region corresponding to the low concentration region 6A is also formed at the other edge of the gate 5, and a MOS corresponding to the write cell is formed.
) Regarding the transistor, an open lower layer may be formed and an n-type impurity may be introduced into the insulating layer on both low concentration regions in the same manner as described above. This structure in which low concentration regions are provided at both edges is an advantageous method for obtaining a deep depression type.

As described above, in one aspect of the present invention, the MOS for storage cells is placed on the wafer before the instruction to write mask ROM data is given.
) can form a transistor matrix,
Moreover, this wafer surface can be protected by an insulating layer used as a mask for introducing write impurities.

Therefore, compared to the conventional writing method in which impurities are introduced into the channel region directly under the gate, the number of steps after writing instructions is significantly reduced, and the delivery time can be shortened. Furthermore, the process leading to the completion of gate formation is MO
S) It is the same as that of a normal integrated circuit consisting of a transistor, and as mentioned above, the process unique to mask ROM is located at the rear of all processes, so the number of post-processes is reduced, and as a result, the product yield is reduced. It is also effective for improvement.

〔Example〕

Embodiments of the present invention will be described below in comparison with the conventional writing method. Figure 2 shows the process of the present invention.

FIG. 4 shows the steps when using the conventional writing method.

In these figures, the same parts as in the previous drawings are designated by the same reference numerals.

For example, using the well-known LOCO5 method, as shown in FIG. 2(a), an isolation insulating layer 3 for isolating element regions 2 defined in a semiconductor substrate 1 made of a p-type silicon wafer is formed. Next, the surface of the semiconductor substrate 1 exposed within the element region 2 is thermally oxidized to form a gate insulating film 4 made of Sin. The steps up to this point are the same as the conventional steps explained in FIG. 4 below. Note that p in the semiconductor substrate 1
The type impurity concentration is IQI5C11-! Order degree theal.

Next, the entire surface of the semiconductor substrate 1 is subjected to 9, for example, a well-known CVD process.
A polysilicon layer is deposited using a method using a polysilicon method, and this is patterned using a well-known glue technique to form a gate 5 as shown in FIG. 2(b).

Then, using the gate 5 as a mask, a low concentration of n-type impurity is introduced into the surface of the semiconductor substrate 1 exposed in the element region 2. For example, As as an n-type impurity is ion-implanted to a concentration on the order of 1QI6cm-''.At this time, the implantation depth is several tens of
Set the ion energy to be human.

Next, as shown in FIG. 2(C), the surface of the semiconductor substrate 1 in a region close to one side edge of the gate 5 is examined.

For example, while masking with a resist layer 11, a high concentration of n-type impurity is introduced into the semiconductor substrate l exposed in the element region 2. For example, ^S as an n-type impurity IQ20cn+-'
Ions are implanted to a concentration of about the order of magnitude. At this time, the ion energy is set so that the implantation depth is about 1000. In addition, in FIG. 2(C), the reference numeral 6A' is the low concentration n-type region.

As a result, as shown in FIG. 2(b), only the region masked by the resist layer 11 is replaced by the low concentration region 6.
The regions remaining as A and exposed from the resist layer 11 become highly doped source/drain regions 6. In this way, an enhancement type n-channel MO transistor (5) having a lightly doped drain region 6A is formed in each element region 2. That is, the source/drain regions 6 face each other with the gate 5 and the low concentration region 6^ in between.

Note that the low concentration region 6A may also be formed on the other side edge of the gate 5 in the same manner as described above.

Next, using 9, for example, a well-known CVD technique, a layer 9 of, for example, Sing is applied to the entire surface of the semiconductor substrate 1 to a thickness of about 0.2 μm.
An insulating layer 8 of m is formed. And corresponds to the write cell? fO5) For the transistor, an open lower is formed in the insulating layer 8 above the low concentration region 6^ using a well-known lithography technique. The open lower is formed at least in contact with the gate 5. In the same figure.

A part of the open lower part overlaps with gate 5. Also.

When the low concentration regions 6A are provided on both side edges of the gate 5 as described above, an open lower is formed in the insulating layer 8 on both low concentration regions 6A.

After the above, using the insulating layer 8 as a mask, an n-type impurity for writing is introduced into the semiconductor substrate 1 exposed in the open lower portion. The introduction of this write impurity.

f! For AL, As is ion-implanted to the same concentration as the source/drain. After this ion implantation, the semi-conductive substrate 1 is heat treated at about 900° C. for about 20 minutes in an oxygen atmosphere. As a result, as shown in FIG. 2(e), the low concentration region 6A becomes a high concentration region 6B due to the impurity for writing, and the MOS transistor is converted into a depletion type transistor.

After that, a glabellar insulating layer 9 with a thickness of about 0.5 μm is formed on the entire surface of the semiconductor substrate 1 using, for example, the well-known CVD technique. Contact holes for connecting an electrode to drain region 6 are provided in insulating layers 8 and 9, and on insulating layer 9.

For example, a conductive layer of aluminum (AI) is deposited.

This is patterned to form gate electrodes, source/drain electrodes, and wiring to complete the mask ROM of the present invention.

Note that, like PSG, the interlayer insulating layer 9 contains as a component *(P), which becomes an n-type impurity in silicon.
In the case of using the ion implantation for writing in the step of FIG. 2(b), the interlayer insulating layer 9 is formed and heat treated as shown in FIG. 2(e). By diffusing phosphorus (P) into the exposed semiconductor substrate 1, the high concentration region 6B can be formed.

In the above, the insulating layer 8 made of SiO□ and the glabellar insulating layer 9 made of PSG are also provided in a normal semiconductor device. Therefore, these insulating layers 8
and 9, the number of man-hours does not increase compared to the conventional method. In the present invention, a step for forming an open lower layer in the insulating layer 8 is added, but this is a soger rough technique and has little effect on the increase in the number of steps.

On the other hand, in the conventional process, immediately after forming the gate insulating film 4 as shown in FIG. 4(a).

As shown in FIG. 4(b), it becomes a write cell. IOS
) Using a resist mask 11 provided with an opening corresponding to the element region 2 of the transistor, ions of 1, for example, arsenic (As) are implanted as an n-type impurity into the 1-open lower region. ÷It is possible to complete the process before the writing instruction is issued.

In the above embodiments, a case where the present invention is applied to the manufacturing of a mask ROM has been explained, but the method of the present invention can also be applied to an element used for management like a sea urchin fly, or to replace a defective element or circuit. It is also applicable to elements for selecting redundant circuits.

After the above, in the same manner as in the present invention, a gate 5 is formed as shown in FIG.
As shown in d), source/drain regions 6 are formed and 9
Then, as shown in FIG. 4(e).

Similar to the present invention, the first insulating layer 8 made of SiO□, the second insulating layer 9 made of PSG, etc. are formed.

In the conventional process, an open lower part is not formed.

As is clear from comparing Figure 4 with Figure 10.

Conventionally, it was necessary to perform many steps such as the formation of the gate 5 and the formation of the insulating layer 8, which took a relatively long time, after the writing instruction. According to MOS, the mask RO is written by making the transistors depletion type.
In manufacturing M, by reducing the number of steps performed after a write instruction, the delivery time of the mask ROM can be shortened compared to the conventional method, and the manufacturing yield can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a detailed explanatory diagram of the present invention. FIG. 3 is an equivalent circuit diagram of a MOS transistor array constituting a NAND type mask ROM. Figure 4 shows a NAND mask RO using the conventional writing method.
It is a manufacturing process explanatory diagram of M. In fig. 1 is a semiconductor substrate, 2 is an element area. 3 is an isolation insulating layer, and 4 is a gate insulating film. 5 is the gate, 6 is the source/drain region. 6A and 68' are low concentration areas, and 6B is high concentration areas. 7 is an opening, 8 is an insulating layer, and 9 is an insulating layer between the eyebrows. It is. Japanese map 2 (T no 2) Figure 4 (Zono 2) Z.

Claims (1)

[Claims] A step of forming an insulated gate in an element region defined on a semiconductor substrate of one conductivity type; forming a doped region in the device region; and forming a source region and a drain region which are opposite to each other with the insulated gate and the lightly doped region in between and contain impurities of opposite conductivity type at a higher concentration than the lightly doped region. forming an insulating layer on the semiconductor substrate on which the source region, the drain region, and the low concentration region are formed; Manufacturing a semiconductor device comprising: forming an aperture in contact with the insulating layer in a predetermined element region; and introducing impurities of opposite conductivity type into the semiconductor substrate exposed within the aperture. Method.