JPH02271669A - Semiconductor laminated structure and semiconductor device including same - Google Patents

Abstract

PURPOSE:To form a graded junction type hetero junction type hetero junction by forming a graded layer into a periodic laminate structure of two or more kinds of a binary compound semiconductor layers each of which takes as ingredients constituent elements of a semiconductor layer A and a semiconductor layer B, and altering the period of the periodic laminate structure. CONSTITUTION:For an InAs layer 2 and a GaAs layer 3, lattice matching with InP is taken into consideration, and the ratio of the layer number therebetween is kept at a predetermined one (1:1) such that they exhibit an equivalent crystal layer to In0.5As. More specifically, the layer number ratio in the In0.5Ga0.5As layer in which the InP layer, the InAs layer, and the GaAs layer are laminated, is progressively altered, whereby there is formed a graded layer in which the composition is changed from the InP to In0.5Ga0.5As. Further, a tetra mixed crystal semiconductor layer can be formed, which has a composition corresponding to In0.6Ga0.4As0.8P0.2, by alternately laminating three InP layers, one InAs layer, and one GaAs layer and by alternately laminating In0.8Ga0.2As0.6P0.6, or InP layer, two InAs layers, and two GaAs layer. Hereby, a graded junction type hetero junction improved in composition uniformity is yielded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor stacked structure and a semiconductor device using the same.

(Prior art) Compound semiconductors and mixed crystal semiconductors have high electron mobility.
It has characteristics that are not found in single-element semiconductors such as Si and Ge, such as new physical phenomena caused by a unique energy band structure that has a light-emitting function.
It is attracting attention as a material for ultra-high-speed processing elements, ultra-high frequency oscillation elements, and optoelectronic elements.

In recent years, research and development has been particularly active on bipolar transistors and field effect transistors that utilize heterojunctions.

Semiconductor layers for manufacturing these semiconductor elements are usually formed by molecular beam epitaxy (hereinafter referred to as MBE method) or metal organic vapor phase epitaxy (hereinafter referred to as MOVPE method). When forming a heterojunction with these, GaA
Except for exceptional combinations such as S and AlGaAs, in which the lattice constants are essentially the same and there is no need to give much consideration to lattice matching, it is necessary to match the lattice constants in order to prevent the occurrence of misfit dislocations. For this purpose, combinations of binary compound semiconductors and ternary mixed crystal semiconductors such as InP and InGaAs, or GaAs and InGaP, or A
Combinations of ternary mixed crystal semiconductors such as lInAs and InGaAs and other ternary mixed crystal semiconductors are often used.

When the above-mentioned heterojunction interface is a tilted junction type, in order to gradually change the crystal composition while maintaining lattice matching,
A transition region (hereinafter referred to as graded layer) is formed. - As an example, Fig. 4 shows InP and Ino, 53GaO,
A schematic diagram of a tilted junction type heterojunction in which 47As is bonded is shown. In Figure 4, 8n□, 53G on two InP layers
a□, In1 x GaX Asl between the 47As layer 30
A graded layer 29 made of -, P, is formed. This graded layer 29 has In and Ga in the atomic plane of group III elements, and P and AS7 in the atomic plane of group V elements.
5 (characterized by the fact that they are mixed, and the composition is controlled by controlling their atomic ratio, and lattice matching is achieved.In fact, the above-mentioned graded When forming a layer, a method is used in which the flux ratio of molecular beams of the constituent elements or the partial pressure ratio of the raw material gas containing the constituent elements is controlled and continuously changed.

(Problems to be Solved by the Invention) A graded layer formed when a binary compound semiconductor and a ternary mixed crystal semiconductor are formed into a heterojunction is often a quaternary mixed crystal semiconductor. Therefore, in order to continuously change the crystal composition while maintaining lattice matching, it is necessary to strictly control the composition ratio of three group III elements or two groups of group III and V elements. This is one of the factors that makes it extremely difficult to control the force shield ratio.

In addition, depending on the combination of semiconductor materials, the grown layer may undergo layer separation, creating a miscibility gap, or even if no clear layer separation occurs, microscopically non-uniform distribution or local composition changes may occur. Different small groups (clusters) may occur. Naturally, such a raster causes a decrease in carrier transport efficiency, running characteristics, and lifetime, and has a negative effect on the electrical and optical properties of the crystal. Therefore, when used in semiconductor devices, this is one of the factors that deteriorates the static characteristics and high-speed/high-frequency characteristics of the device, and also reduces the uniformity of characteristics between semiconductor devices within the wafer. This is also one of the factors.

An object of the present invention is to provide a tilted heterojunction type heterojunction in which such problems are solved and composition controllability and composition uniformity are improved, and a formation method for realizing the same. be.

(Means for Solving the Problem) A semiconductor layer A consisting of a binary compound semiconductor layer or a ternary or more multi-component mixed crystal semiconductor layer and a semiconductor layer B consisting of a ternary or more multi-component mixed crystal semiconductor layer form a graded layer. In a semiconductor laminated structure having a heterojunction in contact with each other through a semiconductor layer, the graded layer is a periodic laminated structure of two or more types of binary compound semiconductor layers whose components are the constituent elements of the semiconductor layer A and the semiconductor layer B, and the periodic The present invention provides a semiconductor stacked structure characterized in that the period of the stacked structure changes.

The semiconductor layer A is composed of a first semiconductor layer made of a first binary compound semiconductor, and the semiconductor layer B is a ternary mixed crystal whose constituent materials are a second binary compound semiconductor and a third binary compound semiconductor. In the case of a semiconductor, the periodic stacked structure includes a first semiconductor layer, a second semiconductor layer made of a second binary compound semiconductor - a third semiconductor layer made of a third binary compound semiconductor, or a first semiconductor layer. It is preferable to include a laminated structure composed of one of a semiconductor layer, a third semiconductor layer and a second semiconductor layer in this order. Alternatively, first semiconductor layer-second semiconductor layer-first
It may include a stacked structure configured in any one of the following order: a semiconductor layer - a third semiconductor layer, or a first semiconductor layer - a third semiconductor layer - a first semiconductor layer - a second semiconductor layer. good. It is also good to include a stacked structure consisting of a second semiconductor layer and a third semiconductor layer.

When the above-described semiconductor laminated structure is used in a semiconductor device, it is possible to obtain excellent electrical properties and optical properties, and uniform properties among the devices.

Three examples of forming methods are shown below as methods for realizing the heterojunction of the present invention.

The first formation method includes a semiconductor layer A made of a first binary compound semiconductor, and a semiconductor layer made of a ternary mixed crystal semiconductor made of a second binary compound semiconductor and a third binary compound semiconductor. A method for forming a heterojunction in which B is connected, wherein a second semiconductor comprising a predetermined number of layers of the second binary compound semiconductor is formed on a first semiconductor layer comprising the first binary compound semiconductor. a first step of forming a layer, a second step of forming a third semiconductor layer made of the third binary compound semiconductor in a predetermined number of layers on the second semiconductor layer, a third step of forming a predetermined number of the first semiconductor layers on the semiconductor layer; and a ratio of the number of layers of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer. and a fourth step of repeating the first step, the second step, and the third step at least once while changing the method.

In addition, the second formation method includes a semiconductor layer A made of a first binary compound semiconductor, and a ternary mixed crystal semiconductor made of a second binary compound semiconductor and a third binary compound semiconductor. A method for forming a heterojunction in which a semiconductor layer B is connected, wherein a second semiconductor layer made of a predetermined number of layers of the second binary compound semiconductor is formed on a first semiconductor layer made of the first binary compound semiconductor. a first step of forming a semiconductor layer;
a second step of forming a predetermined number of the first semiconductor layers on the semiconductor layer; and a third step of forming a predetermined number of the third binary compound semiconductor layers on the first semiconductor layer. a third step of forming a semiconductor layer; a fourth step of forming a predetermined number of the first semiconductor layers on the third semiconductor layer;
the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer;
a fifth step of repeating the first step, the second step, the third step, and the fourth step at least once by changing the ratio of the number of semiconductor layers of the semiconductor layer. .

Further, the third formation method includes a semiconductor layer A made of a first binary compound semiconductor, and a ternary mixed crystal semiconductor made of a second binary compound semiconductor and a third binary compound semiconductor. A method for forming a heterojunction in which a semiconductor layer B is connected, wherein a predetermined number of layers of a first semiconductor layer made of the second binary compound semiconductor are formed on the first semiconductor layer made of the first binary compound semiconductor. 2 and a third semiconductor layer made of a predetermined number of layers of the third binary compound semiconductor to form a fourth semiconductor layer with a predetermined number of layers.
a second step of forming a predetermined number of the first semiconductor layers on the fourth semiconductor layer; a second step of forming the first semiconductor layer in the first semiconductor layer and the fourth semiconductor layer; By changing the ratio of the number of layers of the second semiconductor layer and the third semiconductor layer, the first
and a third step of repeating the second step at least once.

(Function) In general, there are many unknowns about the basic physical properties of mixed crystal semiconductors formed by artificially stacking binary compound semiconductor layers of atomic layer order alternately, but they are not necessarily different from those of conventionally structured mixed crystal semiconductors. It cannot be said that they are the same. however,
Since the basic physical properties of crystals are due to a wide range of periodic atomic arrangements, it is necessary to consider a relatively large volume containing many atoms, and therefore the carriers involved in this also have a certain degree of spread (de Broglie). wavelength). For example, the de Broglie wavelength of electrons involved in band edge absorption and light emission is several hundred angstroms at room temperature, and the number of atoms included in this wavelength is about 106. In other words, even if a crystal has a microscopically regular atomic arrangement, these are normally sufficiently averaged and reflected in the macroscopic basic physical properties.

FIG. 1 shows Ir1P shown for detailed explanation of the present invention.
FIG. 2 is a schematic diagram of a tilted heterojunction in which In□, 5Ga□, and 5As are joined. Compared to the conventional method shown in Figure 4, it is characterized in that only one type of atom exists in the atomic plane of group III elements and in the atomic plane of group V elements, and Control is performed by InP layer 1, InAs layer 2 and Ga
The important point is that this is done by controlling the ratio of the number of As layers 3. In this case, the InAs layer 2 and the Ga
The As layer 3 is made of In□,5 in consideration of lattice matching with InP.
The ratio of the number of layers is kept constant (1:1) to provide crystal layers equivalent to Ga□ and 5As. In other words, InP layer, InAs layer, and GaAs layer are laminated together.
By gradually changing the ratio of the number of layers of , 5Ga□, and 5As, a graded layer whose composition is changed from InP to Ino, 5Ga□, and 5As is formed.

In Figure 1, in order to have the properties of a conventional heterojunction that corresponds to a sufficiently averaged composition,
It is necessary to make the thickness of the semiconductor layer serving as a structural unit sufficiently smaller than the de Broglie wavelength described above. This condition can be fully satisfied by setting the number of layers to several. Also, as a result, the thickness of the semiconductor layer can be changed between InP and InP.
As, InAs and GaAs, or GaAs and InP
The film thickness is set to a value sufficiently smaller than the critical film thickness at which misfit dislocations occur at the heterojunction interface with the substrate, and deterioration of crystallinity due to the occurrence of dislocations can be prevented. Thus, for example, InF3 layer, InAs and G
By laminating one layer each of aAs, In□, gG
a□, 2AS0.6P0.6, InF3 layer, In
By laminating two layers each of As and GaAs in each layer, I
A quaternary mixed crystal semiconductor layer with a composition corresponding to nO, 6Ga0.4AS0.8P0.2, or InAs and GaAs 1
InO, 5Ga□, 5
It is possible to form a ternary mixed crystal semiconductor layer having a composition corresponding to As.

Figure 5 shows In1-XGaxAsl which is lattice matched to InP.
FIG. 2 is a diagram showing the crystal composition of a yPy quaternary mixed crystal semiconductor.

To explain using FIG. 5, by using the method of the present invention, InP layers and semiconductor layers consisting of a stack of InAs layers and GaAs layers are alternately stacked, and the ratio of the number of layers is ao: With a crystal having b□, it is possible to realize an In1-xGaxAsl, P, quaternary mixed crystal semiconductor corresponding to the composition at the Q point. And layer number ratio ao:b
By gradually changing □, a mixed crystal with an arbitrary composition on the solid line in the figure can be realized, and along the solid line, that is, always I
A graded junction type heterojunction can be formed in which the composition is changed from InP to InGaAs while maintaining lattice matching to nP.

As described above, if the method of the present invention is used, since only one type of element exists in each of the atomic planes of group III elements and group II elements, it is possible to suppress the occurrence of compositional heterogeneity such as clusters. . Moreover, semiconductor layers whose lattice is essentially matched (InP and In□ in Fig. 1,
Since a Peter junction is formed by laminating layers of 5Ga□, 5AS), lattice misalignment does not occur in the graded layer.

In addition, in FIG. 1, the graded layer is an InP layer-InA layer.
In the above description, the layer is laminated in the order of J layer-GaAs layer, but the invention is not limited to this, and the layer layer is laminated in the order of InP-GaAs-InAs, and
Layer - GaAs layer or InP layer - GaAs layer - InP
The same effect can be obtained for a structure in which the layers are stacked in the order of -InAs layer, or a structure in which an InP layer and a semiconductor layer formed by alternately stacking InAs layers and GaAs layers are stacked.

In addition, one of the binary compound semiconductors constituting the ternary mixed crystal semiconductor, such as the combination of GaAs and AlGaAs (
In this case, GaAs) is the same as the other binary compound semiconductor forming the heterojunction, the first semiconductor layer is a GaAs layer, the second and third semiconductor layers are an AlAs layer and a GaAs layer, respectively. The invention can be similarly applied by considering the layers.

(Example) Next, the present invention will be explained using the drawings.

FIG. 2 is a sectional view of a grown crystal for explaining the first embodiment of the present invention, and shows a case where the present invention is applied to a buffer layer.

In FIG. 2, a buffer layer 31 of about 370 OA is formed on a semi-insulating substrate 4 made of Fe-doped InP.
Furthermore, 5000 S-doped n-In□, 53
A Ga□, 47As layer 16 is formed. The (111)B plane was used as the plane orientation of the substrate. This buffer layer is formed by periodically stacking an undoped 1-InP layer, an undoped 1-InAs layer, and an undoped 1-GaAs layer, and by controlling the ratio of the number of these layers,
The composition was changed in stages to form a graded layer as a whole. The layer structure of the buffer layer is shown below.

In this case, for example, 1-In□, 7Ga□, 3As□, 6
P□, 4 layers 11 are InP 4 layers-InAs 1 layer-GaA
s1 layer-InAs1 layer-GaAs1 layer-InAs1 layer-
One structural unit was formed by laminating one layer of GaAs in this order, and it was formed by stacking eight such structural units.

Each semiconductor layer was formed using a hydride vapor phase growth apparatus by atomic layer epitaxy (hereinafter referred to as ALE method) at a substrate temperature of 350°C. This method is described, for example, by A. Usi et al.
, Japanese Journal of Applied Fixtures
pplied Physics), Vol. 25, 1986, p. L212. Also, n-In0.5
The 3Ga0.47AS layer 16 was formed at a substrate temperature of 600° C. by a normal hydride vapor phase epitaxy method (hereinafter referred to as hydride VPE method).

n-In□, 53Ga□, 47As obtained above
Layer 16 had significantly fewer misfit dislocations than those obtained by the conventional method, and had a very good surface condition.

FIG. 3 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention, and shows a case where the present invention is applied to the formation of a pn junction.

In FIG. 3, a buffer layer 18 having a layer structure similar to that shown in the first embodiment is formed on a semi-insulating substrate 17 made of Fe-doped InP. The (111)B plane was used as the plane orientation of the substrate. In this buffer layer 18, for example, the In0.7Ga0.3AS0.6P0.4 layer is InP1 layer-InAs1 layer-InP1 layer-GaAs
1 layer - InP 1 layer - InAs 2 layers - InP 1 layer - GaA
It was formed by laminating eight of these structural units, with one structural unit consisting of layers laminated in the order of s2 layers.

On this buffer layer 18 is a Zn-doped p-
In0.53GaO,47As layer 19, about 680A graded layer and 5000 S-doped n-InP layer 2
7 are sequentially formed, and a pn junction is formed by a heterojunction consisting of an n shadow region with a wide forbidden band width and a p shadow region with a narrow forbidden band width. In addition, I)-In0.53G80
．． The 47AS layer 19 and the n-InP layer 27 were formed by the hydride VPE method, and the graded layer was formed by the ALE method. Furthermore, the carrier densities of the n shadow region and the p shadow region are n=3×1017 cm−3 and p=3, respectively.
7×11018a”.

The layer structure of the graded layer is shown below.

In the graded layer, for example, p-In□, 7G
a0.3AS0.6P0.4 layer is InF3 layer-InAs
One structural unit was formed by laminating three layers and three GaAs layers, and the structure was formed by laminating one structural unit.

After etching the p-n junction obtained above into a predetermined pattern, the p-In0.53G80.47AS layer 1
9 surface and the n-InP layer 27 surface, respectively.
forming an ohmic electrode made of i and AuGeNi,
When a large number of pn junction diodes were fabricated on a 2-inch wafer and evaluated, the uniformity of current-voltage characteristics and reverse breakdown voltage were significantly improved compared to those using pn junctions obtained by conventional methods. did.

In addition, in the above embodiment, the case where a (111)B substrate was used was described, but the present invention is not limited to this.
A substrate having a (100) plane or a plane orientation tilted several degrees from the (100) plane or another plane orientation may be used.

Further, in the above embodiment, for example, In□, 7 Ga
□, 3As□, 6Po, three formation methods were shown for forming the four layers, but the present invention is not limited thereto, and InF3
Layer - 1 layer of InAs - 1 layer of GaAs - 3 layers of InF - InA
s1 layer-GaAs1 layer-InF3 layer-InAs1 layer-G
aAs 1 layer - InF 3 layers, or InP 1 layer - GaAs
1 layer - InP 1 layer - InAs 1 layer - GaAs 1 layer -
InF3 layer - InAs1 layer - GaAs1 layer - InF3 layer - InAs1 layer etc.
O, 7Ga O, 3As O, 6P O, 4 layers may be formed.Similarly, the semiconductor layers of each composition are not limited to the laminated structure shown in the above example, but may be formed with other laminated structures. good.

Further, in the above embodiment, the present invention is applied to InP and InG.
The case where the application is applied to the formation of a heterojunction of aAs has been described, but the application is not limited to this, and
It goes without saying that the invention is also applicable to combinations of other binary compound semiconductors and ternary mixed crystal semiconductors, such as a combination of aAs and AlGaAs.

Furthermore, in the above embodiments, the present invention was used to form a buffer layer ρ and a pn junction, but
The invention is not limited thereto, and can also be applied to other semiconductor crystals or various semiconductor elements such as heterobipolar transistors, field effect transistors, semiconductor lasers, and light receiving elements.

(Effects of the Invention) As explained above, according to the present invention, composition control for achieving lattice matching becomes extremely easy, and as a result, lattice misalignment is reduced and composition uniformity is improved in a tilted junction. This has the effect of easily realizing type heterojunction. Therefore, this greatly contributes to improving the characteristics of various semiconductor crystals and semiconductor devices using heterojunctions.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor crystal for explaining the semiconductor stacked structure of the present invention, and FIG.
FIG. 3 is a cross-sectional view of the semiconductor crystal according to the second embodiment of the present invention.
4 is a cross-sectional view of a semiconductor crystal for explaining a conventional heterojunction, and FIG. 5 is a cross-sectional view of a semiconductor crystal according to an embodiment of I
In1-xGaxAsl +yPy lattice matched to nP
FIG. 1.28-InP layer, 2-InAs layer, 3=-GaAs
Layer, 4.17... Semi-insulating substrate (InP), 5-
i-InP layer, 6-'x-In0.95Ga0.05A
S0. IPo, 9 layers/7° = 1-In□, gGa□,
IAs□, 2PO, 3 layers・8°°°1-In O, 86
Ga O, 14As O, 29P O, 71 layers・9°−
1-In □, BGa O, 2As O, 4P O, 6
Layer, 10.23-1-In □, 75 Ga □, 2
5AS0.5P0.5 layer, 11-=1-In□, 7G
a□, 3 As layer, 6 P□, 4 layer, 12-i-In0
．． 64GaO, 36AS0.73P0.27 layer/13°
= 1-In □, 6 Ga □, 4 As O, 32
002 layer 114° = 1-In O,55Ga O,4
5As O, 91Po, 09 layer, 15-i-Ino,
5Ga□, 5As layer, 16-n-In□, 530a
□, 47 As layer, 18... buffer layer (In 1
-x Ga xAs 1 yP y, x : O-+
0.5, y; 1→0), 19-p-In□, 5
3Ga□, 47As'B, 20. p-In0.5Ga□
, 5As layer, 21-p-In □, 6 Ga □,
4 As □, B P □, 2 layers, 22-p -In □
, 7GaO,3AsO,6Po, 4 layers, 24-n-
In□, BGa□, 2As□, 4P□, 6 layers, 25...
・n-In□, g Ga□, IAs□, 2P□, 3 layers, 26.27・n-InP layer, 29. , , graded layer (In1-zGaxAsl-yP, ,x2o-+0
．． 47゜y; 1-+O), 30-In □, 53 G
a □, 47 As layer.

Claims (5)

[Claims] (1) A heterojunction in which a semiconductor layer A made of a binary compound semiconductor layer or a ternary or more multi-component mixed crystal semiconductor layer and a semiconductor layer B made of a ternary or more multi-component mixed crystal semiconductor layer are in contact via a graded layer. In the semiconductor laminated structure having a graded layer, the graded layer is a periodic laminated structure of two or more types of binary compound semiconductor layers containing the constituent elements of the semiconductor layer A and the semiconductor layer B, and the period of the periodic laminated structure is A semiconductor stacked structure characterized by changes. (2) The semiconductor layer A is composed of a first semiconductor layer made of a first binary compound semiconductor, and the semiconductor layer B is composed of a second binary compound semiconductor and a third binary compound semiconductor. It is originally a mixed crystal semiconductor, and the periodic layered structure is a first semiconductor layer - a second semiconductor layer made of a second binary compound semiconductor - a third semiconductor layer made of a third binary compound semiconductor, or 2. The semiconductor stacked structure according to claim 1, comprising a stacked structure configured in any one of the following order: first semiconductor layer - third semiconductor layer - second semiconductor layer. (3) The semiconductor layer A is composed of a first semiconductor layer made of a first binary compound semiconductor, and the semiconductor layer B is composed of a second binary compound semiconductor and a third binary compound semiconductor. It is originally a mixed crystal semiconductor, and has a periodic laminated structure of a first semiconductor layer - a second semiconductor layer made of a second binary compound semiconductor - a first semiconductor layer - a third semiconductor layer made of a third binary compound semiconductor. A claim characterized in that the claim includes a laminated structure composed of three semiconductor layers, or a first semiconductor layer, a third semiconductor layer, and any one of the first semiconductor layer and the second semiconductor layer. Item 1. Semiconductor stacked structure according to item 1. (4) The semiconductor layer A is composed of a first semiconductor layer made of a first binary compound semiconductor, and the semiconductor layer B is a ternary mixture composed of a second binary compound semiconductor and a third binary compound semiconductor. It is a crystalline semiconductor, and the periodic layered structure includes a layered structure consisting of a second semiconductor layer made of a second binary compound semiconductor and a third semiconductor layer made of a third binary compound semiconductor. The semiconductor laminated structure according to claim 1. (5) A semiconductor device characterized in that at least a portion thereof has a semiconductor stacked structure according to claim 1, 2, 3, or 4.