JPH02270036A - Redundant switch protecting circuit - Google Patents

Redundant switch protecting circuit

Info

Publication number
JPH02270036A
JPH02270036A JP1093450A JP9345089A JPH02270036A JP H02270036 A JPH02270036 A JP H02270036A JP 1093450 A JP1093450 A JP 1093450A JP 9345089 A JP9345089 A JP 9345089A JP H02270036 A JPH02270036 A JP H02270036A
Authority
JP
Japan
Prior art keywords
redundant
control signal
switching
output
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1093450A
Other languages
Japanese (ja)
Inventor
Tomomi Nishioka
西岡 智巳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1093450A priority Critical patent/JPH02270036A/en
Publication of JPH02270036A publication Critical patent/JPH02270036A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the occurrence of undesired redundant switch by preparing a circuit which inspects the validity of the redundant switch control signal when the switch control signal has an error with each unit of a redundant system. CONSTITUTION:A 3-stage shift register 2 stores the control signal received from a switch control circuit 1. The AND gates 2 and 3 secure the ANDs of the forward phase output and the inverted output among the stages of the register 2. Then an RS-flip-flop 4 fetches the outputs of both gates 2 and 3 into the S and R inputs respectively and outputs a redundant switch signal. The output of the redundant switch signal is controlled based on the data equivalent to plural past clocks equal to the continuous stages of the register 2. Thus the influence of the control signal error is reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、冗長系を構成する装置における冗長切替機能
の安定化に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to stabilization of a redundancy switching function in devices constituting a redundant system.

〔従来の技術〕[Conventional technology]

従来、この種の冗長系を構成する装置の切替方式は、第
2図に示すように装置の冗長系を構成する各ユニットの
切替状態を制御する切替制御回路から出力される制御信
号とラッチ信号を、前記各ユニットの受信部に設けられ
た1段のD−フリップフロップに取込み、そのD−フリ
ップフロップから冗長切替信号が出力されていた。
Conventionally, the switching method for devices that make up this type of redundant system uses control signals and latch signals output from a switching control circuit that controls the switching state of each unit that makes up the redundant system of the device, as shown in Figure 2. is taken into a one-stage D-flip-flop provided in the receiving section of each unit, and a redundancy switching signal is output from the D-flip-flop.

〔発明が解決しよう、とする課題〕[Problem that the invention aims to solve]

上述した従来の冗長系を構成する各ユニットにおいて、
切替制御回路からの制御信号の受信部は、1段のフリッ
プフロップを用いた構成であるため、各ユニットの制御
信号の受信部に入力される制御信号に誤りが生じたとき
、不必要な冗長切替が行われやすい欠点があった。この
様な制御信号の誤りは、例えば切替制御回路の活線挿抜
によって引き起こされる。
In each unit that constitutes the conventional redundant system mentioned above,
Since the receiving section of the control signal from the switching control circuit uses a single-stage flip-flop, unnecessary redundancy is generated when an error occurs in the control signal input to the control signal receiving section of each unit. There was a drawback that switching was easy to occur. Such control signal errors are caused, for example, by hot insertion and removal of the switching control circuit.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の冗長切替保護方式は、冗長系を構成する各ユニ
ットにおいて、装置の切替制御回路から出力される制御
信号を受ける受信部に、シフトレジスタと、前記シフト
レジスタの各段の正相出力のAND論理を行うANDゲ
ート回路と、各段の反転出力のAND論理を行うAND
ゲート回路と、前記2つのANDゲート回路のそれぞれ
の出力を正相出力はS入力に、反転入力はR入力に取込
むR3−フリップフロップとを有する。
In the redundant switching protection method of the present invention, in each unit constituting the redundant system, a shift register is provided in a receiving section that receives a control signal output from a switching control circuit of the device, and a positive phase output of each stage of the shift register is provided. An AND gate circuit that performs AND logic, and an AND gate circuit that performs AND logic of the inverted output of each stage.
It has a gate circuit and an R3 flip-flop which takes in the outputs of the two AND gate circuits, the positive phase output being taken into the S input, and the inverted input being taken into the R input.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第2図は従来の回路構成、第1図は本発明の一実施例で
、シフトレジスタが3段の場合の冗長切替保護回路の回
路図である。第1図において、3段シフトレジスタ2は
、切替制御回路1より出力される制御信号を記憶する。
FIG. 2 is a circuit diagram of a conventional circuit configuration, and FIG. 1 is an embodiment of the present invention, which is a circuit diagram of a redundant switching protection circuit when the shift register has three stages. In FIG. 1, a three-stage shift register 2 stores a control signal output from a switching control circuit 1.

ANDゲート2およびANDゲート3は、それぞれシフ
トレジスタ各段の正相出力および反転出力のANDをと
り、RS−フリップフロップ4はS、R入力にそれぞれ
ANDゲート2とANDゲート3の出力を取込んで冗長
切替信号を出力する。
AND gate 2 and AND gate 3 take the AND of the positive phase output and inverted output of each stage of the shift register, respectively, and the RS-flip-flop 4 takes in the outputs of AND gate 2 and AND gate 3 into S and R inputs, respectively. outputs a redundant switching signal.

第4図は第1図について、そして第3図は第2図に示す
従来の冗長切替回路について、切替制御信号の擾乱が起
こった場合の影響の一例を、タイムチャートで比較のた
め示す。従来方式では制御信号の誤りは、そのまま冗長
切替信号として出力されるが、本発明では連続したシフ
トレジスタの段数分の過去複数クロック分のデータによ
り、冗長切替信号の出力を制御するため、制御信号誤り
の影響を受けにくい。
4 shows the conventional redundant switching circuit shown in FIG. 1, and FIG. 3 shows an example of the effect when disturbance of the switching control signal occurs in the conventional redundant switching circuit shown in FIG. 2, using a time chart for comparison. In the conventional method, an error in the control signal is output as is as a redundancy switching signal, but in the present invention, the output of the redundancy switching signal is controlled using data for multiple past clocks corresponding to the number of consecutive shift register stages. Less susceptible to error.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は冗長系を構成する装置に
おいて、冗長系の各ユニットで切替制御信号に誤りが生
じた場合に、冗長切替の制御信号の有効性を検証する回
路を備えることにより、不必要な冗長切替の発生を防ぐ
効果がある。
As explained above, the present invention provides a device that constitutes a redundant system, by providing a circuit that verifies the validity of the redundant switching control signal when an error occurs in the switching control signal in each unit of the redundant system. This has the effect of preventing unnecessary redundant switching from occurring.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の冗長切替保護回路の回路図、第2図は
従来の冗長切替回路の回路図、第3図は従来方式による
制御信号誤り時の切替機能実行の一例を示すタイムチャ
ート、第4図は第3図と同じ制御信号誤り時の本発明の
方式の切替機能の実行を示したタイムチャートである。 1・・・・・・切替制御回路、2・・・・・・シフトレ
ジスタ、3・・・・・・ANDゲート回路、4・・・・
・・ANDゲート回路、5・・・・・・RS−フリップ
フロップ。 代理人 弁理士  内 原   音 第1 匿 ピJ ゝ  第2図 環3図     第4図
FIG. 1 is a circuit diagram of a redundant switching protection circuit of the present invention, FIG. 2 is a circuit diagram of a conventional redundant switching circuit, and FIG. 3 is a time chart showing an example of the execution of a switching function in the event of a control signal error according to the conventional method. FIG. 4 is a time chart showing the execution of the switching function of the system of the present invention when the same control signal error as in FIG. 3 occurs. 1...Switching control circuit, 2...Shift register, 3...AND gate circuit, 4...
...AND gate circuit, 5...RS-flip-flop. Agent Patent Attorney Uchihara Oto 1 Anonymous Pi J ゝ Figure 2 Ring 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 複数ユニットにて冗長系を構成する装置における各ユニ
ットの切替を制御する切替制御回路と、前記切替制御回
路から出力される切替制御信号およびラッチ信号を入力
とするシフトレジスタと、前記シフトレジスタの各段の
正相出力のAND論理を行うANDゲート回路と、前記
シフトレジスタの反転出力のAND論理を行うANDゲ
ート回路と、前記2つのANDゲート回路のそれぞれの
出力のうち、正相出力はS入力に、反転出力はR入力に
取込むRS−フリップフロップとをもつことを特徴とす
る冗長切替保護方式。
a switching control circuit that controls switching of each unit in a device that configures a redundant system with a plurality of units; a shift register that receives a switching control signal and a latch signal output from the switching control circuit; and each of the shift registers. An AND gate circuit performs AND logic of the positive phase output of the stage, an AND gate circuit performs AND logic of the inverted output of the shift register, and of the respective outputs of the two AND gate circuits, the positive phase output is connected to the S input. A redundant switching protection system characterized in that it has an RS-flip-flop whose inverted output is taken into the R input.
JP1093450A 1989-04-12 1989-04-12 Redundant switch protecting circuit Pending JPH02270036A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1093450A JPH02270036A (en) 1989-04-12 1989-04-12 Redundant switch protecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1093450A JPH02270036A (en) 1989-04-12 1989-04-12 Redundant switch protecting circuit

Publications (1)

Publication Number Publication Date
JPH02270036A true JPH02270036A (en) 1990-11-05

Family

ID=14082664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1093450A Pending JPH02270036A (en) 1989-04-12 1989-04-12 Redundant switch protecting circuit

Country Status (1)

Country Link
JP (1) JPH02270036A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6449070B1 (en) 1998-02-16 2002-09-10 Fujitsu Limited Optical transmission device and wavelength-multiplexed optical transmission system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6449070B1 (en) 1998-02-16 2002-09-10 Fujitsu Limited Optical transmission device and wavelength-multiplexed optical transmission system

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