JPH0226892B2 - - Google Patents
Info
- Publication number
- JPH0226892B2 JPH0226892B2 JP58033743A JP3374383A JPH0226892B2 JP H0226892 B2 JPH0226892 B2 JP H0226892B2 JP 58033743 A JP58033743 A JP 58033743A JP 3374383 A JP3374383 A JP 3374383A JP H0226892 B2 JPH0226892 B2 JP H0226892B2
- Authority
- JP
- Japan
- Prior art keywords
- tap coefficient
- output
- tap
- digital filter
- equalizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 6
- 230000007423 decrease Effects 0.000 claims description 5
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000013139 quantization Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- DNTFEAHNXKUSKQ-RFZPGFLSSA-N (1r,2r)-2-aminocyclopentane-1-sulfonic acid Chemical compound N[C@@H]1CCC[C@H]1S(O)(=O)=O DNTFEAHNXKUSKQ-RFZPGFLSSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03114—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
- H04L25/03146—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a recursive structure
Description
【発明の詳細な説明】
（技術分野）
本発明は自動等化器の収束判定方式に係り、特
に信号に含まれる波形歪に対する収束判定が、雑
音に強く、確実に行え、かつ簡単な回路で実現で
き、しかも波形歪としてメタリツク線路の分岐線
路（ブリツジドタツプ線路）のパルス反射に基づ
く波形歪の正確で迅速な等化が可能なブリツジド
タツプ等化器の収束判定方式に関する。[Detailed Description of the Invention] (Technical Field) The present invention relates to a convergence determination method for an automatic equalizer, and in particular, convergence determination for waveform distortion contained in a signal is resistant to noise, can be performed reliably, and is performed using a simple circuit. The present invention relates to a convergence determination method for a bridged tap equalizer that can be realized and that can accurately and quickly equalize waveform distortion based on pulse reflection of a branch line (bridged tap line) of a metallic line.
（従来技術）
第１図は、信号に含まれる歪の自動波形等化器
の従来例のブロツク図である。第１図は、信号の
入出力端子１―１，１―２、補正波形加算器１―
３、識別回路１―４、エラー極性判定回路１―
５、時間Ｔの遅延回路１―６、タツプ係数更新回
路１―７、Ｄ／Ａ変換器１―８、低減フイルタ１
―９より構成される。(Prior Art) FIG. 1 is a block diagram of a conventional example of an automatic waveform equalizer for distortion contained in a signal. Figure 1 shows signal input/output terminals 1-1, 1-2, correction waveform adder 1-
3. Identification circuit 1-4, error polarity determination circuit 1-
5. Time T delay circuit 1-6, tap coefficient update circuit 1-7, D/A converter 1-8, reduction filter 1
- Consists of 9.
第１図の系において、等化器の収束時には、自
動制御を受けたタツプ係数の値が一定値を中心と
して増減を繰り返すことを利用して、このタツプ
係数の増減を行つていた。しかし、タツプ係数の
増減の繰り返しは、等化器の発散状態においても
起き、また雑音によつても生ずることが知られ等
化器が確実に収束したか歪かの保証が得られない
欠点を有していた。 In the system shown in FIG. 1, when the equalizer converges, the tap coefficient is increased or decreased by taking advantage of the fact that the value of the automatically controlled tap coefficient repeatedly increases or decreases around a constant value. However, it is known that the repeated increase and decrease of the tap coefficient occurs even when the equalizer is in a divergent state, and is also caused by noise, so it has the disadvantage that it cannot be guaranteed whether the equalizer has converged or is distorted. had.
（発明の目的）
本発明の目的は従来雑音又は回路自体の不安定
性によつて惹起された収束判定の誤りを除去する
ことの出来る収束判定方式を提供することにあ
る。(Object of the Invention) An object of the present invention is to provide a convergence judgment method that can eliminate convergence judgment errors conventionally caused by noise or instability of the circuit itself.
（発明の概要）
この発明では、上記目的を達成するため、あら
かじめ定められた孤立パターンが検出され、しか
も、タツプ係数の一定値を中心とした増減の繰返
し回数が設定値に達したときに、等化器が収束し
たものと判定するようにしたものである。以下実
施例に基づいて詳細に説明する。(Summary of the Invention) In order to achieve the above object, the present invention detects a predetermined isolated pattern, and furthermore, when the number of repetitions of increase and decrease around a constant value of the tap coefficient reaches a set value, It is determined that the equalizer has converged. A detailed explanation will be given below based on examples.
（発明の実施例）
第２図は、本発明の一つの実施例を示すブロツ
ク図であつて、帰還デイジタルフイルタの次数が
２次即ち２タツプの例である。(Embodiment of the Invention) FIG. 2 is a block diagram showing one embodiment of the present invention, and is an example in which the order of the feedback digital filter is quadratic, that is, 2 taps.
第２図において、この等化器は、受信信号の入
出力端子２―１、識別信号の出力端子２―２、識
別回路２―３、エラー極性検出器２―４、パター
ン検出器２―５、タツプ係数カウンタ２―６，２
―２０、Ｄ／Ａ変換器２―７、ローパスフイルタ
２―８、補正信号加算回路２―９、遅延器２―１
０，２―１１，２―１２、加算回路２―１３，２
―１４、乗算器２―１５，２―１６，２―１７，
２―１８、収束判定回路２―１９より構成されて
いる。 In FIG. 2, this equalizer includes a received signal input/output terminal 2-1, an identification signal output terminal 2-2, an identification circuit 2-3, an error polarity detector 2-4, and a pattern detector 2-5. , tap coefficient counter 2-6, 2
-20, D/A converter 2-7, low-pass filter 2-8, correction signal addition circuit 2-9, delay device 2-1
0, 2-11, 2-12, addition circuit 2-13, 2
-14, multiplier 2-15, 2-16, 2-17,
2-18, and a convergence determination circuit 2-19.
第２図において、遅延器２―１０，２―１１、
タツプ係数カウンタ２―６，２―２０、乗算器２
―１７，２―１８、及び加算器２―１４、はデイ
ジタルフイルタを構成し、タツプ係数カウンタ２
―６，２―２０の計数値はデイジタルフイルタの
タツプ係数に対応する。また、パターン検出器２
―５、加算回路２―１３、エラー極性検出器２―
４、遅延器２―１２、及び乗算器２―１５、２―
１６はデイジタルフイルタのタツプ係数制御回路
を構成する。 In FIG. 2, delay devices 2-10, 2-11,
Tap coefficient counter 2-6, 2-20, multiplier 2
-17, 2-18, and adder 2-14 constitute a digital filter, and tap coefficient counter 2-14 constitutes a digital filter.
The count values of -6 and 2-20 correspond to the tap coefficients of the digital filter. In addition, the pattern detector 2
-5, Adder circuit 2-13, Error polarity detector 2-
4, delay device 2-12, and multiplier 2-15, 2-
16 constitutes a digital filter tap coefficient control circuit.
その動作を、４ビツトの孤立パターン（０，±
１，０，０）に歪波形成分が加わつた信号を、入
力信号の例として説明する。第３図ａは歪波形成
分を含む孤立パターン（０，１，０，０）の例を
示す。第３図ａにおいて、横軸３―１は、時間の
進みを示す。タテ軸３―２は、波形の振幅、３―
３は歪を含んだ入力波形、３―４は識別レベルを
示す。時間軸３―１上の―Ｔ，０，Ｔ，2T，3T
は識別回路２―３における識別タイミング時間で
ある。 The operation is controlled by a 4-bit isolated pattern (0, ±
A signal obtained by adding a distorted waveform component to (1, 0, 0) will be explained as an example of an input signal. FIG. 3a shows an example of an isolated pattern (0, 1, 0, 0) containing a distorted waveform component. In FIG. 3a, the horizontal axis 3-1 indicates the progression of time. The vertical axis 3-2 is the amplitude of the waveform, 3-
3 indicates an input waveform containing distortion, and 3-4 indicate the discrimination level. On time axis 3-1 - T, 0, T, 2T, 3T
is the identification timing time in the identification circuit 2-3.
識別回路２―３は、タイミング時間において、
第３図ｂに示した様に（０，＋１，＋１，０）と判
定し、時間Ｔ毎に順番にシフトし、時間Ｔの遅延
器２―１０，２―１１とパターン検出器２―５に
出力する。パターン検出器２―５は、孤立パター
ン（本例では、０，±１，０，０）の検出と、そ
のAMI符号規則に違反する信号パターン（本例
では、０，＋１，＋１，０と、０，−１，−１，０
と、０，＋１，０，＋１と０，−１，−１，０）とを
検出する。なお、AMI符号規則に違反するパタ
ーンは、ブリツジドタツプでの反射に基づくもの
とみなしうるが、AMI符号規則に従うパターン
（０，＋１，−１，０や、０，＋１，０，−１のよう
な）は、タツプの反射と無関係な雑音に基づくも
のなので、検出せず、従つて後述の係数制御も行
わない。 The identification circuit 2-3 at timing time,
As shown in FIG. 3b, it is determined as (0, +1, +1, 0), and is shifted in order at each time T, delayers 2-10, 2-11 and pattern detector 2-5 at time T. Output to. The pattern detector 2-5 detects isolated patterns (in this example, 0, ±1, 0, 0) and signal patterns that violate the AMI code rules (in this example, 0, +1, +1, 0). ,0,-1,-1,0
, 0, +1, 0, +1 and 0, -1, -1, 0). Note that patterns that violate the AMI code rules can be considered to be based on reflections at bridged taps, but patterns that follow the AMI code rules (such as 0, +1, -1, 0, and 0, +1, 0, -1) ) is based on noise unrelated to the tap reflection, so it is not detected and therefore the coefficient control described below is not performed.
一方、加算器２―１３において、識別回路２―
３の入出力間の誤差信号を取り出し、その正負の
極性のみで代表させるために、エラー極性検出器
２―４において、タイミング時間における誤差信
号の極性を検出する。 On the other hand, in the adder 2-13, the identification circuit 2-
In order to take out the error signal between the input and output of No. 3 and represent it only by its positive and negative polarities, the error polarity detector 2-4 detects the polarity of the error signal at the timing time.
第３図ｃは、エラー極性検出器２―４の出力で
ある。 FIG. 3c shows the output of the error polarity detector 2-4.
乗算器２―１５，２―１６では、このエラー検
出器２―４の出力もしくは遅延回路２―１２を介
した出力と、パターン検出器２―５の出力との論
理積を取り、それをタツプ係数制御信号として、
タツプ係数カウンタ２―６，２―２０へ送る。 Multipliers 2-15 and 2-16 perform a logical AND operation between the output of the error detector 2-4 or the output via the delay circuit 2-12 and the output of the pattern detector 2-5, and tap the result. As a coefficient control signal,
Send to tap coefficient counters 2-6 and 2-20.
係数カウンタ２―６，２―２０は乗算器２―１
５，２―１６の出力に応じて、カウントアツプ又
はカウントダウンする。すなわち、識別回路２―
３の出力において、孤立パターン又はそのAMI
符号規則違反のパターンが検出されていることを
条件にして、誤差信号に応じて、アツプ又はダウ
ンする。 Coefficient counters 2-6, 2-20 are multiplier 2-1
It counts up or down depending on the output of 5, 2-16. That is, the identification circuit 2-
In the output of 3, the isolated pattern or its AMI
It goes up or down depending on the error signal, provided that a pattern that violates the code rule is detected.
タツプ係数カウンタ２―６，２―２０（及び乗
算器２―１７，２―１８）は、デイジタルフイル
タのタツプ係数器に相当するので、その精度は、
Ｄ／Ａ変換器２―７の量子化ビツト数と同一に選
らばれる。 Since the tap coefficient counters 2-6, 2-20 (and multipliers 2-17, 2-18) correspond to the tap coefficient counters of a digital filter, their accuracy is
The number of quantization bits is selected to be the same as the number of quantization bits of the D/A converter 2-7.
また、識別回路２―３の出力はデイジタルフイ
ルタの入力として遅延回路２―１０へ与えられ、
時間Ｔの遅延器２―１０，２―１１の出力と、タ
ツプ係数カウンタ２―６，２―２０の出力との積
を加算器２―１４で加算することによつて、デイ
ジタルフイルタの出力を作成し、補正信号は、こ
の出力をＤ／Ａ変換器２―７にてアナログ信号へ
変換され、ローパスフイルタ２―８で帯域制限さ
れて得られる。帯域制限された補正信号は、加算
器２―９で歪を含んだ入力信号と加算される。 Further, the output of the identification circuit 2-3 is given to the delay circuit 2-10 as an input of a digital filter,
By adding the products of the outputs of the delay devices 2-10, 2-11 at time T and the outputs of the tap coefficient counters 2-6, 2-20 in the adder 2-14, the output of the digital filter is calculated. A correction signal is obtained by converting this output into an analog signal in a D/A converter 2-7, and band-limiting it in a low-pass filter 2-8. The band-limited correction signal is added to the distorted input signal in an adder 2-9.
以上説明した系のシユミレーシヨンにより得ら
れたタツプ係数の収束過程を第４図に示す。第４
図において、４―１は、１タツプ目のタツプ係
数、４―２は２タツプ目のタツプ係数である。横
軸４―３は、タツプ係数の更新回数、タテ軸４―
４は係数値、破線４―５は、等化器のタツプ係数
が収束状態に入る基点である。本例では、約35回
のタツプ係数更新によつて、収束状態に移行して
いる。等化器が収束状態に入ると各タツプ係数
は、一定値で増減を繰返す。 FIG. 4 shows the convergence process of tap coefficients obtained by simulation of the system described above. Fourth
In the figure, 4-1 is the tap coefficient for the first tap, and 4-2 is the tap coefficient for the second tap. The horizontal axis 4-3 is the number of updates of the tap coefficient, and the vertical axis 4-3 is the number of updates of the tap coefficient.
4 is the coefficient value, and the dashed line 4-5 is the base point at which the tap coefficient of the equalizer enters the convergence state. In this example, the convergence state is reached by updating the tap coefficients approximately 35 times. When the equalizer enters a convergence state, each tap coefficient repeats increasing and decreasing at a constant value.
すなわち、タツプ等化の初期においては、孤立
パターンのAMI符号規則違反の信号パターンが
検出されて、タツプ係数は単調変化するが、収束
状態に移行すると、入力信号の歪波形成分は、ほ
とんど補正され、パターン検出器２―５は、（０，
±１，０，０）なる孤立パターンを検出し、タツ
プ係数は増減を繰返す。 In other words, at the initial stage of tap equalization, a signal pattern that violates the AMI sign rule is detected as an isolated pattern, and the tap coefficient changes monotonically, but when the state reaches a convergence state, the distorted waveform component of the input signal is almost completely corrected. , the pattern detector 2-5 detects (0,
An isolated pattern of ±1, 0, 0) is detected, and the tap coefficient increases and decreases repeatedly.
収束判定回路２―１９による収束判定は、識別
回路２―３の出力において、孤立パターン（０，
±１，０，０）が検出されていて、しかも、タツ
プ係数カウンタ２―６，２―２０の計数値の、一
定値を中心とした繰返し数が設定値に達したと
き、タツプ係数収束信号を発生させることにより
行い、この信号によりタツプ係数カウンタ２―
６，２―２０の更新動作を停止させる。 The convergence judgment by the convergence judgment circuit 2-19 is based on the isolated pattern (0,
±1, 0, 0) is detected and the number of repetitions of the count values of tap coefficient counters 2-6, 2-20, centered around a constant value, reaches the set value, the tap coefficient convergence signal This is done by generating tap coefficient counter 2-
6. Stop the update operation of 2-20.
このように、孤立パターン（０，±１，０，０）
の検出を一つの条件として等化器の収束判定を行
うので、タツプ係数の発散状態における収束と雑
音時における収束とを避けることができる。 In this way, isolated pattern (0,±1,0,0)
Since the convergence determination of the equalizer is made using the detection of the tap coefficient as one condition, it is possible to avoid convergence in the divergent state of the tap coefficients and convergence in the noise state.
なお、以上記述においては、自動等化器の制御
動作が、系の動作の初期段階すなわち、トレーニ
ング段階にある場合について記述した。一方、ト
レーニング段階が終了し、系が情報通信期間に移
行した場合においても、さらに等化器の状態を変
更する必要が生ずる場合がある。これは、系が経
時的に特性変動する場合である。トレーニング状
態においては、等化動作は可及的速やかに行われ
る必要があるのに対して、情報通信期間時におい
ては、むしろ動作が緩和して行われることがもと
められている。 In the above description, the control operation of the automatic equalizer is in the initial stage of system operation, that is, in the training stage. On the other hand, even when the training phase ends and the system transitions to the information communication period, it may be necessary to further change the state of the equalizer. This is the case when the characteristics of the system change over time. In the training state, the equalization operation must be performed as quickly as possible, whereas during the information communication period, the equalization operation is required to be performed in a relaxed manner.
トレーニング期間については、（０，±１，０，
０）なる孤立パターンを要素とする繰返しパター
ンを送信するので、一般には４ビツト毎に孤立パ
ターンが検出されることになるが、情報通信期間
においては、通信情報中に確率的に含まれている
その孤立パターンを利用して、タツプ係数カウン
タの動作停止を一時的に解除することによつて行
う。すなわち、信号中に確率的に含まれる孤立パ
ターンを検出し、かつ、その、回数が予め設定し
た回数に達した時のみ、前記タツプ係数の更新を
行うことにより達成できる。これは、タツプ係数
更新のガードタイムを設定することにより行う。 For the training period, (0, ±1,0,
0) is transmitted, so an isolated pattern is generally detected every 4 bits, but during the information communication period, the isolated pattern is stochastically included in the communication information. This is done by temporarily canceling the stoppage of the tap coefficient counter using the isolated pattern. That is, this can be achieved by detecting an isolated pattern stochastically included in a signal and updating the tap coefficient only when the number of isolated patterns has reached a preset number. This is done by setting a guard time for updating tap coefficients.
（発明の効果）
以上説明したように、この発明では、タツプ係
数の収束信号と、パターン検出信号との論理積に
よつて、等化器の収束判定を行うため、雑音にも
強く、確実に等化器の収束判定を行うことができ
る。(Effects of the Invention) As explained above, in this invention, the convergence determination of the equalizer is performed by the AND of the convergence signal of the tap coefficient and the pattern detection signal. It is possible to determine the convergence of the equalizer.
以上の説明においては０，±１，０，０なる４
ビツトの孤立パターンを用いた場合について説明
したが、０，±１，０，０，０のような、他の長
ビツトの孤立パターンを用いてもよい。 In the above explanation, 4 is 0, ±1, 0, 0.
Although the case where an isolated bit pattern is used has been described, other long bit isolated patterns such as 0, ±1, 0, 0, 0 may also be used.
本発明は、デイジタル加入者線伝送において、
反射に基づくパルス伝送歪を等化する波形歪の自
動等化器の収束判定に非常に有効であり、又、孤
立パターンにより等化器を収束させる方式には、
広く利用することができるものである。 In digital subscriber line transmission, the present invention provides
It is very effective in determining the convergence of an automatic equalizer for waveform distortion that equalizes pulse transmission distortion based on reflections.
It can be widely used.
第１図は従来の判定帰還形自動等化器の一般例
を示すブロツク図、第２図は本発明の一実施例を
示すブロツク図、第３図は第２図に示した回路に
おける動作の説明図、第４図は第２図に示した回
路のシユミレーシヨンによつて得たタツプ係数の
収束過程を示す説明図である。
２―１，２―２……入出力端子、２―３……識
別回路、２―４……エラー極性判定回路、２―５
……パターン検出器、２―６……タツプ係数更新
カウンタ、２―７……Ｄ／Ａ変換器、２―８……
ローパスフイルタ、３―１……時間軸、３―２…
…波形振幅、３―３……入力波形、３―４……識
別レベル、４―１，４―２……タツプ係数、４―
３……係数更新回数。
Fig. 1 is a block diagram showing a general example of a conventional decision feedback type automatic equalizer, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 shows the operation of the circuit shown in Fig. 2. The explanatory diagram, FIG. 4, is an explanatory diagram showing the convergence process of tap coefficients obtained by simulation of the circuit shown in FIG. 2. 2-1, 2-2...Input/output terminal, 2-3...Identification circuit, 2-4...Error polarity determination circuit, 2-5
...Pattern detector, 2-6...Tap coefficient update counter, 2-7...D/A converter, 2-8...
Low-pass filter, 3-1...Time axis, 3-2...
...Waveform amplitude, 3-3...Input waveform, 3-4...Identification level, 4-1, 4-2...Tap coefficient, 4-
3...Number of coefficient updates.
Claims (1)
識別回路２―３と、 遅延器とタツプ係数カウンタとを含み、前記識
別回路の出力を入力とするデイジタルフイルタ２
―１０，２―１１，２―６，２―２０，２―１
７，２―１８，２―１４と、 そのデイジタルフイルタの出力に基づいて、前
記補正信号を発生する手段２―７，２―８と、 前記識別回路の出力においてあらかじめ定めら
れた孤立パターンおよびそのAMI符号規則違反
のパターンのいずれかを検出したことを条件とし
て、前記識別回路の入出力間の誤差信号に応じ
て、前記デイジタルフイルタの前記タツプ係数カ
ウンタの計数値をアツプ又はダウンする制御手段
２―１３，２―４，２―５，２―１５，２―１６
とを備え、 前記識別回路の出力において前記孤立パターン
が検出されていて、しかも、前記デイジタルフイ
ルタの前記タツプ係数カウンタの一定値を中心と
した増減の繰返し回数が設定値に達したときに、
等化器が収束したものと判定することを特徴とし
たブリツジドタツプ等化器の収束判定方式。[Claims] 1. An identification circuit 2-3 which receives as input the received signal corrected by the correction signal, and a digital filter 2 which includes a delay device and a tap coefficient counter and receives the output of the identification circuit as input.
-10,2-11,2-6,2-20,2-1
7, 2-18, 2-14, means 2-7, 2-8 for generating the correction signal based on the output of the digital filter, and a predetermined isolated pattern and its Control means 2 for increasing or decreasing the count value of the tap coefficient counter of the digital filter according to the error signal between the input and output of the identification circuit, on the condition that any pattern violating the AMI code rule is detected. -13, 2-4, 2-5, 2-15, 2-16
and when the isolated pattern is detected in the output of the identification circuit and the number of repetitions of increase and decrease around a constant value of the tap coefficient counter of the digital filter reaches a set value,
A convergence determination method for a bridged tap equalizer characterized by determining that the equalizer has converged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3374383A JPS59160335A (en) | 1983-03-03 | 1983-03-03 | Decision system for convergence of bridged tap equalizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3374383A JPS59160335A (en) | 1983-03-03 | 1983-03-03 | Decision system for convergence of bridged tap equalizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59160335A JPS59160335A (en) | 1984-09-11 |
| JPH0226892B2 true JPH0226892B2 (en) | 1990-06-13 |
Family
ID=12394889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3374383A Granted JPS59160335A (en) | 1983-03-03 | 1983-03-03 | Decision system for convergence of bridged tap equalizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59160335A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0216183B1 (en) * | 1985-08-28 | 1992-06-03 | Nec Corporation | Decision feedback equalizer with a pattern detector |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58197927A (en) * | 1982-05-14 | 1983-11-17 | Fujitsu Ltd | System for discriminating completion of automatic equalization |
-
1983
- 1983-03-03 JP JP3374383A patent/JPS59160335A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58197927A (en) * | 1982-05-14 | 1983-11-17 | Fujitsu Ltd | System for discriminating completion of automatic equalization |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59160335A (en) | 1984-09-11 |
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