JPH02267523A - Driving method for liquid crystal element - Google Patents

Driving method for liquid crystal element

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Publication number
JPH02267523A
JPH02267523A JP9030189A JP9030189A JPH02267523A JP H02267523 A JPH02267523 A JP H02267523A JP 9030189 A JP9030189 A JP 9030189A JP 9030189 A JP9030189 A JP 9030189A JP H02267523 A JPH02267523 A JP H02267523A
Authority
JP
Japan
Prior art keywords
pulse
liquid crystal
selection period
polarity
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9030189A
Other languages
Japanese (ja)
Inventor
Hidekazu Kobayashi
英和 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP9030189A priority Critical patent/JPH02267523A/en
Publication of JPH02267523A publication Critical patent/JPH02267523A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

PURPOSE:To stabilize a memory in a non-selection period at the time of time division driving by applying a set pulse corresponding to the display contents, and thereafter, applying a pulse in which the product of a crest value and pulse width is smaller than that of the set pulse, in a ferroelectric liquid crystal. CONSTITUTION:In a scanning electrode waveform 101, a crest value Ve of a reset pulse of a selection period 1 is set to a value by which a liquid crystal molecule is inverted enough by some pulse width Pw. Also, a crest value Vw of a set pulse is set to an average value of a crest value Vth whose inversion is started and a crest value Vsat whose inversion is ended, when a pulse whose polarity is opposite to that of the reset pulse is applied. Subsequently, in accordance with the polarity which a panel has, a positive or negative pulse is applied, and in accordance with magnitude of its polarity, a memory stabilizing pulse of a crest value VC2 is applied. On the other hand, in a signal electrode waveform 102, a crest value of pulse width Pw is set to >= (Vpat - Vth/2) and <=Vw. In such a way, in the course of a non-selection period, the polarity of the panel is negated, and instability of the memory can be avoided.

Description

【発明の詳細な説明】[Detailed description of the invention]

【産業上の利用分野] 本発明は液晶素子の時分割駆動方法に関する。 [従来の技術] 従来強誘電性液晶を用いた素子においては、駆動波形に
電荷の偏りが存在すると駆動中に上下基板方向で電荷の
偏りが生じ、この電荷の偏りにより強誘電性液晶の自発
分極が反転しメモリー性が失われ表示が不鮮明になる事
が多かった。ここでメモリー性とは選択期間で選択され
た表示状態が非選択時にも保たれる効果をいう。またこ
のような電荷の偏りが生じると液晶自身も劣化する。こ
のような電荷の偏りのない駆動方法としては、特願昭6
1−179346号に幾つか呈示されている。 [発明が解決しようとする課題】 しかし、従来の方法では液晶素子を駆動する場合の液晶
素子の液晶層の厚さに対する動作マージン、駆動パルス
のパルス幅及び波高値に対する動作マージン、動作温度
に対する動作マージンが狭い。これは液晶素子が走査電
極信号及び選択電極信号の合成波形で駆動されることに
1因がある(第3図参照)。すなわち走査電極信号に於
いては選択期間にさきに説明したセットパルス1(波高
値vth)とセットパルス2(波高値Vsat)の平均
パルス(波高値(Vth+Vsat)/2)を印加して
おき、これに同期して選択電極に状態1を選択スル場合
ハ(V s a t −V t h ) / 2なる波
高値のパルスを印加し、状態2を選択する場合は(Vt
h−VSat)/2なる波高値のパルスを印加する。こ
のため選択期間外に於いても他の走査線上の画素のため
の選択電極信号が印加されメモリー状態が不安定化され
る。すなわち状態1にリセットし状R2を書き込んでも
選択電極信号に液晶が応答し画素の1部が状B1に戻っ
てしまう。あるいは1度状態1にリセットし状態1を書
き込んでも選択電極信号に液晶が応答し画素の1部が状
態2に反転してしまう。この2つの現象は通常同時に起
こることはなくパネルの液晶層方向での極性によりどち
らかの現象が顕著にみられる。信号電極信号の振幅を小
さくすれば良いことになるがそれでは状態1及び状態2
が充分に選択できない。そこで本発明では、このような
課題を解決するものでありその目的とするところは非選
択期間に於いて選択電極信号により液晶が応答しにくい
駆動法を提供することである。
[Industrial Field of Application] The present invention relates to a time-division driving method for a liquid crystal element. [Prior art] In conventional devices using ferroelectric liquid crystals, if there is a charge bias in the drive waveform, charge bias occurs in the upper and lower substrate directions during driving, and this charge bias causes the spontaneous activation of the ferroelectric liquid crystal. Polarization was reversed, memory properties were lost, and the display often became unclear. Here, the term "memory property" refers to the effect that the display state selected during the selection period is maintained even when the display state is not selected. Moreover, when such charge bias occurs, the liquid crystal itself also deteriorates. As a driving method without such charge bias, there is a patent application filed in 1983.
1-179346. [Problems to be Solved by the Invention] However, in the conventional method, when driving a liquid crystal element, the operating margin for the thickness of the liquid crystal layer of the liquid crystal element, the operating margin for the pulse width and peak value of the driving pulse, and the operation for the operating temperature are Margins are narrow. One reason for this is that the liquid crystal element is driven by a composite waveform of a scanning electrode signal and a selection electrode signal (see FIG. 3). That is, in the scanning electrode signal, the average pulse (peak value (Vth+Vsat)/2) of set pulse 1 (peak value vth) and set pulse 2 (peak value Vsat) described earlier is applied during the selection period, In synchronization with this, if state 1 is selected, a pulse with a peak value of (Vs at - V th )/2 is applied to the selection electrode, and if state 2 is selected, (Vt
A pulse with a peak value of h-VSat)/2 is applied. Therefore, selection electrode signals for pixels on other scanning lines are applied even outside the selection period, making the memory state unstable. That is, even if the state is reset to state 1 and state R2 is written, the liquid crystal responds to the selection electrode signal and a portion of the pixels return to state B1. Alternatively, even if state 1 is reset once and state 1 is written, the liquid crystal responds to the selection electrode signal and a portion of the pixels are inverted to state 2. These two phenomena usually do not occur at the same time, and one of the phenomena is more noticeable depending on the polarity in the direction of the liquid crystal layer of the panel. It would be better to reduce the amplitude of the signal electrode signal, but that would result in state 1 and state 2.
There are not enough choices. SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a driving method that makes it difficult for the liquid crystal to respond to a selection electrode signal during a non-selection period.

【課題を解決するための手段】[Means to solve the problem]

(1)少なくとも走査電極の形成された基板と信号電極
の形成された基板間に、強誘電性液晶あるいは強誘電体
を挟持した素子に選択期間中あるいは選択期間の前に素
子を第一の状態にするパルス(リセットパルス)を印加
し、選択期間中に表示内容により素子を第二の状態にす
る実効値を有するパルス(セットパルス2)あるいは素
子を第二の状態にするしきい値以下のパルス(セットパ
ルス1)を印加する駆動方法に於て、セットパルス印加
後、素子の厚み方向に存在する電荷的な非対称性を打ち
消す極性で、波高値とパルス幅の積がセットパルス10
波高値とパルス幅の積よりも小さいパルスを印加するこ
とを特徴とする。 (2)課題を解決するための手段第1項記載のセットパ
ルスを印加する前に、波形全体を1フレーム内で電荷的
に中和するパルスを印加する事を特徴とする。 [作用〕 本発明の上記の構成によれば、発明が解決しようとする
課題で述べたようにメモリーが不安定化される要因とし
てパネルの極性があげられるが、セットパルス印加後に
パネルの極性を打ち消す方向にパルスを印加すればこの
様なメモリーの不安定化は回避される。またこの様に強
誘電性液晶を用いた素子では電気的な偏りに敏感である
ために選択期間の前あるいは選択期間中に波形全体に渡
って電荷を中和するパルスを印加すれば更によいメモリ
ー特性が得られ、液晶の寿命も長くなる。 以下、実施例により本発明の詳細を示す。 〔実施例〕 本実施例では便宜上負極性で飽和電圧以上のパルスが印
加された場合を暗状態とし、正極性で飽和電圧以上のパ
ルスが印加された場合を明状態であるとする。 実施例1 第1図に本実施例における駆動波形のタイミングチャー
ト図を示した。各波形における波高値の設定の方法につ
いて説明する。まず走査電極波形101について説明す
る。リセットパルスの波高値Veは液晶分子があるパル
ス幅Pwで充分に反転するに足る値とする。あるパルス
幅Pwとは液晶分子の応答速度よりもわずか長い値とす
る。セットパルスの波高値Vwはリセットパルスが印加
された後にパルス幅Pwでリセットパルスと逆極性のセ
ットパルスを印加したとき反転しかかる波高値vthと
さらに高い電圧を印加して表示が反転仕切る波高値Vs
atの平均値とする。メモリー安定化パルスはパネルの
持つ極性により正があるいは負か、またその極性の大き
さにより波高値VC2を決定する。電荷補正パルスの波
高値Vclは本実施例ではOvとしておく。次に信号電
極波形102について説明する。パルス幅はPwとして
波高値V d 4t (V s a t −V t h
 ) / 2以上でVw以下とする。第1図102で選
択期間1に示した信号波形を出力すれば101との合成
波形103で暗状態が選択され、選択期間2に示した信
号波形を出力すれば明状態が選択される。この時の素子
の光学応答を104に示した。本実施例では液晶として
大日本インキ■DOFOOO4を用い液晶層2.um、
Pw=150μsec、Ve=−25V、Vw=10V
、Vc2=−1,5V。 Vcl=OV% Vd=1.5Vであった。■c2をO
vとするとコントラストが10: 1であったが、Vc
2を−1,5vとするとコントラストは15: 1とな
った。 本実施例では電荷補正パルスを選択期間外としたが選択
期間内としてもよい。また信号電極波形102の選択期
間に於て1番目のパルスと3番目のパルスを入れ換えて
もよい。つまり実際に選択に関係するパルスは2番目の
パルスであり、他のパルスは電荷を補正するためにしか
すぎないからである。 本実施例では用いる液晶を他のものに変えればパルス幅
及び波高値の設定値を変更しなければならないことは云
うまでもない。 実施例2 本実施例では実施例1に於て電荷補正パルスを印加する
場合について説明する。第1図の走査電極波形101に
おける電荷補正パルスの波高値Vc1は、リセットパル
ス、セットパルス及びメモリー安定化パルスの総電荷量
を中和するように設定する。ここではVclを16.5
Vに設定した。 これにより駆動時の電荷の偏りが補正されメモリー状態
の安定性が増した。実際実施例1では電圧設定後しばら
くは動作するがその後はこまめにVC2を調整する必要
があったが、本実施例ではほとんとその必要が無い。 実施例3 実施例1及び実施例2では選択期間が液晶の応答速度の
3倍以上必要であったが、ここでは液晶の応答速度の2
倍程度の速度で選択できる方法について説明する。第2
図に本実施例における駆動波形のタイミングチャート図
を示す。各波形における波高値の設定の方法について説
明する。まず走査電極波形201について説明する。リ
セットパルスの波高値Ve及びセットパルスVwは実施
例1と同様に決定する。メモリー安定化パルスはパネル
の持つ極性により正かあるいは負か、またその極性の大
きさにより波高値Vc2を決定する。 但しパルス幅はセットパルスの半分とする。電荷補正パ
ルスの波高値Vclは実施例2と同様に決定した。次に
信号電極波形202について説明する。パルス幅は実施
例1の半分として波高値Vdは(Vsat−Vth)以
上でVw*2以下とする。第2図202で選択期間1に
示した信号波形を出力すれば201との合成波形203
で暗状態が選択され、選択期間2に示した信号波形を出
力すれ、ば明状態が選択される。この時の素子の光学応
答を204に示した。本実施例では液晶としてヘキスト
@Fe1ixoolをベースに用い液晶層2μm、Pw
=120.usec、Ve=−25V、Vw=12V、
Vc2=−3,OV、Vcl=15.5V、Vd=3.
 0Vであった。Vc2をOVとするとコントラストが
12: 1であったが、Vc2を−3,0■とするとコ
ントラストは17: 1となった。 本実施例では電荷補正パルスを選択期間外としたが選択
期間内としてもよい。但し選択期間が長くなる。 本実施例では用いる液晶を他のものに変えればパルス幅
及び波高値の設定値を変更しなければならないことは云
うまでもない。 以上実施例を述べたが、本発明は以上の実施例の波形の
みならず、あらゆるリセットパルス十セットパルスタイ
プの駆動波形に応用できる。またしきい特性とメモリー
性を有する素子、たとえば強誘電体表示素子などに応用
が可能である。 [発明の効果] 以上述べたように本発明によれば、強誘電性液晶を用い
た電気光学素子の時分割駆動時の非選択期間に於てメモ
リー状態が安定し、しかも長寿命という効果を有する。
(1) An element having a ferroelectric liquid crystal or a ferroelectric substance sandwiched between at least a substrate on which a scanning electrode is formed and a substrate on which a signal electrode is formed is placed in the first state during or before the selection period. A pulse (reset pulse) is applied to set the element to the second state during the selection period, and a pulse (set pulse 2) having an effective value that puts the element into the second state or a pulse below the threshold value that puts the element into the second state is applied depending on the display content during the selection period. In a driving method that applies a pulse (set pulse 1), after applying the set pulse, the product of the peak value and the pulse width is set pulse 10 with a polarity that cancels out the charge asymmetry that exists in the thickness direction of the element.
It is characterized by applying a pulse smaller than the product of the peak value and the pulse width. (2) Means for Solving the Problems Before applying the set pulse described in item 1, the present invention is characterized by applying a pulse that neutralizes the entire waveform in terms of charge within one frame. [Operation] According to the above configuration of the present invention, as described in the problem to be solved by the invention, the polarity of the panel is cited as a factor that makes the memory unstable. Such memory instability can be avoided by applying pulses in the canceling direction. In addition, devices using ferroelectric liquid crystals are sensitive to electrical bias, so applying a pulse to neutralize the charge over the entire waveform before or during the selection period will improve the memory. characteristics, and the lifespan of the liquid crystal is extended. Hereinafter, the details of the present invention will be shown by examples. [Example] For convenience, in this example, the case where a pulse with a negative polarity and a voltage higher than the saturation voltage is applied is defined as a dark state, and the case where a pulse with a positive polarity and a voltage higher than the saturation voltage is applied is defined as a bright state. Embodiment 1 FIG. 1 shows a timing chart of drive waveforms in this embodiment. A method for setting the peak value of each waveform will be explained. First, the scanning electrode waveform 101 will be explained. The peak value Ve of the reset pulse is set to a value sufficient to sufficiently invert the liquid crystal molecules with a certain pulse width Pw. A certain pulse width Pw is a value slightly longer than the response speed of liquid crystal molecules. The wave height value Vw of the set pulse is the wave height value vth at which the display is inverted when a set pulse with a pulse width Pw and the opposite polarity to the reset pulse is applied after the reset pulse is applied, and the wave height value at which the display is inverted when an even higher voltage is applied. Vs
Let it be the average value of at. The memory stabilizing pulse is positive or negative depending on the polarity of the panel, and the peak value VC2 is determined depending on the magnitude of the polarity. The peak value Vcl of the charge correction pulse is set to Ov in this embodiment. Next, the signal electrode waveform 102 will be explained. The pulse width is Pw, and the peak value V d 4t (V s a t - V th
) / 2 or more and Vw or less. If the signal waveform shown in the selection period 102 in FIG. 1 is output, the dark state is selected by the combined waveform 103 with 101, and if the signal waveform shown in the selection period 2 is output, the bright state is selected. The optical response of the element at this time is shown in 104. In this example, Dainippon Ink DOFOOO4 is used as the liquid crystal layer 2. Um,
Pw=150μsec, Ve=-25V, Vw=10V
, Vc2=-1,5V. Vcl=OV% Vd=1.5V. ■c2 to O
v, the contrast was 10:1, but Vc
When 2 was set to -1.5V, the contrast was 15:1. In this embodiment, the charge correction pulse is set outside the selection period, but it may be set within the selection period. Further, the first pulse and the third pulse may be interchanged in the selection period of the signal electrode waveform 102. This is because the pulse that is actually involved in selection is the second pulse, and the other pulses are only for correcting the charge. In this embodiment, it goes without saying that if the liquid crystal used is changed to another type, the set values of the pulse width and peak value must be changed. Embodiment 2 In this embodiment, a case will be described in which a charge correction pulse is applied in Embodiment 1. The peak value Vc1 of the charge correction pulse in the scanning electrode waveform 101 in FIG. 1 is set so as to neutralize the total charge amount of the reset pulse, set pulse, and memory stabilization pulse. Here, Vcl is 16.5
It was set to V. This corrects the imbalance in charge during driving and increases the stability of the memory state. In fact, in the first embodiment, the device operates for a while after setting the voltage, but after that it was necessary to frequently adjust VC2, but in this embodiment, there is almost no need for this. Example 3 In Examples 1 and 2, the selection period was required to be at least three times the response speed of the liquid crystal, but here, the selection period was required to be twice the response speed of the liquid crystal.
We will explain a method that allows you to select at twice the speed. Second
The figure shows a timing chart of drive waveforms in this embodiment. A method for setting the peak value of each waveform will be explained. First, the scanning electrode waveform 201 will be explained. The peak value Ve of the reset pulse and the set pulse Vw are determined in the same manner as in the first embodiment. The memory stabilizing pulse is positive or negative depending on the polarity of the panel, and the peak value Vc2 is determined depending on the magnitude of the polarity. However, the pulse width shall be half of the set pulse. The peak value Vcl of the charge correction pulse was determined in the same manner as in Example 2. Next, the signal electrode waveform 202 will be explained. The pulse width is half that of Example 1, and the peak value Vd is set to be greater than (Vsat-Vth) and less than Vw*2. If the signal waveform shown in selection period 1 in FIG. 2 202 is output, the combined waveform 203 with 201
The dark state is selected at , the signal waveform shown in selection period 2 is output, and the bright state is selected. The optical response of the element at this time is shown in 204. In this example, Hoechst@Fe1ixool was used as the liquid crystal as a base, and the liquid crystal layer was 2 μm thick, Pw
=120. usec, Ve=-25V, Vw=12V,
Vc2=-3, OV, Vcl=15.5V, Vd=3.
It was 0V. When Vc2 was set to OV, the contrast was 12:1, but when Vc2 was set to -3.0■, the contrast was 17:1. In this embodiment, the charge correction pulse is set outside the selection period, but it may be set within the selection period. However, the selection period will be longer. In this embodiment, it goes without saying that if the liquid crystal used is changed to another type, the set values of the pulse width and peak value must be changed. Although the embodiments have been described above, the present invention can be applied not only to the waveforms of the above embodiments but also to any drive waveform of the ten-set pulse type with reset pulses. It can also be applied to elements having threshold characteristics and memory properties, such as ferroelectric display elements. [Effects of the Invention] As described above, according to the present invention, the memory state is stabilized during the non-selection period during time-division driving of an electro-optical element using a ferroelectric liquid crystal, and furthermore, the effect of long life can be achieved. have

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の実施例1における 駆動波形のタイ
ミングチャート図である 第3図は、従来例に於ける駆動波形図である。 301・・・・・走査電極信号波形 302・・・・・信号電極信号波形 303・・・・・合成波形 304・・・・・光学応答 以  上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木 喜三部(他1名)101・・・
・・走査電極信号波形 102・・・・・信号電極信号波形 103・・・・・合成波形 104・・・・・光学応答 第2図は、本発明の実施例3における 形のタイミングチャート図である 201・・・・・走査電極信号波形 202・・・・・信号電極信号波形 203・・・・・合成波形 204・・・・・光学応答 駆動波
FIG. 1 is a timing chart of drive waveforms in Embodiment 1 of the present invention. FIG. 3 is a drive waveform diagram in a conventional example. 301...Scanning electrode signal waveform 302...Signal electrode signal waveform 303...Synthetic waveform 304...Optical response and above Applicant Seiko Epson Corporation Agent Patent attorney Yoshi Suzuki Part 3 (1 other person) 101...
...Scanning electrode signal waveform 102...Signal electrode signal waveform 103...Synthetic waveform 104...Optical response FIG. 2 is a timing chart diagram of the form according to the third embodiment of the present invention. 201...Scanning electrode signal waveform 202...Signal electrode signal waveform 203...Synthesized waveform 204...Optical response drive wave

Claims (2)

【特許請求の範囲】[Claims] (1)少なくとも走査電極の形成された基板と信号電極
の形成された基板間に、強誘電性液晶あるいは強誘電体
を挟持した素子に選択期間中あるいは選択期間の前に素
子を第一の状態にするパルス(リセットパルス)を印加
し、選択期間中に表示内容により素子を第二の状態にす
る実効値を有するパルス(セットパルス2)あるいは素
子を第二の状態にするしきい値以下のパルス(セットパ
ルス1)を印加する駆動方法に於て、セットパルス印加
後、素子の厚み方向に存在する電荷的な非対称性を打ち
消す極性で、波高値とパルス幅の積がセットパルス1の
波高値とパルス幅の積よりも小さいパルスを印加するこ
とを特徴とする液晶素子の駆動方法。
(1) An element having a ferroelectric liquid crystal or a ferroelectric substance sandwiched between at least a substrate on which a scanning electrode is formed and a substrate on which a signal electrode is formed is placed in the first state during or before the selection period. A pulse (reset pulse) is applied to set the element to the second state during the selection period, and a pulse (set pulse 2) having an effective value that puts the element into the second state or a pulse below the threshold value that puts the element into the second state is applied depending on the display content during the selection period. In a driving method that applies a pulse (set pulse 1), after applying the set pulse, the product of the peak value and the pulse width is the wave of set pulse 1, with a polarity that cancels out the charge asymmetry that exists in the thickness direction of the element. A method for driving a liquid crystal element, characterized by applying a pulse smaller than the product of a high value and a pulse width.
(2)リセットパルスを印加する前に、波形全体を1フ
レーム内で電荷的に中和するパルスを印加する事を特徴
とする特許請求の範囲第1項記載の電気光学素子の駆動
方法。
(2) The method for driving an electro-optical element according to claim 1, characterized in that, before applying the reset pulse, a pulse is applied that charges neutralizes the entire waveform within one frame.
JP9030189A 1989-04-10 1989-04-10 Driving method for liquid crystal element Pending JPH02267523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9030189A JPH02267523A (en) 1989-04-10 1989-04-10 Driving method for liquid crystal element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9030189A JPH02267523A (en) 1989-04-10 1989-04-10 Driving method for liquid crystal element

Publications (1)

Publication Number Publication Date
JPH02267523A true JPH02267523A (en) 1990-11-01

Family

ID=13994716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9030189A Pending JPH02267523A (en) 1989-04-10 1989-04-10 Driving method for liquid crystal element

Country Status (1)

Country Link
JP (1) JPH02267523A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5646755A (en) * 1992-12-28 1997-07-08 Canon Kabushiki Kaisha Method and apparatus for ferroelectric liquid crystal display having gradational display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5646755A (en) * 1992-12-28 1997-07-08 Canon Kabushiki Kaisha Method and apparatus for ferroelectric liquid crystal display having gradational display

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