JPH02266672A - Image pickup device - Google Patents

Image pickup device

Info

Publication number
JPH02266672A
JPH02266672A JP1087803A JP8780389A JPH02266672A JP H02266672 A JPH02266672 A JP H02266672A JP 1087803 A JP1087803 A JP 1087803A JP 8780389 A JP8780389 A JP 8780389A JP H02266672 A JPH02266672 A JP H02266672A
Authority
JP
Japan
Prior art keywords
signal
field
line
aperture compensation
vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1087803A
Other languages
Japanese (ja)
Other versions
JP2979549B2 (en
Inventor
Toshihiko Mimura
敏彦 三村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP1087803A priority Critical patent/JP2979549B2/en
Publication of JPH02266672A publication Critical patent/JPH02266672A/en
Application granted granted Critical
Publication of JP2979549B2 publication Critical patent/JP2979549B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Picture Signal Circuits (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Color Television Image Signal Generators (AREA)

Abstract

PURPOSE:To constitute an in-field differentiating vertical aperture compensation circuit and an inter-field quadratic differentiating compensation circuit with less number of line memories than that of conventional circuits by using an output of the line memory storing an interpolation signal so as to apply vertical aperture compensation. CONSTITUTION:A vertical low pass filter(LPF) 24 uses a delay signal through line memories 20, 22 to form interpolation signal and the formed interpolation signal is stored in a line memory 26 for interpolation data. Since the line memory 26 for forming the interpolation signal is used for one line delay for vertical aperture compensation, the number of line memories in use is decreased. Thus, an in-field first order derivative vertical aperture compensation circuit and an inter-field second order derivative compensation circuit are constituted with less number of line memories than that of conventional circuits.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、画素配列が二次元オフセット配置になってい
る固体撮像装置を用いた撮像装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an imaging device using a solid-state imaging device in which a pixel array is arranged in a two-dimensional offset arrangement.

[従来の技術] 従来から、固体撮像素子を用いる撮像装置が、ビデオ・
カメラ、スチル・ビデオ・カメラなどで広く用いられて
いる。これらに使用される固体撮像素子としては当初、
正方形又は長方形の受光素子がマトリクス状に規則正し
く並んだ感光部を具備するものが用いられたが、近年、
画質向上の要求が高まり、固体撮像素子の高画質化が図
られ、第2図に示すように、各画素(受光素子)を夏型
又は六角形などにし、各画素の重心が二次元オフセット
構造になるようにした固体撮像素子が開発された。この
画素配置により、受光面積の縮小(即ち感度の低下)を
抑えつつ、画質を向上させることができる。
[Prior Art] Traditionally, imaging devices using solid-state imaging devices have been used for video and
Widely used in cameras, still video cameras, etc. Initially, the solid-state image sensors used in these applications were
A device with a photosensitive area in which square or rectangular photodetectors were regularly arranged in a matrix was used, but in recent years,
As the demand for improved image quality increased, the image quality of solid-state image sensors was improved, and as shown in Figure 2, each pixel (light receiving element) was made into a summer shape or hexagonal shape, and the center of gravity of each pixel was constructed with a two-dimensional offset structure. A solid-state image sensor has been developed. This pixel arrangement makes it possible to improve image quality while suppressing a reduction in light-receiving area (that is, a decrease in sensitivity).

しかし第2図の撮像素子では、矢印(実線又は破線)で
示すように、水平方向線上でジグザグに信号を読み出し
てTV信号を形成すると、モアレを発生するので、非サ
ンプル点(例えば、○又は・をサンプル点とした場合の
、口の点)の信号を補間する必要があり、更には、水平
方向で帯域制限をするために、巨大な信号処理部を有す
る二次元フィルタを設ける必要がある。また、上記補間
処理のために、多数のライン・メモリ又はフレーム・メ
モリが必要になる。
However, in the image sensor shown in FIG. 2, if the signal is read out in a zigzag manner on a horizontal line to form a TV signal as shown by the arrow (solid line or broken line), moiré will occur, so non-sample points (for example, ○ or It is necessary to interpolate the signal of the mouth point) when ・ is the sample point, and furthermore, it is necessary to provide a two-dimensional filter with a huge signal processing section in order to limit the band in the horizontal direction. . Furthermore, the interpolation process requires a large number of line memories or frame memories.

[発明が解決しようとする課題] 上記従来例で垂直アパーチャ補償を行おうとすると、そ
のためのライン・メモリが必要になり、上記補間処理の
ためのライン・メモリも加えると、かなり多数のラリン
・メモリが必要になる。IC化を考える場合、このよう
に多数のライン・メモリが必要になることは問題である
[Problems to be Solved by the Invention] When attempting to perform vertical aperture compensation in the conventional example described above, a line memory for that purpose is required, and when the line memory for the above interpolation processing is added, a considerably large number of lalin memories are required. is required. When considering IC implementation, the necessity of such a large number of line memories is a problem.

そこで、本発明はより少ないライン・メモリで済む撮像
装置を提示することを目的とする。
Therefore, it is an object of the present invention to provide an imaging device that requires less line memory.

[課題を解決するための手段] 本発明に係る撮像装置は、感光部の光電変換素子が二次
元的にオフセット配置になっている撮像素子を具備し、
当該感光部の、隣接する2行の光電変換素子の信号をジ
グザグに読み出し、メモリ手段に一時格納して所定の補
間信号を形成し、第1フィールドと第2フィールドとで
はジグザグ読出しの上下の順番を異ならしめる撮像装置
であって、補間信号を保持するメモリ手段の出力を使つ
て垂直アパーチャ補償を行うことを特徴としている。
[Means for Solving the Problems] An imaging device according to the present invention includes an imaging device in which a photoelectric conversion element of a photosensitive portion is arranged two-dimensionally offset,
The signals of the photoelectric conversion elements in two adjacent rows of the photosensitive section are read out in a zigzag manner and temporarily stored in a memory means to form a predetermined interpolated signal. This imaging device is characterized in that it performs vertical aperture compensation using the output of a memory means that holds an interpolation signal.

[作用] 上記手段により、補間信号用の上記メモリ手段を垂直ア
パーチャ補償用の1ライン遅延にも利用するので、その
分、メモリ手段を少なくできる。
[Operation] With the above means, the memory means for interpolation signals is also used for one line delay for vertical aperture compensation, so the number of memory means can be reduced accordingly.

即ち、フィールド内−次微分垂直アパーチャ補償回路や
フィールド間二次微分補償回路を、従来より少ないライ
ン・メモリで実現できる。
That is, an intra-field-order differential vertical aperture compensation circuit and an inter-field second-order differential compensation circuit can be realized with fewer line memories than conventional ones.

[実施例] 以下、図面を参照して本発明の詳細な説明する。[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例の構成ブロック図である。1
0は、感光部の受光素子配列が第2図に示すように二次
元オフセット構造になっている撮像素子であり、R,G
、Bの3つの色信号を出力する。撮像素子10は、水平
方向に3n(nは正の整数)個、垂直方向にm(正の整
数)個の受光素子を具備するものとする。11は回路各
部を同期動作させるためのシステム信号を発生するシス
テム信号発生回路(S S G)である。スイッチ12
は撮像素子10の3つの出力を、第2図の矢印(実線又
は破線)の順序で順次選択する。以下、このような読出
しをジグザグ読出しと呼ぶ。このようにジグザグ読出し
された信号はサンプル・ホールド回路14でサンプル・
ホールドされ、A/D変換器16によりディジタル化さ
れる。なお、A/D変換器16において、同時にガンマ
補正やホワイト・バランスが行われる。
FIG. 1 is a block diagram of an embodiment of the present invention. 1
0 is an image sensor in which the light-receiving element array of the photosensitive part has a two-dimensional offset structure as shown in FIG.
, B are output. It is assumed that the image sensor 10 includes 3n (n is a positive integer) light receiving elements in the horizontal direction and m (positive integer) light receiving elements in the vertical direction. Reference numeral 11 denotes a system signal generation circuit (SSG) that generates a system signal for synchronously operating each part of the circuit. switch 12
The three outputs of the image sensor 10 are sequentially selected in the order indicated by the arrows (solid or broken lines) in FIG. Hereinafter, such readout will be referred to as zigzag readout. The signal read out in a zigzag manner in this way is sampled and held in the sample/hold circuit 14.
The signal is held and digitized by the A/D converter 16. Note that gamma correction and white balance are performed at the same time in the A/D converter 16.

A/D変換器16によるディジタル信号は、スイッチ1
8により、感光部の上側の行の信号がライン・メモリ2
0に印加され、下側の行の信号がライン・メモリ22に
印加される。垂直ローパス・フィルタ(LPF)24は
、ライン・メモリ20.22による遅延信号を使って、
補間信号を形成する。例えば、第3図は第2フィールド
の場合であるが、信号◎と信号Oとから補間信号△を形
成し、これによりF2.Flを作成する。形成された補
間信号は、補間データ用のライン・メモリ26に格納さ
れる。
The digital signal from the A/D converter 16 is sent to the switch 1
8, the signal in the upper row of the photosensitive area is transferred to the line memory 2.
0 and the lower row signal is applied to line memory 22. Vertical low-pass filter (LPF) 24 uses the delayed signal from line memory 20.22 to
Form an interpolated signal. For example, in the case of the second field shown in FIG. 3, an interpolated signal △ is formed from the signal ◎ and the signal O, and thereby F2. Create Fl. The formed interpolated signal is stored in a line memory 26 for interpolated data.

いま、スイッチ18の出力に信号Oがきているとき、信
号◎はまだ、ライン・メモリ20又は22に残っている
。そこで、垂直LPF24で合成された信号の内、信号
口を、F2の出力時に半分だけ蓄えておけば、垂直LP
F24之がF2°のとき、F2を再合成でき、この2本
の信号うぇつを用いれば、フィールド内の走査線間で垂
直アパーチャ補償を行える。即ち、36がその垂直アパ
ーチャ補償回路である。
Now, when the signal O is coming to the output of the switch 18, the signal ◎ still remains in the line memory 20 or 22. Therefore, if only half of the signal output of the signal synthesized by the vertical LPF 24 is stored when outputting F2, the vertical LPF
When F24 is F2°, F2 can be recombined, and by using these two signals, vertical aperture compensation can be performed between scanning lines within a field. That is, 36 is the vertical aperture compensation circuit.

垂直アパーチャ補償回路36の出力は輝度信号用LPF
38に印加される。LPF38はFIR(有限インパル
ス応答)型のディジタル・フィルタであり、ここで、水
平方向の帯域制限を受け、D/A変換器40及びLPF
42を介して、輝度信号が外部に出力される。
The output of the vertical aperture compensation circuit 36 is a luminance signal LPF.
38. The LPF 38 is a FIR (Finite Impulse Response) type digital filter, which is subjected to horizontal band limitation and is connected to the D/A converter 40 and the LPF.
A luminance signal is output to the outside via 42.

色信号処理に関しては、スイッチ32により垂直アパー
チャ補償していない信号を抜き取り、色信号処理回路4
4でRGB信号を色差信号R−Y。
Regarding color signal processing, the switch 32 extracts the signal that has not been subjected to vertical aperture compensation, and the signal is sent to the color signal processing circuit 4.
4 converts the RGB signal into a color difference signal RY.

B−Yに変換し、同時に、水平方向にも帯域制限する。The signal is converted to B-Y, and at the same time, the band is limited in the horizontal direction as well.

この後は、輝度信号と同様に、D/A変換器46.47
及びLPF48.49を介して外部に色差信号R−Y、
B−Yを出力する。
After this, similarly to the luminance signal, the D/A converter 46.47
and a color difference signal R-Y to the outside via LPF48.49.
Output B-Y.

第3図を参照して、第2フィールド時の動作を説明した
が、第1フィールドでは、第2フィールドと上下逆順の
ジグザグ読出しを行う。第1フィールドの読出し及び垂
直アパーチャ補償の関係をを第4図に示す。
The operation in the second field has been described with reference to FIG. 3. In the first field, zigzag reading is performed in the reverse order of the second field. The relationship between first field readout and vertical aperture compensation is shown in FIG.

第5図は本発明の別の実施例の構成ブロック図を示し、
第6図は第1フィールドの読出し順序及びフィールド間
二次微分アパーチャ補償を示す。
FIG. 5 shows a block diagram of another embodiment of the present invention,
FIG. 6 shows the readout order of the first field and inter-field second-order differential aperture compensation.

第1図と同じ構成要素には同じ符号を付しである。The same components as in FIG. 1 are given the same reference numerals.

5oはフィールド専用の撮像素子、52はシステム信号
発生回路、56が第1図のライン・メモリ26に対応す
る補間データ格納用のライン・メモリである。ライン・
メモリ20.22への振り分けまでの動作は、第1図の
場合と同様である。第6図に示すように、Fl信号に対
してF2’信号を、F1信号の作成時に半分ノライン・
メモリ容量で作成できるので、F1信号と同時に作られ
るF2信号を利用すれば、フィールド間の垂直二次微分
アパーチャ補償を行える。第5図の垂直アパーチャ補償
回路56はその垂直二次微分アパーチャ補償を行ってい
る。
Reference numeral 5o designates a field-only image pickup device, 52 a system signal generation circuit, and 56 a line memory for storing interpolated data corresponding to the line memory 26 in FIG. line·
The operation up to allocation to the memories 20 and 22 is the same as in the case of FIG. As shown in Fig. 6, when creating the F1 signal, the F2' signal is set to a half
Since it can be created using a memory capacity, vertical second-order differential aperture compensation between fields can be performed by using the F2 signal that is created simultaneously with the F1 signal. The vertical aperture compensation circuit 56 in FIG. 5 performs vertical second-order differential aperture compensation.

第5図の構成はフィールド専用の撮像装置であるが、第
1図の実施例と同様に、上下逆のジグザグ読出しを行え
ば、第2フィールドに対しても垂直二次微分アパーチャ
補償を行える。また、撮像素子50において、ジグザグ
読出し又は上下逆のジグザグ読出しが行えない場合には
、その出力をA/D変換した後、−旦フレーム・メモリ
に格納すればよく、本発明は、撮像素子自体の信号読出
し方法によって限定されない。
Although the configuration shown in FIG. 5 is a field-only image pickup apparatus, vertical second-order differential aperture compensation can also be performed for the second field by performing upside-down zigzag reading as in the embodiment shown in FIG. Further, in the case where the image sensor 50 cannot perform zigzag readout or upside down zigzag readout, the output may be A/D converted and then stored in the frame memory. The present invention is not limited by the signal reading method.

[発明の効果コ 以上の説明から容易に理解できるように、本発明によれ
ば、より少ないメモリ手段で、垂直アパーチャ補償回路
を実現でき、回路規模を小さくし、消費電力、製造コス
トの低域を図ることができる。
[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, a vertical aperture compensation circuit can be realized with less memory means, the circuit size can be reduced, and power consumption and manufacturing cost can be reduced. can be achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の構成ブロック図、第2図は
撮像素子の感光部の画素配置の説明図、第3図は第1図
の第2フィールドのフィールド内アパーチャ補償の説明
図、第4図は第1フィールドのフィールド内アパーチャ
補償の説明図、第5図は本発明の別の実施例の構成ブロ
ック図、第6図は第5図の第1フィールドのフィールド
間二次微分アパーチャ補償の説明図である。 10.50:撮像素子 11,52ニジステム信号発生
回路 20,22ニライン・メモリ 24:垂直LPF
  26,56+補間データ用ライン・メモリ 60:
垂直アパーチャ補償回路第 図 第 図
FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the pixel arrangement of the photosensitive part of the image sensor, and FIG. 3 is an explanatory diagram of intra-field aperture compensation of the second field in FIG. , FIG. 4 is an explanatory diagram of intra-field aperture compensation of the first field, FIG. 5 is a block diagram of another embodiment of the present invention, and FIG. 6 is an illustration of the inter-field quadratic differential of the first field of FIG. FIG. 3 is an explanatory diagram of aperture compensation. 10.50: Image sensor 11, 52 System signal generation circuit 20, 22 Line memory 24: Vertical LPF
26, 56 + line memory for interpolated data 60:
Vertical aperture compensation circuit diagram

Claims (1)

【特許請求の範囲】[Claims] 感光部の光電変換素子が二次元的にオフセット配置にな
っている撮像素子を具備し、当該感光部の、隣接する2
行の光電変換素子の信号をジグザグに読み出し、メモリ
手段に一時格納して所定の補間信号を形成し、第1フィ
ールドと第2フィールドとではジグザグ読出しの上下の
順番を異ならしめる撮像装置であって、補間信号を保持
するメモリ手段の出力を使って垂直アパーチャ補償を行
うことを特徴とする撮像装置。
The photosensitive section is equipped with an image sensor in which the photoelectric conversion elements are two-dimensionally offset, and two adjacent photoelectric conversion elements of the photosensitive section are provided.
The imaging apparatus reads signals from photoelectric conversion elements in a row in a zigzag manner, temporarily stores them in a memory means to form a predetermined interpolated signal, and makes the vertical order of the zigzag readout different between the first field and the second field. , an imaging apparatus characterized in that vertical aperture compensation is performed using an output of a memory means holding an interpolation signal.
JP1087803A 1989-04-06 1989-04-06 Imaging device Expired - Fee Related JP2979549B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1087803A JP2979549B2 (en) 1989-04-06 1989-04-06 Imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1087803A JP2979549B2 (en) 1989-04-06 1989-04-06 Imaging device

Publications (2)

Publication Number Publication Date
JPH02266672A true JPH02266672A (en) 1990-10-31
JP2979549B2 JP2979549B2 (en) 1999-11-15

Family

ID=13925140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1087803A Expired - Fee Related JP2979549B2 (en) 1989-04-06 1989-04-06 Imaging device

Country Status (1)

Country Link
JP (1) JP2979549B2 (en)

Also Published As

Publication number Publication date
JP2979549B2 (en) 1999-11-15

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